1 | /* |
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2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | #ifndef IMX_GPCREG_H |
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10 | #define IMX_GPCREG_H |
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11 | |
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12 | #include <bsp/utility.h> |
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13 | |
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14 | typedef struct { |
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15 | uint32_t lpcr_a7_bsc; |
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16 | uint32_t lpcr_a7_ad; |
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17 | uint32_t lpcr_m4; |
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18 | uint32_t reserved_0c[2]; |
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19 | uint32_t slpcr; |
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20 | uint32_t reserved_18[2]; |
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21 | uint32_t mlpcr; |
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22 | uint32_t pgc_ack_sel_a7; |
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23 | uint32_t pgc_ack_sel_m4; |
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24 | uint32_t misc; |
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25 | uint32_t imr1_core0_a7; |
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26 | uint32_t imr2_core0_a7; |
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27 | uint32_t imr3_core0_a7; |
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28 | uint32_t imr4_core0_a7; |
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29 | uint32_t imr1_core1_a7; |
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30 | uint32_t imr2_core1_a7; |
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31 | uint32_t imr3_core1_a7; |
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32 | uint32_t imr4_core1_a7; |
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33 | uint32_t imr1_m4; |
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34 | uint32_t imr2_m4; |
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35 | uint32_t imr3_m4; |
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36 | uint32_t imr4_m4; |
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37 | uint32_t reserved_60[4]; |
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38 | uint32_t isr1_a7; |
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39 | uint32_t isr2_a7; |
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40 | uint32_t isr3_a7; |
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41 | uint32_t isr4_a7; |
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42 | uint32_t isr1_m4; |
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43 | uint32_t isr2_m4; |
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44 | uint32_t isr3_m4; |
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45 | uint32_t isr4_m4; |
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46 | uint32_t reserved_90[8]; |
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47 | uint32_t slt0_cfg; |
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48 | uint32_t slt1_cfg; |
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49 | uint32_t slt2_cfg; |
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50 | uint32_t slt3_cfg; |
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51 | uint32_t slt4_cfg; |
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52 | uint32_t slt5_cfg; |
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53 | uint32_t slt6_cfg; |
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54 | uint32_t slt7_cfg; |
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55 | uint32_t slt8_cfg; |
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56 | uint32_t slt9_cfg; |
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57 | uint32_t reserved_d8[5]; |
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58 | uint32_t pgc_cpu_mapping; |
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59 | #define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2) |
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60 | #define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1) |
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61 | #define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0) |
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62 | #define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4) |
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63 | #define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3) |
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64 | #define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2) |
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65 | #define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1) |
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66 | #define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0) |
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67 | uint32_t cpu_pgc_sw_pup_req; |
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68 | uint32_t reserved_f4; |
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69 | uint32_t pu_pgc_sw_pup_req; |
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70 | uint32_t cpu_pgc_sw_pdn_req; |
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71 | uint32_t reserved_100; |
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72 | uint32_t pu_pgc_sw_pdn_req; |
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73 | uint32_t reserved_108[10]; |
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74 | uint32_t cpu_pgc_pup_status1; |
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75 | uint32_t a7_mix_pgc_pup_status0; |
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76 | uint32_t a7_mix_pgc_pup_status1; |
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77 | uint32_t a7_mix_pgc_pup_status2; |
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78 | uint32_t m4_mix_pgc_pup_status0; |
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79 | uint32_t m4_mix_pgc_pup_status1; |
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80 | uint32_t m4_mix_pgc_pup_status2; |
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81 | uint32_t a7_pu_pgc_pup_status0; |
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82 | uint32_t a7_pu_pgc_pup_status1; |
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83 | uint32_t a7_pu_pgc_pup_status2; |
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84 | uint32_t m4_pu_pgc_pup_status0; |
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85 | uint32_t m4_pu_pgc_pup_status1; |
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86 | uint32_t m4_pu_pgc_pup_status2; |
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87 | uint32_t reserved_164[3]; |
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88 | uint32_t cpu_pgc_pdn_status1; |
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89 | uint32_t reserved_174[6]; |
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90 | uint32_t a7_pu_pgc_pdn_status0; |
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91 | uint32_t a7_pu_pgc_pdn_status1; |
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92 | uint32_t a7_pu_pgc_pdn_status2; |
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93 | uint32_t m4_pu_pgc_pdn_status0; |
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94 | uint32_t m4_pu_pgc_pdn_status1; |
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95 | uint32_t m4_pu_pgc_pdn_status2; |
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96 | uint32_t reserved_1a4[3]; |
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97 | uint32_t a7_mix_pdn_flg; |
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98 | uint32_t a7_pu_pdn_flg; |
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99 | uint32_t m4_mix_pdn_flg; |
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100 | uint32_t m4_pu_pdn_flg; |
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101 | #define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29) |
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102 | #define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29) |
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103 | #define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) |
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104 | #define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21) |
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105 | #define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21) |
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106 | #define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) |
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107 | #define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13) |
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108 | #define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13) |
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109 | #define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13) |
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110 | #define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6) |
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111 | #define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6) |
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112 | #define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6) |
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113 | #define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0) |
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114 | uint32_t reserved_1c0[400]; |
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115 | uint32_t pgc_a7core0_ctrl; |
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116 | uint32_t pgc_a7core0_pupscr; |
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117 | uint32_t pgc_a7core0_pdnscr; |
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118 | uint32_t pgc_a7core0_sr; |
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119 | uint32_t reserved_810[12]; |
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120 | uint32_t pgc_a7core1_ctrl; |
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121 | uint32_t pgc_a7core1_pupscr; |
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122 | uint32_t pgc_a7core1_pdnscr; |
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123 | uint32_t pgc_a7core1_sr; |
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124 | uint32_t reserved_850[12]; |
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125 | uint32_t pgc_a7scu_ctrl; |
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126 | uint32_t pgc_a7scu_pupscr; |
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127 | uint32_t pgc_a7scu_pdnscr; |
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128 | uint32_t pgc_a7scu_sr; |
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129 | uint32_t pgc_scu_auxsw; |
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130 | uint32_t reserved_894[11]; |
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131 | uint32_t pgc_mix_ctrl; |
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132 | uint32_t pgc_mix_pupscr; |
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133 | uint32_t pgc_mix_pdnscr; |
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134 | uint32_t pgc_mix_sr; |
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135 | uint32_t reserved_8d0[12]; |
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136 | uint32_t pgc_mipi_ctrl; |
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137 | uint32_t pgc_mipi_pupscr; |
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138 | uint32_t pgc_mipi_pdnscr; |
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139 | uint32_t pgc_mipi_sr; |
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140 | uint32_t reserved_910[12]; |
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141 | uint32_t pgc_pcie_ctrl; |
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142 | uint32_t pgc_pcie_pupscr; |
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143 | uint32_t pgc_pcie_pdnscr; |
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144 | uint32_t pgc_pcie_sr; |
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145 | uint32_t reserved_950[176]; |
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146 | uint32_t pgc_mipi_auxsw; |
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147 | uint32_t reserved_c14[15]; |
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148 | uint32_t pgc_pcie_auxsw; |
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149 | uint32_t reserved_c54[43]; |
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150 | uint32_t pgc_hsic_ctrl; |
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151 | uint32_t pgc_hsic_pupscr; |
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152 | uint32_t pgc_hsic_pdnscr; |
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153 | uint32_t pgc_hsic_sr; |
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154 | } imx_gpc; |
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155 | |
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156 | #endif /* IMX_GPCREG_H */ |
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