source: rtems/bsps/arm/imx/include/arm/freescale/imx/imx_gpcreg.h @ ba619b7f

Last change on this file since ba619b7f was ba619b7f, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 21:38:20

bsps/arm/: Scripted embedded brains header file clean up

Updates #4625.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 * Copyright (c) 2017 embedded brains GmbH.  All rights reserved.
3 *
4 * The license and distribution terms for this file may be
5 * found in the file LICENSE in this distribution or at
6 * http://www.rtems.org/license/LICENSE.
7 */
8
9#ifndef IMX_GPCREG_H
10#define IMX_GPCREG_H
11
12#include <bsp/utility.h>
13
14typedef struct {
15        uint32_t lpcr_a7_bsc;
16        uint32_t lpcr_a7_ad;
17        uint32_t lpcr_m4;
18        uint32_t reserved_0c[2];
19        uint32_t slpcr;
20        uint32_t reserved_18[2];
21        uint32_t mlpcr;
22        uint32_t pgc_ack_sel_a7;
23        uint32_t pgc_ack_sel_m4;
24        uint32_t misc;
25        uint32_t imr1_core0_a7;
26        uint32_t imr2_core0_a7;
27        uint32_t imr3_core0_a7;
28        uint32_t imr4_core0_a7;
29        uint32_t imr1_core1_a7;
30        uint32_t imr2_core1_a7;
31        uint32_t imr3_core1_a7;
32        uint32_t imr4_core1_a7;
33        uint32_t imr1_m4;
34        uint32_t imr2_m4;
35        uint32_t imr3_m4;
36        uint32_t imr4_m4;
37        uint32_t reserved_60[4];
38        uint32_t isr1_a7;
39        uint32_t isr2_a7;
40        uint32_t isr3_a7;
41        uint32_t isr4_a7;
42        uint32_t isr1_m4;
43        uint32_t isr2_m4;
44        uint32_t isr3_m4;
45        uint32_t isr4_m4;
46        uint32_t reserved_90[8];
47        uint32_t slt0_cfg;
48        uint32_t slt1_cfg;
49        uint32_t slt2_cfg;
50        uint32_t slt3_cfg;
51        uint32_t slt4_cfg;
52        uint32_t slt5_cfg;
53        uint32_t slt6_cfg;
54        uint32_t slt7_cfg;
55        uint32_t slt8_cfg;
56        uint32_t slt9_cfg;
57        uint32_t reserved_d8[5];
58        uint32_t pgc_cpu_mapping;
59#define IMX_GPC_CPU_PGC_SCU_A7 BSP_BIT32(2)
60#define IMX_GPC_CPU_PGC_CORE1_A7 BSP_BIT32(1)
61#define IMX_GPC_CPU_PGC_CORE0_A7 BSP_BIT32(0)
62#define IMX_GPC_PU_PGC_USB_HSIC_PHY BSP_BIT32(4)
63#define IMX_GPC_PU_PGC_USB_OTG2_PHY BSP_BIT32(3)
64#define IMX_GPC_PU_PGC_USB_OTG1_PHY BSP_BIT32(2)
65#define IMX_GPC_PU_PGC_PCIE_PHY BSP_BIT32(1)
66#define IMX_GPC_PU_PGC_MIPI_PHY BSP_BIT32(0)
67        uint32_t cpu_pgc_sw_pup_req;
68        uint32_t reserved_f4;
69        uint32_t pu_pgc_sw_pup_req;
70        uint32_t cpu_pgc_sw_pdn_req;
71        uint32_t reserved_100;
72        uint32_t pu_pgc_sw_pdn_req;
73        uint32_t reserved_108[10];
74        uint32_t cpu_pgc_pup_status1;
75        uint32_t a7_mix_pgc_pup_status0;
76        uint32_t a7_mix_pgc_pup_status1;
77        uint32_t a7_mix_pgc_pup_status2;
78        uint32_t m4_mix_pgc_pup_status0;
79        uint32_t m4_mix_pgc_pup_status1;
80        uint32_t m4_mix_pgc_pup_status2;
81        uint32_t a7_pu_pgc_pup_status0;
82        uint32_t a7_pu_pgc_pup_status1;
83        uint32_t a7_pu_pgc_pup_status2;
84        uint32_t m4_pu_pgc_pup_status0;
85        uint32_t m4_pu_pgc_pup_status1;
86        uint32_t m4_pu_pgc_pup_status2;
87        uint32_t reserved_164[3];
88        uint32_t cpu_pgc_pdn_status1;
89        uint32_t reserved_174[6];
90        uint32_t a7_pu_pgc_pdn_status0;
91        uint32_t a7_pu_pgc_pdn_status1;
92        uint32_t a7_pu_pgc_pdn_status2;
93        uint32_t m4_pu_pgc_pdn_status0;
94        uint32_t m4_pu_pgc_pdn_status1;
95        uint32_t m4_pu_pgc_pdn_status2;
96        uint32_t reserved_1a4[3];
97        uint32_t a7_mix_pdn_flg;
98        uint32_t a7_pu_pdn_flg;
99        uint32_t m4_mix_pdn_flg;
100        uint32_t m4_pu_pdn_flg;
101#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(val) BSP_FLD32(val, 24, 29)
102#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_GET(reg) BSP_FLD32GET(reg, 24, 29)
103#define IMX_GPC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29)
104#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR(val) BSP_FLD32(val, 16, 21)
105#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_GET(reg) BSP_FLD32GET(reg, 16, 21)
106#define IMX_GPC_PGC_CTRL_L2RETN_TCD1_TDR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21)
107#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1(val) BSP_FLD32(val, 8, 13)
108#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_GET(reg) BSP_FLD32GET(reg, 8, 13)
109#define IMX_GPC_PGC_CTRL_DFTRAM_TCD1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
110#define IMX_GPC_PGC_CTRL_L2RSTDIS(val) BSP_FLD32(val, 1, 6)
111#define IMX_GPC_PGC_CTRL_L2RSTDIS_GET(reg) BSP_FLD32GET(reg, 1, 6)
112#define IMX_GPC_PGC_CTRL_L2RSTDIS_SET(reg, val) BSP_FLD32SET(reg, val, 1, 6)
113#define IMX_GPC_PGC_CTRL_PCR BSP_BIT32(0)
114        uint32_t reserved_1c0[400];
115        uint32_t pgc_a7core0_ctrl;
116        uint32_t pgc_a7core0_pupscr;
117        uint32_t pgc_a7core0_pdnscr;
118        uint32_t pgc_a7core0_sr;
119        uint32_t reserved_810[12];
120        uint32_t pgc_a7core1_ctrl;
121        uint32_t pgc_a7core1_pupscr;
122        uint32_t pgc_a7core1_pdnscr;
123        uint32_t pgc_a7core1_sr;
124        uint32_t reserved_850[12];
125        uint32_t pgc_a7scu_ctrl;
126        uint32_t pgc_a7scu_pupscr;
127        uint32_t pgc_a7scu_pdnscr;
128        uint32_t pgc_a7scu_sr;
129        uint32_t pgc_scu_auxsw;
130        uint32_t reserved_894[11];
131        uint32_t pgc_mix_ctrl;
132        uint32_t pgc_mix_pupscr;
133        uint32_t pgc_mix_pdnscr;
134        uint32_t pgc_mix_sr;
135        uint32_t reserved_8d0[12];
136        uint32_t pgc_mipi_ctrl;
137        uint32_t pgc_mipi_pupscr;
138        uint32_t pgc_mipi_pdnscr;
139        uint32_t pgc_mipi_sr;
140        uint32_t reserved_910[12];
141        uint32_t pgc_pcie_ctrl;
142        uint32_t pgc_pcie_pupscr;
143        uint32_t pgc_pcie_pdnscr;
144        uint32_t pgc_pcie_sr;
145        uint32_t reserved_950[176];
146        uint32_t pgc_mipi_auxsw;
147        uint32_t reserved_c14[15];
148        uint32_t pgc_pcie_auxsw;
149        uint32_t reserved_c54[43];
150        uint32_t pgc_hsic_ctrl;
151        uint32_t pgc_hsic_pupscr;
152        uint32_t pgc_hsic_pdnscr;
153        uint32_t pgc_hsic_sr;
154} imx_gpc;
155
156#endif /* IMX_GPCREG_H */
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