[4bf2ce31] | 1 | /* |
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| 2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.org/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef IMX_ECSPIREG_H |
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| 16 | #define IMX_ECSPIREG_H |
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| 17 | |
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| 18 | #include <bsp/utility.h> |
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| 19 | |
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| 20 | typedef struct { |
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| 21 | uint32_t rxdata; |
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| 22 | uint32_t txdata; |
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| 23 | uint32_t conreg; |
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| 24 | #define IMX_ECSPI_CONREG_BURST_LENGTH(val) BSP_FLD32(val, 20, 31) |
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| 25 | #define IMX_ECSPI_CONREG_BURST_LENGTH_GET(reg) BSP_FLD32GET(reg, 20, 31) |
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| 26 | #define IMX_ECSPI_CONREG_BURST_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 20, 31) |
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| 27 | #define IMX_ECSPI_CONREG_CHANNEL_SELECT(val) BSP_FLD32(val, 18, 19) |
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| 28 | #define IMX_ECSPI_CONREG_CHANNEL_SELECT_GET(reg) BSP_FLD32GET(reg, 18, 19) |
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| 29 | #define IMX_ECSPI_CONREG_CHANNEL_SELECT_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) |
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| 30 | #define IMX_ECSPI_CONREG_DRCTL(val) BSP_FLD32(val, 16, 17) |
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| 31 | #define IMX_ECSPI_CONREG_DRCTL_GET(reg) BSP_FLD32GET(reg, 16, 17) |
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| 32 | #define IMX_ECSPI_CONREG_DRCTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) |
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| 33 | #define IMX_ECSPI_CONREG_PRE_DIVIDER(val) BSP_FLD32(val, 12, 15) |
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| 34 | #define IMX_ECSPI_CONREG_PRE_DIVIDER_GET(reg) BSP_FLD32GET(reg, 12, 15) |
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| 35 | #define IMX_ECSPI_CONREG_PRE_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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| 36 | #define IMX_ECSPI_CONREG_POST_DIVIDER(val) BSP_FLD32(val, 8, 11) |
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| 37 | #define IMX_ECSPI_CONREG_POST_DIVIDER_GET(reg) BSP_FLD32GET(reg, 8, 11) |
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| 38 | #define IMX_ECSPI_CONREG_POST_DIVIDER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) |
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| 39 | #define IMX_ECSPI_CONREG_CHANNEL_MODE(val) BSP_FLD32(val, 4, 7) |
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| 40 | #define IMX_ECSPI_CONREG_CHANNEL_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) |
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| 41 | #define IMX_ECSPI_CONREG_CHANNEL_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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| 42 | #define IMX_ECSPI_CONREG_SMC BSP_BIT32(3) |
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| 43 | #define IMX_ECSPI_CONREG_XCH BSP_BIT32(2) |
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| 44 | #define IMX_ECSPI_CONREG_HT BSP_BIT32(1) |
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| 45 | #define IMX_ECSPI_CONREG_EN BSP_BIT32(0) |
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| 46 | uint32_t configreg; |
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| 47 | #define IMX_ECSPI_CONFIGREG_HT_LENGTH(val) BSP_FLD32(val, 24, 28) |
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| 48 | #define IMX_ECSPI_CONFIGREG_HT_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 28) |
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| 49 | #define IMX_ECSPI_CONFIGREG_HT_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) |
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| 50 | #define IMX_ECSPI_CONFIGREG_SCLK_CTL(val) BSP_FLD32(val, 20, 23) |
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| 51 | #define IMX_ECSPI_CONFIGREG_SCLK_CTL_GET(reg) BSP_FLD32GET(reg, 20, 23) |
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| 52 | #define IMX_ECSPI_CONFIGREG_SCLK_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) |
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| 53 | #define IMX_ECSPI_CONFIGREG_DATA_CTL(val) BSP_FLD32(val, 16, 19) |
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| 54 | #define IMX_ECSPI_CONFIGREG_DATA_CTL_GET(reg) BSP_FLD32GET(reg, 16, 19) |
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| 55 | #define IMX_ECSPI_CONFIGREG_DATA_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) |
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| 56 | #define IMX_ECSPI_CONFIGREG_SS_POL(val) BSP_FLD32(val, 12, 15) |
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| 57 | #define IMX_ECSPI_CONFIGREG_SS_POL_GET(reg) BSP_FLD32GET(reg, 12, 15) |
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| 58 | #define IMX_ECSPI_CONFIGREG_SS_POL_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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| 59 | #define IMX_ECSPI_CONFIGREG_SS_CTL(val) BSP_FLD32(val, 8, 11) |
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| 60 | #define IMX_ECSPI_CONFIGREG_SS_CTL_GET(reg) BSP_FLD32GET(reg, 8, 11) |
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| 61 | #define IMX_ECSPI_CONFIGREG_SS_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) |
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| 62 | #define IMX_ECSPI_CONFIGREG_SCLK_POL(val) BSP_FLD32(val, 4, 7) |
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| 63 | #define IMX_ECSPI_CONFIGREG_SCLK_POL_GET(reg) BSP_FLD32GET(reg, 4, 7) |
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| 64 | #define IMX_ECSPI_CONFIGREG_SCLK_POL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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| 65 | #define IMX_ECSPI_CONFIGREG_SCLK_PHA(val) BSP_FLD32(val, 0, 3) |
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| 66 | #define IMX_ECSPI_CONFIGREG_SCLK_PHA_GET(reg) BSP_FLD32GET(reg, 0, 3) |
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| 67 | #define IMX_ECSPI_CONFIGREG_SCLK_PHA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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| 68 | #define IMX_ECSPI_TC BSP_BIT32(7) |
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| 69 | #define IMX_ECSPI_RO BSP_BIT32(6) |
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| 70 | #define IMX_ECSPI_RF BSP_BIT32(5) |
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| 71 | #define IMX_ECSPI_RDR BSP_BIT32(4) |
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| 72 | #define IMX_ECSPI_RR BSP_BIT32(3) |
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| 73 | #define IMX_ECSPI_TF BSP_BIT32(2) |
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| 74 | #define IMX_ECSPI_TDR BSP_BIT32(1) |
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| 75 | #define IMX_ECSPI_TE BSP_BIT32(0) |
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| 76 | uint32_t intreg; |
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| 77 | uint32_t dmareg; |
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| 78 | #define IMX_ECSPI_DMAREG_RXTDEN BSP_BIT32(31) |
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| 79 | #define IMX_ECSPI_DMAREG_RX_DMA_LENGTH(val) BSP_FLD32(val, 24, 29) |
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| 80 | #define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_GET(reg) BSP_FLD32GET(reg, 24, 29) |
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| 81 | #define IMX_ECSPI_DMAREG_RX_DMA_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 24, 29) |
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| 82 | #define IMX_ECSPI_DMAREG_RXDEN BSP_BIT32(23) |
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| 83 | #define IMX_ECSPI_DMAREG_RX_THRESHOLD(val) BSP_FLD32(val, 16, 21) |
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| 84 | #define IMX_ECSPI_DMAREG_RX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 16, 21) |
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| 85 | #define IMX_ECSPI_DMAREG_RX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) |
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| 86 | #define IMX_ECSPI_DMAREG_TEDEN BSP_BIT32(7) |
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| 87 | #define IMX_ECSPI_DMAREG_TX_THRESHOLD(val) BSP_FLD32(val, 0, 5) |
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| 88 | #define IMX_ECSPI_DMAREG_TX_THRESHOLD_GET(reg) BSP_FLD32GET(reg, 0, 5) |
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| 89 | #define IMX_ECSPI_DMAREG_TX_THRESHOLD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) |
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| 90 | uint32_t statreg; |
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| 91 | uint32_t periodreg; |
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| 92 | #define IMX_ECSPI_PERIODREG_CSD_CTL(val) BSP_FLD32(val, 16, 21) |
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| 93 | #define IMX_ECSPI_PERIODREG_CSD_CTL_GET(reg) BSP_FLD32GET(reg, 16, 21) |
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| 94 | #define IMX_ECSPI_PERIODREG_CSD_CTL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 21) |
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| 95 | #define IMX_ECSPI_PERIODREG_CSRC BSP_BIT32(15) |
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| 96 | #define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD(val) BSP_FLD32(val, 0, 14) |
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| 97 | #define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_GET(reg) BSP_FLD32GET(reg, 0, 14) |
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| 98 | #define IMX_ECSPI_PERIODREG_SAMPLE_PERIOD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 14) |
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| 99 | uint32_t testreg; |
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| 100 | #define IMX_ECSPI_TESTREG_LBC BSP_BIT32(31) |
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| 101 | #define IMX_ECSPI_TESTREG_RXCNT(val) BSP_FLD32(val, 8, 14) |
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| 102 | #define IMX_ECSPI_TESTREG_RXCNT_GET(reg) BSP_FLD32GET(reg, 8, 14) |
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| 103 | #define IMX_ECSPI_TESTREG_RXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 14) |
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| 104 | #define IMX_ECSPI_TESTREG_TXCNT(val) BSP_FLD32(val, 0, 6) |
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| 105 | #define IMX_ECSPI_TESTREG_TXCNT_GET(reg) BSP_FLD32GET(reg, 0, 6) |
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| 106 | #define IMX_ECSPI_TESTREG_TXCNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) |
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| 107 | uint32_t reserved_24[7]; |
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| 108 | uint32_t msgdata; |
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| 109 | } imx_ecspi; |
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| 110 | |
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| 111 | #endif /* IMX_ECSPIREG_H */ |
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