1 | /* |
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2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/fdt.h> |
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17 | #include <libfdt.h> |
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18 | #include <arm/freescale/imx/imx_ccmvar.h> |
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19 | #include <arm/freescale/imx/imx_i2creg.h> |
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20 | #include <dev/i2c/i2c.h> |
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21 | #include <rtems/irq-extension.h> |
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22 | |
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23 | #define IMX_I2C_TRANSMIT (IMX_I2C_I2CR_IEN | IMX_I2C_I2CR_IIEN \ |
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24 | | IMX_I2C_I2CR_MSTA | IMX_I2C_I2CR_MTX) |
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25 | |
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26 | #define IMX_I2C_RECEIVE (IMX_I2C_I2CR_IEN | IMX_I2C_I2CR_IIEN \ |
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27 | | IMX_I2C_I2CR_MSTA) |
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28 | |
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29 | typedef struct { |
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30 | i2c_bus base; |
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31 | volatile imx_i2c *regs; |
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32 | uint32_t msg_todo; |
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33 | const i2c_msg *msg; |
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34 | bool read; |
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35 | bool start; |
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36 | uint16_t restart; |
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37 | uint32_t chunk_total; |
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38 | uint32_t chunk_done; |
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39 | uint16_t buf_todo; |
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40 | uint8_t *buf; |
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41 | rtems_id task_id; |
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42 | int eno; |
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43 | rtems_vector_number irq; |
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44 | } imx_i2c_bus; |
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45 | |
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46 | typedef struct { |
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47 | uint16_t divisor; |
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48 | uint8_t ifdr; |
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49 | } imx_i2c_clock_divisor; |
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50 | |
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51 | static const imx_i2c_clock_divisor imx_i2c_clock_divisor_table[] = { |
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52 | { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, |
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53 | { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, |
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54 | { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, |
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55 | { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, |
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56 | { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, |
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57 | { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, |
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58 | { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, |
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59 | { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, |
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60 | { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, |
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61 | { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, |
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62 | { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, |
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63 | { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, |
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64 | { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, { 0xffff, 0x1f } |
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65 | }; |
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66 | |
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67 | static void imx_i2c_stop(volatile imx_i2c *regs) |
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68 | { |
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69 | regs->i2cr = IMX_I2C_I2CR_IEN; |
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70 | regs->i2sr = 0; |
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71 | regs->i2sr; |
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72 | } |
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73 | |
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74 | static void imx_i2c_trigger_receive(imx_i2c_bus *bus, volatile imx_i2c *regs) |
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75 | { |
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76 | uint16_t i2cr; |
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77 | |
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78 | i2cr = IMX_I2C_RECEIVE; |
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79 | |
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80 | if (bus->chunk_total == 1) { |
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81 | i2cr |= IMX_I2C_I2CR_TXAK; |
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82 | } |
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83 | |
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84 | regs->i2cr = i2cr; |
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85 | regs->i2dr; |
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86 | } |
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87 | |
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88 | static void imx_i2c_done(imx_i2c_bus *bus, int eno) |
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89 | { |
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90 | /* |
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91 | * Generates a stop in case of transmit, otherwise, only disables interrupts |
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92 | * (IMX_I2C_I2CR_MSTA is already cleared). |
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93 | */ |
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94 | imx_i2c_stop(bus->regs); |
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95 | |
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96 | bus->eno = eno; |
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97 | rtems_event_transient_send(bus->task_id); |
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98 | } |
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99 | |
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100 | static const i2c_msg *imx_i2c_msg_inc(imx_i2c_bus *bus) |
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101 | { |
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102 | const i2c_msg *next; |
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103 | |
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104 | next = bus->msg + 1; |
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105 | bus->msg = next; |
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106 | --bus->msg_todo; |
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107 | return next; |
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108 | } |
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109 | |
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110 | static void imx_i2c_msg_inc_and_set_buf(imx_i2c_bus *bus) |
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111 | { |
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112 | const i2c_msg *next; |
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113 | |
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114 | next = imx_i2c_msg_inc(bus); |
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115 | bus->buf_todo = next->len; |
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116 | bus->buf = next->buf; |
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117 | } |
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118 | |
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119 | static void imx_i2c_buf_inc(imx_i2c_bus *bus) |
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120 | { |
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121 | ++bus->buf; |
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122 | --bus->buf_todo; |
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123 | ++bus->chunk_done; |
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124 | } |
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125 | |
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126 | static void imx_i2c_buf_push(imx_i2c_bus *bus, uint8_t c) |
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127 | { |
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128 | while (true) { |
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129 | if (bus->buf_todo > 0) { |
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130 | bus->buf[0] = c; |
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131 | imx_i2c_buf_inc(bus); |
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132 | break; |
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133 | } |
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134 | |
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135 | imx_i2c_msg_inc_and_set_buf(bus); |
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136 | } |
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137 | } |
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138 | |
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139 | static uint8_t imx_i2c_buf_pop(imx_i2c_bus *bus) |
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140 | { |
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141 | while (true) { |
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142 | if (bus->buf_todo > 0) { |
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143 | uint8_t c; |
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144 | |
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145 | c = bus->buf[0]; |
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146 | imx_i2c_buf_inc(bus); |
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147 | return c; |
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148 | } |
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149 | |
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150 | imx_i2c_msg_inc_and_set_buf(bus); |
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151 | } |
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152 | } |
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153 | |
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154 | RTEMS_STATIC_ASSERT(I2C_M_RD == 1, imx_i2c_read_flag); |
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155 | |
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156 | static void imx_i2c_setup_chunk(imx_i2c_bus *bus, volatile imx_i2c *regs) |
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157 | { |
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158 | while (true) { |
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159 | const i2c_msg *msg; |
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160 | int flags; |
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161 | int can_continue; |
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162 | uint32_t i; |
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163 | |
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164 | if (bus->msg_todo == 0) { |
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165 | imx_i2c_done(bus, 0); |
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166 | break; |
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167 | } |
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168 | |
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169 | msg = bus->msg; |
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170 | flags = msg->flags; |
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171 | |
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172 | bus->read = (flags & I2C_M_RD) != 0; |
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173 | bus->start = (flags & I2C_M_NOSTART) == 0; |
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174 | bus->chunk_total = msg->len; |
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175 | bus->chunk_done = 0; |
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176 | bus->buf_todo = msg->len; |
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177 | bus->buf = msg->buf; |
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178 | |
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179 | can_continue = (flags & I2C_M_RD) | I2C_M_NOSTART; |
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180 | |
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181 | for (i = 1; i < bus->msg_todo; ++i) { |
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182 | if ((msg[i].flags & (I2C_M_RD | I2C_M_NOSTART)) != can_continue) { |
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183 | break; |
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184 | } |
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185 | |
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186 | bus->chunk_total += msg[i].len; |
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187 | } |
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188 | |
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189 | if (bus->start) { |
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190 | regs->i2cr = IMX_I2C_TRANSMIT | bus->restart; |
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191 | regs->i2dr = (uint8_t) ((msg->addr << 1) | (flags & I2C_M_RD)); |
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192 | bus->restart = IMX_I2C_I2CR_RSTA; |
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193 | break; |
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194 | } else if (bus->chunk_total > 0) { |
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195 | if (bus->read) { |
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196 | imx_i2c_trigger_receive(bus, regs); |
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197 | } else { |
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198 | regs->i2cr = IMX_I2C_TRANSMIT; |
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199 | regs->i2dr = imx_i2c_buf_pop(bus); |
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200 | } |
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201 | |
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202 | break; |
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203 | } else { |
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204 | ++bus->msg; |
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205 | --bus->msg_todo; |
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206 | } |
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207 | } |
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208 | } |
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209 | |
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210 | static void imx_i2c_transfer_complete( |
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211 | imx_i2c_bus *bus, |
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212 | volatile imx_i2c *regs, |
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213 | uint16_t i2sr |
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214 | ) |
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215 | { |
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216 | if (bus->start) { |
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217 | bus->start = false; |
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218 | |
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219 | if ((i2sr & IMX_I2C_I2SR_RXAK) != 0) { |
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220 | imx_i2c_done(bus, EIO); |
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221 | return; |
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222 | } |
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223 | |
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224 | if (bus->read) { |
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225 | imx_i2c_trigger_receive(bus, regs); |
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226 | return; |
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227 | } |
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228 | } |
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229 | |
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230 | if (bus->chunk_done < bus->chunk_total) { |
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231 | if (bus->read) { |
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232 | if (bus->chunk_done + 2 == bus->chunk_total) { |
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233 | /* Receive second last byte with NACK */ |
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234 | regs->i2cr = IMX_I2C_RECEIVE | IMX_I2C_I2CR_TXAK; |
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235 | } else if (bus->chunk_done + 1 == bus->chunk_total) { |
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236 | /* Receive last byte with STOP */ |
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237 | bus->restart = 0; |
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238 | regs->i2cr = (IMX_I2C_RECEIVE | IMX_I2C_I2CR_TXAK) |
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239 | & ~IMX_I2C_I2CR_MSTA; |
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240 | } |
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241 | |
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242 | imx_i2c_buf_push(bus, (uint8_t) regs->i2dr); |
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243 | |
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244 | if (bus->chunk_done == bus->chunk_total) { |
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245 | imx_i2c_msg_inc(bus); |
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246 | imx_i2c_setup_chunk(bus, regs); |
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247 | } |
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248 | } else { |
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249 | if (bus->chunk_done > 0 && (i2sr & IMX_I2C_I2SR_RXAK) != 0) { |
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250 | imx_i2c_done(bus, EIO); |
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251 | return; |
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252 | } |
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253 | |
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254 | regs->i2dr = imx_i2c_buf_pop(bus); |
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255 | } |
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256 | } else { |
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257 | imx_i2c_msg_inc(bus); |
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258 | imx_i2c_setup_chunk(bus, regs); |
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259 | } |
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260 | } |
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261 | |
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262 | static void imx_i2c_interrupt(void *arg) |
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263 | { |
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264 | imx_i2c_bus *bus; |
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265 | volatile imx_i2c *regs; |
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266 | uint16_t i2sr; |
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267 | |
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268 | bus = arg; |
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269 | regs = bus->regs; |
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270 | |
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271 | i2sr = regs->i2sr; |
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272 | regs->i2sr = 0; |
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273 | |
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274 | if ((i2sr & (IMX_I2C_I2SR_IAL | IMX_I2C_I2SR_ICF)) == IMX_I2C_I2SR_ICF) { |
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275 | imx_i2c_transfer_complete(bus, regs, i2sr); |
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276 | } else { |
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277 | imx_i2c_done(bus, EIO); |
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278 | } |
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279 | } |
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280 | |
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281 | static int imx_i2c_wait_for_not_busy(volatile imx_i2c *regs) |
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282 | { |
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283 | rtems_interval timeout; |
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284 | bool before; |
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285 | |
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286 | if ((regs->i2sr & IMX_I2C_I2SR_IBB) == 0) { |
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287 | return 0; |
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288 | } |
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289 | |
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290 | timeout = rtems_clock_tick_later(10); |
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291 | |
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292 | do { |
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293 | before = rtems_clock_tick_before(timeout); |
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294 | |
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295 | if ((regs->i2sr & IMX_I2C_I2SR_IBB) == 0) { |
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296 | return 0; |
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297 | } |
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298 | } while (before); |
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299 | |
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300 | return ETIMEDOUT; |
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301 | } |
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302 | |
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303 | static int imx_i2c_transfer(i2c_bus *base, i2c_msg *msgs, uint32_t n) |
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304 | { |
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305 | imx_i2c_bus *bus; |
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306 | int supported_flags; |
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307 | uint32_t i; |
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308 | volatile imx_i2c *regs; |
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309 | int eno; |
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310 | rtems_status_code sc; |
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311 | |
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312 | supported_flags = I2C_M_RD; |
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313 | |
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314 | for (i = 0; i < n; ++i) { |
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315 | if ((msgs[i].flags & ~supported_flags) != 0) { |
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316 | return -EINVAL; |
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317 | } |
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318 | |
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319 | supported_flags |= I2C_M_NOSTART; |
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320 | } |
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321 | |
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322 | bus = (imx_i2c_bus *) base; |
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323 | regs = bus->regs; |
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324 | |
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325 | eno = imx_i2c_wait_for_not_busy(regs); |
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326 | if (eno != 0) { |
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327 | return -eno; |
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328 | } |
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329 | |
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330 | bus->msg_todo = n; |
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331 | bus->msg = &msgs[0]; |
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332 | bus->restart = 0; |
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333 | bus->task_id = rtems_task_self(); |
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334 | bus->eno = 0; |
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335 | |
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336 | regs->i2sr = 0; |
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337 | imx_i2c_setup_chunk(bus, regs); |
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338 | |
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339 | sc = rtems_event_transient_receive(RTEMS_WAIT, bus->base.timeout); |
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340 | if (sc != RTEMS_SUCCESSFUL) { |
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341 | imx_i2c_stop(bus->regs); |
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342 | rtems_event_transient_clear(); |
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343 | return -ETIMEDOUT; |
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344 | } |
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345 | |
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346 | return -bus->eno; |
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347 | } |
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348 | |
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349 | static int imx_i2c_set_clock(i2c_bus *base, unsigned long clock) |
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350 | { |
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351 | imx_i2c_bus *bus; |
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352 | uint32_t ipg_clock; |
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353 | uint16_t div; |
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354 | size_t i; |
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355 | const imx_i2c_clock_divisor *clock_divisor; |
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356 | |
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357 | bus = (imx_i2c_bus *) base; |
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358 | ipg_clock = imx_ccm_ipg_hz(); |
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359 | div = (uint16_t) ((ipg_clock + clock - 1) / clock); |
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360 | |
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361 | for (i = 0; i < RTEMS_ARRAY_SIZE(imx_i2c_clock_divisor_table); ++i) { |
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362 | clock_divisor = &imx_i2c_clock_divisor_table[i]; |
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363 | |
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364 | if (clock_divisor->divisor >= div) { |
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365 | break; |
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366 | } |
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367 | } |
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368 | |
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369 | bus->regs->ifdr = clock_divisor->ifdr; |
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370 | return 0; |
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371 | } |
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372 | |
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373 | static void imx_i2c_destroy(i2c_bus *base) |
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374 | { |
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375 | imx_i2c_bus *bus; |
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376 | |
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377 | bus = (imx_i2c_bus *) base; |
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378 | rtems_interrupt_handler_remove(bus->irq, imx_i2c_interrupt, bus); |
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379 | i2c_bus_destroy_and_free(&bus->base); |
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380 | } |
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381 | |
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382 | static int imx_i2c_init(imx_i2c_bus *bus) |
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383 | { |
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384 | rtems_status_code sc; |
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385 | |
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386 | imx_i2c_set_clock(&bus->base, I2C_BUS_CLOCK_DEFAULT); |
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387 | bus->regs->i2cr = IMX_I2C_I2CR_IEN; |
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388 | |
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389 | sc = rtems_interrupt_handler_install( |
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390 | bus->irq, |
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391 | "I2C", |
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392 | RTEMS_INTERRUPT_UNIQUE, |
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393 | imx_i2c_interrupt, |
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394 | bus |
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395 | ); |
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396 | if (sc != RTEMS_SUCCESSFUL) { |
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397 | return EAGAIN; |
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398 | } |
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399 | |
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400 | return 0; |
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401 | } |
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402 | |
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403 | int i2c_bus_register_imx(const char *bus_path, const char *alias_or_path) |
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404 | { |
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405 | const void *fdt; |
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406 | const char *path; |
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407 | int node; |
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408 | imx_i2c_bus *bus; |
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409 | int eno; |
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410 | |
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411 | fdt = bsp_fdt_get(); |
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412 | path = fdt_get_alias(fdt, alias_or_path); |
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413 | |
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414 | if (path == NULL) { |
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415 | path = alias_or_path; |
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416 | } |
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417 | |
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418 | node = fdt_path_offset(fdt, path); |
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419 | if (node < 0) { |
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420 | rtems_set_errno_and_return_minus_one(ENXIO); |
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421 | } |
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422 | |
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423 | bus = (imx_i2c_bus *) i2c_bus_alloc_and_init(sizeof(*bus)); |
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424 | if (bus == NULL){ |
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425 | return -1; |
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426 | } |
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427 | |
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428 | bus->regs = imx_get_reg_of_node(fdt, node); |
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429 | bus->irq = imx_get_irq_of_node(fdt, node, 0); |
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430 | |
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431 | eno = imx_i2c_init(bus); |
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432 | if (eno != 0) { |
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433 | (*bus->base.destroy)(&bus->base); |
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434 | rtems_set_errno_and_return_minus_one(eno); |
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435 | } |
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436 | |
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437 | bus->base.transfer = imx_i2c_transfer; |
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438 | bus->base.set_clock = imx_i2c_set_clock; |
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439 | bus->base.destroy = imx_i2c_destroy; |
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440 | |
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441 | return i2c_bus_register(&bus->base, bus_path); |
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442 | } |
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