1 | /* |
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2 | * SPDX-License-Identifier: BSD-2-Clause |
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3 | * |
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4 | * Copyright (C) 2019-2020 embedded brains GmbH. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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17 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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18 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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19 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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20 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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21 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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22 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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23 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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25 | * POSSIBILITY OF SUCH DAMAGE. |
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26 | */ |
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27 | |
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28 | #include <assert.h> |
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29 | #include <bsp/fatal.h> |
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30 | #include <bsp/fdt.h> |
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31 | #include <bsp/imx-gpio.h> |
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32 | #include <libfdt.h> |
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33 | #include <rtems.h> |
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34 | #include <rtems/sysinit.h> |
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35 | |
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36 | #define IMX_GPIO_ALIAS_NAME "gpioX" |
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37 | |
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38 | /* |
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39 | * i.MX6ULL has 5, i.MX7D has 7 |
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40 | * |
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41 | * Be careful when changing this. The attach() does a simple ASCII conversion. |
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42 | */ |
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43 | #define IMX_MAX_GPIO_MODULES 7 |
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44 | |
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45 | struct imx_gpio_regs { |
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46 | uint32_t dr; |
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47 | uint32_t gdir; |
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48 | uint32_t psr; |
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49 | uint32_t icr1; |
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50 | #define IMX_GPIO_ICR_LOW_LEVEL 0 |
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51 | #define IMX_GPIO_ICR_HIGH_LEVEL 1 |
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52 | #define IMX_GPIO_ICR_RISING_EDGE 2 |
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53 | #define IMX_GPIO_ICR_FALLING_EDGE 3 |
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54 | uint32_t icr2; |
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55 | uint32_t imr; |
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56 | uint32_t isr; |
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57 | uint32_t edge_sel; |
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58 | }; |
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59 | |
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60 | struct imx_gpio { |
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61 | char name[sizeof(IMX_GPIO_ALIAS_NAME)]; |
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62 | struct imx_gpio_regs *regs; |
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63 | rtems_interrupt_lock lock; |
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64 | }; |
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65 | |
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66 | /* The GPIO modules. These will be initialized based on the FDT alias table. */ |
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67 | struct imx_gpio imx_gpio[IMX_MAX_GPIO_MODULES]; |
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68 | |
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69 | const char *imx_gpio_get_name(struct imx_gpio *imx_gpio) |
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70 | { |
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71 | return imx_gpio->name; |
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72 | } |
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73 | |
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74 | static void imx_gpio_attach(void) |
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75 | { |
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76 | size_t i; |
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77 | const void *fdt; |
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78 | |
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79 | fdt = bsp_fdt_get(); |
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80 | |
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81 | memset(imx_gpio, 0, sizeof(imx_gpio)); |
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82 | |
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83 | for (i = 0; i < IMX_MAX_GPIO_MODULES; ++i) { |
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84 | const char *path; |
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85 | int node; |
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86 | const uint32_t *val; |
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87 | uint32_t gpio_regs = 0; |
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88 | int len; |
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89 | |
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90 | memcpy(imx_gpio[i].name, IMX_GPIO_ALIAS_NAME, sizeof(IMX_GPIO_ALIAS_NAME)); |
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91 | imx_gpio[i].name[sizeof(IMX_GPIO_ALIAS_NAME)-2] = (char)('0' + i); |
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92 | |
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93 | path = fdt_get_alias(fdt, imx_gpio[i].name); |
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94 | if (path == NULL) { |
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95 | continue; |
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96 | } |
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97 | |
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98 | node = fdt_path_offset(fdt, path); |
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99 | if (node < 0) { |
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100 | bsp_fatal(IMX_FATAL_GPIO_UNEXPECTED_FDT); |
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101 | } |
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102 | |
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103 | val = fdt_getprop(fdt, node, "reg", &len); |
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104 | if (len > 0) { |
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105 | gpio_regs = fdt32_to_cpu(val[0]); |
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106 | } else { |
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107 | bsp_fatal(IMX_FATAL_GPIO_UNEXPECTED_FDT); |
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108 | } |
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109 | |
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110 | imx_gpio[i].regs = (struct imx_gpio_regs *)gpio_regs; |
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111 | rtems_interrupt_lock_initialize(&imx_gpio[i].lock, imx_gpio[i].name); |
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112 | } |
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113 | } |
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114 | |
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115 | struct imx_gpio *imx_gpio_get_by_index(unsigned idx) |
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116 | { |
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117 | if ((idx < IMX_MAX_GPIO_MODULES) && (imx_gpio[idx].regs != NULL)) { |
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118 | return &imx_gpio[idx]; |
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119 | } |
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120 | return NULL; |
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121 | } |
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122 | |
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123 | struct imx_gpio *imx_gpio_get_by_register(void *regs) |
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124 | { |
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125 | size_t i; |
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126 | |
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127 | for (i = 0; i < IMX_MAX_GPIO_MODULES; ++i) { |
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128 | if (imx_gpio[i].regs == regs) { |
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129 | return &imx_gpio[i]; |
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130 | } |
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131 | } |
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132 | return NULL; |
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133 | } |
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134 | |
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135 | static void imx_gpio_direction_input(struct imx_gpio_pin *pin) |
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136 | { |
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137 | rtems_interrupt_lock_context lock_context; |
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138 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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139 | pin->gpio->regs->gdir &= ~pin->mask; |
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140 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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141 | } |
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142 | |
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143 | static void imx_gpio_direction_output(struct imx_gpio_pin *pin) |
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144 | { |
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145 | rtems_interrupt_lock_context lock_context; |
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146 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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147 | pin->gpio->regs->gdir |= pin->mask; |
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148 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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149 | } |
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150 | |
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151 | static void imx_gpio_set_interrupt_any_edge(struct imx_gpio_pin *pin) |
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152 | { |
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153 | rtems_interrupt_lock_context lock_context; |
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154 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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155 | pin->gpio->regs->edge_sel |= pin->mask; |
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156 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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157 | } |
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158 | |
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159 | static void imx_gpio_set_interrupt_mode(struct imx_gpio_pin *pin, uint32_t mode) |
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160 | { |
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161 | size_t i; |
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162 | |
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163 | for (i=0; i < 32; ++i) { |
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164 | if ((pin->mask & (1u << i)) != 0) { |
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165 | volatile uint32_t *icr; |
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166 | size_t shift; |
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167 | rtems_interrupt_lock_context lock_context; |
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168 | |
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169 | if (i < 16) { |
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170 | icr = &pin->gpio->regs->icr1; |
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171 | shift = 2 * i; |
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172 | } else { |
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173 | icr = &pin->gpio->regs->icr2; |
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174 | shift = 2 * (i - 16); |
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175 | } |
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176 | |
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177 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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178 | *icr = (*icr & ~(3u << shift)) | (mode << shift); |
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179 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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180 | } |
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181 | } |
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182 | } |
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183 | |
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184 | rtems_status_code imx_gpio_init_from_fdt_property ( |
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185 | struct imx_gpio_pin *pin, |
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186 | int node_offset, |
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187 | const char *property, |
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188 | enum imx_gpio_mode mode, |
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189 | size_t index |
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190 | ) |
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191 | { |
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192 | int len; |
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193 | const uint32_t *val; |
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194 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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195 | const void *fdt; |
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196 | uint32_t gpio_regs; |
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197 | const unsigned pin_length_dwords = 3; |
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198 | const unsigned pin_length_bytes = (pin_length_dwords * sizeof(uint32_t)); |
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199 | uint32_t gpio_phandle; |
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200 | uint32_t pin_nr; |
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201 | int cfgnode; |
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202 | |
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203 | memset(pin, 0, sizeof(*pin)); |
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204 | |
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205 | fdt = bsp_fdt_get(); |
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206 | val = fdt_getprop(fdt, node_offset, property, &len); |
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207 | if (val == NULL || (len % pin_length_bytes != 0) || |
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208 | (index >= len / pin_length_bytes)) { |
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209 | sc = RTEMS_UNSATISFIED; |
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210 | } |
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211 | if (sc == RTEMS_SUCCESSFUL) { |
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212 | pin_nr = fdt32_to_cpu(val[1 + index * pin_length_dwords]); |
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213 | gpio_phandle = fdt32_to_cpu(val[0 + index * pin_length_dwords]); |
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214 | |
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215 | cfgnode = fdt_node_offset_by_phandle(fdt, gpio_phandle); |
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216 | val = fdt_getprop(fdt, cfgnode, "reg", &len); |
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217 | if (len > 0) { |
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218 | gpio_regs = fdt32_to_cpu(val[0]); |
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219 | } else { |
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220 | sc = RTEMS_UNSATISFIED; |
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221 | } |
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222 | } |
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223 | if (sc == RTEMS_SUCCESSFUL) { |
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224 | pin->gpio = imx_gpio_get_by_register((void *)gpio_regs); |
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225 | pin->mask = 1u << pin_nr; |
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226 | pin->shift = pin_nr; |
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227 | pin->mode = mode; |
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228 | } |
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229 | if (sc == RTEMS_SUCCESSFUL) { |
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230 | imx_gpio_init(pin); |
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231 | } |
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232 | |
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233 | return sc; |
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234 | } |
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235 | |
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236 | rtems_vector_number imx_gpio_get_irq_of_node( |
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237 | const void *fdt, |
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238 | int node, |
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239 | size_t index |
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240 | ) |
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241 | { |
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242 | const uint32_t *val; |
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243 | uint32_t pin; |
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244 | int parent; |
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245 | size_t parent_index; |
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246 | int len; |
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247 | |
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248 | val = fdt_getprop(fdt, node, "interrupts", &len); |
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249 | if (val == NULL || len < (int) ((index + 1) * 8)) { |
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250 | return UINT32_MAX; |
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251 | } |
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252 | pin = fdt32_to_cpu(val[index * 2]); |
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253 | if (pin < 16) { |
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254 | parent_index = 0; |
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255 | } else { |
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256 | parent_index = 1; |
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257 | } |
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258 | |
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259 | val = fdt_getprop(fdt, node, "interrupt-parent", &len); |
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260 | if (len != 4) { |
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261 | return UINT32_MAX; |
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262 | } |
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263 | parent = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(val[0])); |
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264 | |
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265 | return imx_get_irq_of_node(fdt, parent, parent_index); |
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266 | } |
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267 | |
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268 | void imx_gpio_init (struct imx_gpio_pin *pin) |
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269 | { |
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270 | switch (pin->mode) { |
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271 | case (IMX_GPIO_MODE_INTERRUPT_LOW): |
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272 | imx_gpio_direction_input(pin); |
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273 | imx_gpio_set_interrupt_mode(pin, IMX_GPIO_ICR_LOW_LEVEL); |
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274 | break; |
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275 | case (IMX_GPIO_MODE_INTERRUPT_HIGH): |
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276 | imx_gpio_direction_input(pin); |
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277 | imx_gpio_set_interrupt_mode(pin, IMX_GPIO_ICR_HIGH_LEVEL); |
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278 | break; |
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279 | case (IMX_GPIO_MODE_INTERRUPT_RISING): |
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280 | imx_gpio_direction_input(pin); |
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281 | imx_gpio_set_interrupt_mode(pin, IMX_GPIO_ICR_RISING_EDGE); |
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282 | break; |
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283 | case (IMX_GPIO_MODE_INTERRUPT_FALLING): |
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284 | imx_gpio_direction_input(pin); |
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285 | imx_gpio_set_interrupt_mode(pin, IMX_GPIO_ICR_FALLING_EDGE); |
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286 | break; |
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287 | case (IMX_GPIO_MODE_INTERRUPT_ANY_EDGE): |
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288 | imx_gpio_direction_input(pin); |
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289 | imx_gpio_set_interrupt_any_edge(pin); |
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290 | /* Interrupt mode isn't really relevant here. Just set it to get |
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291 | * a defined behaviour in case of a bug. */ |
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292 | imx_gpio_set_interrupt_mode(pin, IMX_GPIO_ICR_FALLING_EDGE); |
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293 | break; |
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294 | case (IMX_GPIO_MODE_INPUT): |
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295 | imx_gpio_direction_input(pin); |
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296 | break; |
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297 | case (IMX_GPIO_MODE_OUTPUT): |
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298 | imx_gpio_direction_output(pin); |
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299 | break; |
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300 | default: |
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301 | assert(false); |
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302 | break; |
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303 | } |
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304 | } |
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305 | |
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306 | void imx_gpio_set_output(struct imx_gpio_pin *pin, uint32_t set) |
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307 | { |
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308 | rtems_interrupt_lock_context lock_context; |
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309 | set <<= pin->shift; |
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310 | set &= pin->mask; |
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311 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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312 | pin->gpio->regs->dr = (pin->gpio->regs->dr & ~pin->mask) | set; |
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313 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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314 | } |
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315 | |
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316 | void imx_gpio_toggle_output(struct imx_gpio_pin *pin) |
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317 | { |
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318 | rtems_interrupt_lock_context lock_context; |
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319 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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320 | pin->gpio->regs->dr = (pin->gpio->regs->dr ^ pin->mask); |
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321 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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322 | } |
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323 | |
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324 | uint32_t imx_gpio_get_input(struct imx_gpio_pin *pin) |
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325 | { |
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326 | return (pin->gpio->regs->dr & pin->mask) >> pin->shift; |
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327 | } |
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328 | |
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329 | void imx_gpio_int_disable(struct imx_gpio_pin *pin) |
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330 | { |
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331 | rtems_interrupt_lock_context lock_context; |
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332 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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333 | pin->gpio->regs->imr &= ~pin->mask; |
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334 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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335 | } |
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336 | |
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337 | void imx_gpio_int_enable(struct imx_gpio_pin *pin) |
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338 | { |
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339 | rtems_interrupt_lock_context lock_context; |
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340 | rtems_interrupt_lock_acquire(&pin->gpio->lock, &lock_context); |
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341 | pin->gpio->regs->imr |= pin->mask; |
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342 | rtems_interrupt_lock_release(&pin->gpio->lock, &lock_context); |
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343 | } |
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344 | |
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345 | uint32_t imx_gpio_get_isr(struct imx_gpio_pin *pin) |
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346 | { |
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347 | return (pin->gpio->regs->isr & pin->mask) >> pin->shift; |
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348 | } |
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349 | |
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350 | void imx_gpio_clear_isr(struct imx_gpio_pin *pin, uint32_t clr) |
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351 | { |
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352 | pin->gpio->regs->isr = (clr << pin->shift) & pin->mask; |
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353 | } |
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354 | |
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355 | RTEMS_SYSINIT_ITEM( |
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356 | imx_gpio_attach, |
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357 | RTEMS_SYSINIT_DEVICE_DRIVERS, |
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358 | RTEMS_SYSINIT_ORDER_FIRST |
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359 | ); |
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