1 | /* |
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2 | * By Yang Xi <hiyangxi@gmail.com>. |
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3 | * Based upon CSB337 |
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4 | * |
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5 | * The license and distribution terms for this file may be |
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6 | * found in the file LICENSE in this distribution or at |
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7 | * http://www.rtems.org/license/LICENSE. |
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8 | */ |
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9 | |
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10 | #include <rtems/asm.h> |
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11 | #include <rtems/score/cpu.h> |
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12 | |
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13 | .text |
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14 | .globl _start |
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15 | _start: |
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16 | /* |
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17 | * Since I don't plan to return to the bootloader, |
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18 | * I don't have to save the registers. |
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19 | */ |
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20 | |
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21 | /* Set end of interrupt stack area */ |
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22 | ldr r7, =_ISR_Stack_area_end |
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23 | |
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24 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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25 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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26 | msr cpsr, r0 |
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27 | ldr r1, =bsp_stack_fiq_size |
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28 | mov sp, r7 |
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29 | sub r7, r7, r1 |
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30 | |
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31 | /* Enter ABT mode and set up the ABT stack pointer */ |
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32 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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33 | msr cpsr, r0 |
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34 | ldr r1, =bsp_stack_abt_size |
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35 | mov sp, r7 |
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36 | sub r7, r7, r1 |
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37 | |
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38 | /* Enter UND mode and set up the UND stack pointer */ |
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39 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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40 | msr cpsr, r0 |
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41 | ldr r1, =bsp_stack_und_size |
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42 | mov sp, r7 |
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43 | sub r7, r7, r1 |
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44 | |
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45 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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46 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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47 | msr cpsr, r0 |
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48 | mov sp, r7 |
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49 | |
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50 | /* |
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51 | * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack |
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52 | * (interrupts are disabled). |
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53 | */ |
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54 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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55 | msr cpsr, r0 |
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56 | mov sp, r7 |
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57 | |
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58 | /* Stay in SVC mode */ |
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59 | |
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60 | /* zero the bss */ |
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61 | ldr r1, =bsp_section_bss_end |
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62 | ldr r0, =bsp_section_bss_begin |
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63 | |
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64 | _bss_init: |
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65 | mov r2, #0 |
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66 | cmp r0, r1 |
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67 | strlot r2, [r0], #4 |
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68 | blo _bss_init /* loop while r0 < r1 */ |
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69 | |
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70 | /* |
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71 | * Initialize the MMU. After we return, the MMU is enabled, |
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72 | * and memory may be remapped. I hope we don't remap this |
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73 | * memory away. |
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74 | */ |
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75 | |
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76 | ldr r0, =mem_map |
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77 | bl mmu_init |
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78 | |
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79 | |
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80 | |
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81 | /* |
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82 | * Initialize the exception vectors. This includes the |
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83 | * exceptions vectors (0x00000000-0x0000001c), and the |
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84 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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85 | */ |
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86 | mov r0, #0 |
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87 | adr r1, vector_block |
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88 | ldmia r1!, {r2-r9} |
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89 | stmia r0!, {r2-r9} |
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90 | ldmia r1!, {r2-r9} |
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91 | stmia r0!, {r2-r9} |
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92 | |
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93 | |
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94 | |
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95 | /* Now we are prepared to start the BSP's C code */ |
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96 | mov r0, #0 |
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97 | bl boot_card |
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98 | |
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99 | /* |
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100 | * Theoretically, we could return to what started us up, |
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101 | * but we'd have to have saved the registers and stacks. |
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102 | * Instead, we'll just reset. |
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103 | */ |
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104 | bl bsp_reset |
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105 | |
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106 | /* We shouldn't get here. If we do, hang */ |
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107 | _hang: b _hang |
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108 | |
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109 | |
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110 | /* |
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111 | * This is the exception vector table and the pointers to |
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112 | * the functions that handle the exceptions. It's a total |
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113 | * of 16 words (64 bytes) |
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114 | */ |
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115 | vector_block: |
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116 | ldr pc, handler_addr_reset |
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117 | ldr pc, handler_addr_undef |
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118 | ldr pc, handler_addr_swi |
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119 | ldr pc, handler_addr_prefetch |
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120 | ldr pc, handler_addr_abort |
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121 | nop |
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122 | ldr pc, handler_addr_irq |
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123 | ldr pc, handler_addr_fiq |
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124 | |
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125 | handler_addr_reset: |
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126 | .word bsp_reset |
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127 | |
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128 | handler_addr_undef: |
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129 | .word _ARMV4_Exception_undef_default |
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130 | |
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131 | handler_addr_swi: |
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132 | .word _ARMV4_Exception_swi_default |
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133 | |
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134 | handler_addr_prefetch: |
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135 | .word _ARMV4_Exception_pref_abort_default |
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136 | |
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137 | handler_addr_abort: |
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138 | .word _ARMV4_Exception_data_abort_default |
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139 | |
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140 | handler_addr_reserved: |
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141 | .word _ARMV4_Exception_reserved_default |
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142 | |
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143 | handler_addr_irq: |
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144 | .word _ARMV4_Exception_interrupt |
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145 | |
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146 | handler_addr_fiq: |
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147 | .word _ARMV4_Exception_fiq_default |
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