source: rtems/bsps/arm/gumstix/start/start.S @ ff081aee

Last change on this file since ff081aee was ff081aee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 6, 2018 at 3:58:02 PM

score: Rename interrupt stack symbols

Rename

  • _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  • _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  • _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.

Update #3459.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*
2 *  By Yang Xi <hiyangxi@gmail.com>.
3 *  Based upon CSB337
4 *
5 *  The license and distribution terms for this file may be
6 *  found in the file LICENSE in this distribution or at
7 *  http://www.rtems.org/license/LICENSE.
8 */
9
10#include <rtems/asm.h>
11#include <rtems/score/cpu.h>
12
13.text
14.globl  _start
15_start:
16        /*
17         * Since I don't plan to return to the bootloader,
18         * I don't have to save the registers.
19         */
20
21        /* Set end of interrupt stack area */
22        ldr     r7, =_ISR_Stack_area_end
23
24        /* Enter FIQ mode and set up the FIQ stack pointer */
25        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
26        msr     cpsr, r0
27        ldr     r1, =bsp_stack_fiq_size
28        mov     sp, r7
29        sub     r7, r7, r1
30
31        /* Enter ABT mode and set up the ABT stack pointer */
32        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
33        msr     cpsr, r0
34        ldr     r1, =bsp_stack_abt_size
35        mov     sp, r7
36        sub     r7, r7, r1
37
38        /* Enter UND mode and set up the UND stack pointer */
39        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
40        msr     cpsr, r0
41        ldr     r1, =bsp_stack_und_size
42        mov     sp, r7
43        sub     r7, r7, r1
44
45        /* Enter IRQ mode and set up the IRQ stack pointer */
46        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
47        msr     cpsr, r0
48        mov     sp, r7
49
50        /*
51         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
52         * (interrupts are disabled).
53         */
54        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
55        msr     cpsr, r0
56        mov     sp, r7
57
58        /* Stay in SVC mode */
59
60        /* zero the bss */
61        ldr     r1, =bsp_section_bss_end
62        ldr     r0, =bsp_section_bss_begin
63
64_bss_init:
65        mov     r2, #0
66        cmp     r0, r1
67        strlot  r2, [r0], #4
68        blo     _bss_init        /* loop while r0 < r1 */
69
70        /*
71         * Initialize the MMU. After we return, the MMU is enabled,
72         * and memory may be remapped. I hope we don't remap this
73         * memory away.
74         */
75
76        ldr     r0, =mem_map
77        bl      mmu_init
78
79
80
81        /*
82         * Initialize the exception vectors. This includes the
83         * exceptions vectors (0x00000000-0x0000001c), and the
84         * pointers to the exception handlers (0x00000020-0x0000003c).
85         */
86        mov     r0, #0
87        adr     r1, vector_block
88        ldmia   r1!, {r2-r9}
89        stmia   r0!, {r2-r9}
90        ldmia   r1!, {r2-r9}
91        stmia   r0!, {r2-r9}
92
93
94
95        /* Now we are prepared to start the BSP's C code */
96        mov     r0, #0
97        bl      boot_card
98
99        /*
100         * Theoretically, we could return to what started us up,
101         * but we'd have to have saved the registers and stacks.
102         * Instead, we'll just reset.
103         */
104        bl      bsp_reset
105
106        /* We shouldn't get here. If we do, hang */
107_hang:  b       _hang
108
109
110/*
111 * This is the exception vector table and the pointers to
112 * the functions that handle the exceptions. It's a total
113 * of 16 words (64 bytes)
114 */
115vector_block:
116        ldr    pc, handler_addr_reset
117        ldr    pc, handler_addr_undef
118        ldr    pc, handler_addr_swi
119        ldr    pc, handler_addr_prefetch
120        ldr    pc, handler_addr_abort
121        nop
122        ldr    pc, handler_addr_irq
123        ldr    pc, handler_addr_fiq
124
125handler_addr_reset:
126        .word  bsp_reset
127
128handler_addr_undef:
129        .word  _ARMV4_Exception_undef_default
130
131handler_addr_swi:
132        .word  _ARMV4_Exception_swi_default
133
134handler_addr_prefetch:
135        .word  _ARMV4_Exception_pref_abort_default
136
137handler_addr_abort:
138        .word  _ARMV4_Exception_data_abort_default
139
140handler_addr_reserved:
141        .word  _ARMV4_Exception_reserved_default
142
143handler_addr_irq:
144        .word  _ARMV4_Exception_interrupt
145
146handler_addr_fiq:
147        .word  _ARMV4_Exception_fiq_default
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