[3d6e1740] | 1 | /** |
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| 2 | * @file |
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| 3 | * @ingroup gumstix_dp8390 |
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| 4 | * @brief DP8390 Ethernet Controller Support |
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| 5 | */ |
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| 6 | |
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[a17bc42] | 7 | /* |
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| 8 | * Information about the DP8390 Ethernet controller. |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef __BSP_WD80x3_h |
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| 12 | #define __BSP_WD80x3_h |
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| 13 | |
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| 14 | /* Register descriptions */ |
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| 15 | |
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[3d6e1740] | 16 | /** |
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| 17 | * @defgroup gumstix_dp8390 DP8390 Support |
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| 18 | * @ingroup arm_gumstix |
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| 19 | * @brief DP8390 Ethernet Controller Support |
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| 20 | * @{ |
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| 21 | */ |
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| 22 | |
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| 23 | /** |
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| 24 | * @name Controller DP8390. |
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| 25 | * @{ |
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| 26 | */ |
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| 27 | |
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| 28 | /** @brief Port Window. */ |
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| 29 | #define DATAPORT 0x10 |
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| 30 | /** @brief Issue a read for reset */ |
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| 31 | #define RESET 0x1f |
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| 32 | /** @brief I/O port definition */ |
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| 33 | #define W83CREG 0x00 |
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[a17bc42] | 34 | #define ADDROM 0x08 |
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| 35 | |
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[3d6e1740] | 36 | /** @} */ |
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| 37 | |
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| 38 | /** |
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| 39 | * @name page 0 read or read/write registers |
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| 40 | * @{ |
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| 41 | */ |
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[a17bc42] | 42 | |
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| 43 | #define CMDR 0x00+RO |
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[3d6e1740] | 44 | /** @brief current local dma addr 0 for read */ |
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| 45 | #define CLDA0 0x01+RO |
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| 46 | /** @brief current local dma addr 1 for read */ |
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| 47 | #define CLDA1 0x02+RO |
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| 48 | /** @brief boundary reg for rd and wr */ |
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| 49 | #define BNRY 0x03+RO |
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| 50 | /** @brief tx status reg for rd */ |
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| 51 | #define TSR 0x04+RO |
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| 52 | /** @brief number of collision reg for rd */ |
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| 53 | #define NCR 0x05+RO |
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| 54 | /** @breif FIFO for rd */ |
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| 55 | #define FIFO 0x06+RO |
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| 56 | /** @brief interrupt status reg for rd and wr */ |
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| 57 | #define ISR 0x07+RO |
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| 58 | /** @brief current remote dma address 0 for rd */ |
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| 59 | #define CRDA0 0x08+RO |
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| 60 | /** @brief current remote dma address 1 for rd */ |
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| 61 | #define CRDA1 0x09+RO |
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| 62 | /** @brief rx status reg for rd */ |
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| 63 | #define RSR 0x0C+RO |
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| 64 | /** @brief tally cnt 0 for frm alg err for rd */ |
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| 65 | #define CNTR0 0x0D+RO |
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| 66 | /** @brief tally cnt 1 for crc err for rd */ |
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| 67 | #define CNTR1 RO+0x0E |
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| 68 | /** @brief tally cnt 2 for missed pkt for rd */ |
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| 69 | #define CNTR2 0x0F+RO |
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| 70 | |
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| 71 | /** @} */ |
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| 72 | |
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| 73 | /** |
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| 74 | * @name page 0 write registers |
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| 75 | * @{ |
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| 76 | */ |
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| 77 | |
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| 78 | /** @brief page start register */ |
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| 79 | #define PSTART 0x01+RO |
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| 80 | /** @brief page stop register */ |
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| 81 | #define PSTOP 0x02+RO |
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| 82 | /** @breif tx start page start reg */ |
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| 83 | #define TPSR 0x04+RO |
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| 84 | /** @brief tx byte count 0 reg */ |
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| 85 | #define TBCR0 0x05+RO |
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| 86 | /** @brief tx byte count 1 reg */ |
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| 87 | #define TBCR1 0x06+RO |
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| 88 | /** @brief remote start address reg 0 */ |
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| 89 | #define RSAR0 0x08+RO |
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| 90 | /** @brief remote start address reg 1 */ |
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| 91 | #define RSAR1 0x09+RO |
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| 92 | /** @brief remote byte count reg 0 */ |
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| 93 | #define RBCR0 0x0A+RO |
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| 94 | /** @brief remote byte count reg 1 */ |
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| 95 | #define RBCR1 0x0B+RO |
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| 96 | /** @brief rx configuration reg */ |
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| 97 | #define RCR 0x0C+RO |
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| 98 | /** @brief tx configuration reg */ |
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| 99 | #define TCR 0x0D+RO |
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| 100 | /** @brief data configuration reg */ |
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| 101 | #define DCR RO+0x0E |
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| 102 | /** @brief interrupt mask reg */ |
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| 103 | #define IMR 0x0F+RO |
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| 104 | |
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| 105 | /** @} */ |
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| 106 | |
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| 107 | /** |
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| 108 | * @name page 1 registers |
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| 109 | * @{ |
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| 110 | */ |
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| 111 | |
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| 112 | /** @brief physical addr reg base for rd and wr */ |
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| 113 | #define PAR 0x01+RO |
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| 114 | /** @brief current page reg for rd and wr */ |
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| 115 | #define CURR 0x07+RO |
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| 116 | /** @brief multicast addr reg base fro rd and WR */ |
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| 117 | #define MAR 0x08+RO |
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| 118 | /** @brief size of multicast addr space */ |
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| 119 | #define MARsize 8 |
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| 120 | |
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| 121 | /** @} */ |
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| 122 | |
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| 123 | /** |
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| 124 | * @name W83CREG command bits |
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| 125 | * @{ |
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| 126 | */ |
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| 127 | |
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| 128 | /** @brief W83CREG masks */ |
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| 129 | #define MSK_RESET 0x80 |
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[a17bc42] | 130 | #define MSK_ENASH 0x40 |
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[3d6e1740] | 131 | /** @brief memory decode bits, corresponding */ |
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| 132 | #define MSK_DECOD 0x3F |
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| 133 | |
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| 134 | /** @} */ |
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| 135 | |
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| 136 | /** |
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| 137 | * @name CMDR command bits |
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| 138 | * @{ |
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| 139 | */ |
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| 140 | |
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| 141 | /** @brief stop the chip */ |
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| 142 | #define MSK_STP 0x01 |
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| 143 | /** @brief start the chip */ |
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| 144 | #define MSK_STA 0x02 |
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| 145 | /** @brief initial txing of a frm */ |
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| 146 | #define MSK_TXP 0x04 |
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| 147 | /** @brief remote read */ |
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| 148 | #define MSK_RRE 0x08 |
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| 149 | /** @brief remote write */ |
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| 150 | #define MSK_RWR 0x10 |
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| 151 | /** @brief no DMA used */ |
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| 152 | #define MSK_RD2 0x20 |
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| 153 | /** @brief select register page 0 */ |
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| 154 | #define MSK_PG0 0x00 |
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| 155 | /** @brief select register page 1 */ |
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| 156 | #define MSK_PG1 0x40 |
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| 157 | /** @brief select register page 2 */ |
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| 158 | #define MSK_PG2 0x80 |
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| 159 | |
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| 160 | /** @} */ |
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| 161 | |
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| 162 | /** |
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| 163 | * @name ISR and TSR status bits |
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| 164 | * @{ |
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| 165 | */ |
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| 166 | |
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| 167 | /* @brief rx with no error */ |
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| 168 | #define MSK_PRX 0x01 |
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| 169 | /* @brief tx with no error */ |
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| 170 | #define MSK_PTX 0x02 |
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| 171 | /* @brief rx with error */ |
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| 172 | #define MSK_RXE 0x04 |
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| 173 | /* @brief tx with error */ |
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| 174 | #define MSK_TXE 0x08 |
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| 175 | /* @brief overwrite warning */ |
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| 176 | #define MSK_OVW 0x10 |
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| 177 | /* @brief MSB of one of the tally counters is set */ |
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| 178 | #define MSK_CNT 0x20 |
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| 179 | /* @brief remote dma completed */ |
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| 180 | #define MSK_RDC 0x40 |
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| 181 | /* @brief reset state indicator */ |
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| 182 | #define MSK_RST 0x80 |
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| 183 | |
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| 184 | /** @} */ |
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| 185 | |
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| 186 | /** |
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| 187 | * @name DCR command bits |
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| 188 | * @{ |
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| 189 | */ |
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| 190 | |
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| 191 | /** @brief word transfer mode selection */ |
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| 192 | #define MSK_WTS 0x01 |
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| 193 | /** @brief byte order selection */ |
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| 194 | #define MSK_BOS 0x02 |
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| 195 | /** @brief long addr selection */ |
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| 196 | #define MSK_LAS 0x04 |
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| 197 | /** @brief burst mode selection */ |
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| 198 | #define MSK_BMS 0x08 |
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| 199 | /** @brief autoinitialize remote */ |
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| 200 | #define MSK_ARM 0x10 |
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| 201 | /** @brief burst lrngth selection */ |
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| 202 | #define MSK_FT00 0x00 |
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| 203 | /** @brief burst lrngth selection */ |
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| 204 | #define MSK_FT01 0x20 |
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| 205 | /** @brief burst lrngth selection */ |
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| 206 | #define MSK_FT10 0x40 |
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| 207 | /** @brief burst lrngth selection */ |
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| 208 | #define MSK_FT11 0x60 |
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| 209 | |
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| 210 | /** @} */ |
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| 211 | |
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| 212 | /** |
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| 213 | * @name RCR command bits |
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| 214 | * @{ |
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| 215 | */ |
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| 216 | |
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| 217 | /** @brief save error pkts */ |
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| 218 | #define MSK_SEP 0x01 |
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| 219 | /** @brief accept runt pkt */ |
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| 220 | #define MSK_AR 0x02 |
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| 221 | /** @brief 8390 RCR */ |
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| 222 | #define MSK_AB 0x04 |
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| 223 | /** @brief accept multicast */ |
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| 224 | #define MSK_AM 0x08 |
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| 225 | /** @brief accept all pkt with physical adr */ |
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| 226 | #define MSK_PRO 0x10 |
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| 227 | /** @brief monitor mode */ |
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| 228 | #define MSK_MON 0x20 |
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| 229 | |
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| 230 | /** @} */ |
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| 231 | |
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| 232 | /** |
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| 233 | * @name TCR command bits |
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| 234 | * @{ |
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| 235 | */ |
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| 236 | |
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| 237 | /** @brief inhibit CRC, do not append crc */ |
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| 238 | #define MSK_CRC 0x01 |
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| 239 | /** @brief set loopback mode */ |
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| 240 | #define MSK_LOOP 0x02 |
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| 241 | /** @brief Accept broadcasts */ |
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| 242 | #define MSK_BCST 0x04 |
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| 243 | /** @brief encoded loopback control */ |
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| 244 | #define MSK_LB01 0x06 |
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| 245 | /** @brief auto tx disable */ |
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| 246 | #define MSK_ATD 0x08 |
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| 247 | /** @brief collision offset enable */ |
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| 248 | #define MSK_OFST 0x10 |
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| 249 | |
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| 250 | /** @} */ |
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| 251 | |
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| 252 | /** |
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| 253 | * @name receive status bits |
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| 254 | * @{ |
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| 255 | */ |
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| 256 | |
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| 257 | /** @brief rx without error */ |
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| 258 | #define SMK_PRX 0x01 |
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| 259 | /** @brief CRC error */ |
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| 260 | #define SMK_CRC 0x02 |
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| 261 | /** @brief frame alignment error */ |
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| 262 | #define SMK_FAE 0x04 |
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| 263 | /** @brief FIFO overrun */ |
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| 264 | #define SMK_FO 0x08 |
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| 265 | /** @brief missed pkt */ |
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| 266 | #define SMK_MPA 0x10 |
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| 267 | /** @brief physical/multicase address */ |
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| 268 | #define SMK_PHY 0x20 |
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| 269 | /** @brief receiver disable. set in monitor mode */ |
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| 270 | #define SMK_DIS 0x40 |
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| 271 | /** @brief deferring */ |
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| 272 | #define SMK_DEF 0x80 |
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| 273 | |
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| 274 | /** @} */ |
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| 275 | |
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| 276 | /** |
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| 277 | * @name transmit status bits |
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| 278 | * @{ |
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| 279 | */ |
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| 280 | |
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| 281 | /** @brief tx without error */ |
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| 282 | #define SMK_PTX 0x01 |
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| 283 | /** @brief non deferred tx */ |
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| 284 | #define SMK_DFR 0x02 |
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| 285 | /** @brief tx collided */ |
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| 286 | #define SMK_COL 0x04 |
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| 287 | /** @brief tx abort because of excessive collisions */ |
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| 288 | #define SMK_ABT 0x08 |
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| 289 | /** @brief carrier sense lost */ |
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| 290 | #define SMK_CRS 0x10 |
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| 291 | /** @brief FIFO underrun */ |
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| 292 | #define SMK_FU 0x20 |
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| 293 | /** @brief collision detect heartbeat */ |
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| 294 | #define SMK_CDH 0x40 |
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| 295 | /** @brief out of window collision */ |
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| 296 | #define SMK_OWC 0x80 |
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| 297 | |
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| 298 | /** @} */ |
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| 299 | |
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| 300 | /** @} */ |
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[a17bc42] | 301 | |
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| 302 | #endif |
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| 303 | /* end of include */ |
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