[3d6669cc] | 1 | /* |
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| 2 | * Cirrus EP7312 Startup code |
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| 3 | * |
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[8d992be9] | 4 | * Copyright (c) 2010 embedded brains GmbH. |
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| 5 | * |
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[3d6669cc] | 6 | * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com> |
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[6128a4a] | 7 | * |
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[3d6669cc] | 8 | * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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[c499856] | 12 | * http://www.rtems.org/license/LICENSE. |
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[3d6669cc] | 13 | */ |
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| 14 | |
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[511dc4b] | 15 | #include <rtems/asm.h> |
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| 16 | #include <rtems/score/cpu.h> |
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[3d6669cc] | 17 | |
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[8d992be9] | 18 | .section ".bsp_start_text", "ax" |
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| 19 | .arm |
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[3d6669cc] | 20 | |
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| 21 | /******************************************************* |
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| 22 | standard exception vectors table |
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[6128a4a] | 23 | *** Must be located at address 0 |
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| 24 | ********************************************************/ |
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[3d6669cc] | 25 | |
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[6128a4a] | 26 | Vector_Init_Block: |
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[2433a8ab] | 27 | ldr pc, handler_addr_reset |
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| 28 | ldr pc, handler_addr_undef |
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| 29 | ldr pc, handler_addr_swi |
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| 30 | ldr pc, handler_addr_prefetch |
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| 31 | ldr pc, handler_addr_abort |
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| 32 | nop |
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| 33 | ldr pc, handler_addr_irq |
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| 34 | ldr pc, handler_addr_fiq |
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| 35 | |
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| 36 | handler_addr_reset: |
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| 37 | .word _start |
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| 38 | |
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| 39 | handler_addr_undef: |
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| 40 | .word _ARMV4_Exception_undef_default |
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| 41 | |
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| 42 | handler_addr_swi: |
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| 43 | .word _ARMV4_Exception_swi_default |
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| 44 | |
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| 45 | handler_addr_prefetch: |
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| 46 | .word _ARMV4_Exception_pref_abort_default |
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| 47 | |
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| 48 | handler_addr_abort: |
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| 49 | .word _ARMV4_Exception_data_abort_default |
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| 50 | |
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| 51 | handler_addr_reserved: |
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| 52 | .word _ARMV4_Exception_reserved_default |
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| 53 | |
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| 54 | handler_addr_irq: |
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| 55 | .word _ARMV4_Exception_interrupt |
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| 56 | |
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| 57 | handler_addr_fiq: |
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| 58 | .word _ARMV4_Exception_fiq_default |
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[3d6669cc] | 59 | |
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[8d992be9] | 60 | .globl _start |
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| 61 | _start: |
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[511dc4b] | 62 | /* Set end of interrupt stack area */ |
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[ff081aee] | 63 | ldr r7, =_ISR_Stack_area_end |
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[511dc4b] | 64 | |
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| 65 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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| 66 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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| 67 | msr cpsr, r0 |
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| 68 | ldr r1, =bsp_stack_fiq_size |
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| 69 | mov sp, r7 |
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| 70 | sub r7, r7, r1 |
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| 71 | |
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| 72 | /* Enter ABT mode and set up the ABT stack pointer */ |
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| 73 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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| 74 | msr cpsr, r0 |
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| 75 | ldr r1, =bsp_stack_abt_size |
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| 76 | mov sp, r7 |
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| 77 | sub r7, r7, r1 |
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| 78 | |
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| 79 | /* Enter UND mode and set up the UND stack pointer */ |
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| 80 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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| 81 | msr cpsr, r0 |
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| 82 | ldr r1, =bsp_stack_und_size |
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| 83 | mov sp, r7 |
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| 84 | sub r7, r7, r1 |
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| 85 | |
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| 86 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 87 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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| 88 | msr cpsr, r0 |
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| 89 | mov sp, r7 |
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| 90 | |
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| 91 | /* |
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| 92 | * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack |
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| 93 | * (interrupts are disabled). |
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| 94 | */ |
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| 95 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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| 96 | msr cpsr, r0 |
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| 97 | mov sp, r7 |
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| 98 | |
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| 99 | /* Stay in SVC mode */ |
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[8d992be9] | 100 | /* |
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| 101 | * Here is the code to initialize the low-level BSP environment |
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| 102 | * (Chip Select, PLL, ....?) |
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| 103 | */ |
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| 104 | |
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| 105 | /* zero the bss */ |
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| 106 | LDR r1, =bsp_section_bss_end /* get end of ZI region */ |
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| 107 | LDR r0, =bsp_section_bss_begin /* load base address of ZI region */ |
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| 108 | |
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| 109 | zi_init: |
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| 110 | MOV r2, #0 |
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| 111 | CMP r0, r1 /* loop whilst r0 < r1 */ |
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| 112 | STRLOT r2, [r0], #4 |
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| 113 | BLO zi_init |
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| 114 | |
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[3d6669cc] | 115 | /* --- Now we enter the C code */ |
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| 116 | |
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[de237f4] | 117 | mov r0, #0 |
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| 118 | bl boot_card |
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