source: rtems/bsps/arm/edb7312/irq/irq.c @ deb5afb

Last change on this file since deb5afb was deb5afb, checked in by Sebastian Huber <sebastian.huber@…>, on 07/05/21 at 11:28:02

bsps/irq: Add rtems_interrupt_is_pending()

Add a default implementation which just returns RTEMS_UNSATISFIED.

Update #3269.

  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*
2 * Cirrus EP7312 Intererrupt handler
3 */
4
5/*
6 * Copyright (c) 2010 embedded brains GmbH.
7 *
8 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
9 *
10 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15*/
16
17#include <rtems/score/armv4.h>
18
19#include <bsp.h>
20#include <bsp/irq.h>
21#include <bsp/irq-generic.h>
22
23#include <ep7312.h>
24
25void edb7312_interrupt_dispatch(rtems_vector_number vector)
26{
27  bsp_interrupt_handler_dispatch(vector);
28}
29
30rtems_status_code bsp_interrupt_get_attributes(
31  rtems_vector_number         vector,
32  rtems_interrupt_attributes *attributes
33)
34{
35  return RTEMS_SUCCESSFUL;
36}
37
38rtems_status_code bsp_interrupt_is_pending(
39  rtems_vector_number vector,
40  bool               *pending
41)
42{
43  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
44  bsp_interrupt_assert(pending != NULL);
45  *pending = false;
46  return RTEMS_UNSATISFIED;
47}
48
49rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
50{
51  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
52  return RTEMS_UNSATISFIED;
53}
54
55rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
56{
57  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
58  return RTEMS_UNSATISFIED;
59}
60
61rtems_status_code bsp_interrupt_vector_is_enabled(
62  rtems_vector_number vector,
63  bool               *enabled
64)
65{
66  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
67  bsp_interrupt_assert(enabled != NULL);
68  *enabled = false;
69  return RTEMS_UNSATISFIED;
70}
71
72void bsp_interrupt_vector_enable(rtems_vector_number vector)
73{
74    bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
75
76    if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
77    {
78        /* interrupt managed by INTMR1 and INTSR1 */
79        *EP7312_INTMR1 |= (1 << vector);
80    }
81    else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
82    {
83        /* interrupt managed by INTMR2 and INTSR2 */
84        *EP7312_INTMR2 |= (1 << (vector - 16));
85    }
86    else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
87    {
88        /* interrupt managed by INTMR2 and INTSR2 */
89        *EP7312_INTMR2 |= (1 << (vector - 7));
90    }
91    else if(vector == BSP_DAIINT)
92    {
93        /* interrupt managed by INTMR3 and INTSR3 */
94        *EP7312_INTMR3 |= (1 << (vector - 21));
95    }
96}
97
98void bsp_interrupt_vector_disable(rtems_vector_number vector)
99{
100    bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
101
102    if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
103    {
104        /* interrupt managed by INTMR1 and INTSR1 */
105        *EP7312_INTMR1 &= ~(1 << vector);
106    }
107    else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
108    {
109        /* interrupt managed by INTMR2 and INTSR2 */
110        *EP7312_INTMR2 &= ~(1 << (vector - 16));
111    }
112    else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
113    {
114        /* interrupt managed by INTMR2 and INTSR2 */
115        *EP7312_INTMR2 &= ~(1 << (vector - 7));
116    }
117    else if(vector == BSP_DAIINT)
118    {
119        /* interrupt managed by INTMR3 and INTSR3 */
120        *EP7312_INTMR3 &= ~(1 << (vector - 21));
121    }
122}
123
124rtems_status_code bsp_interrupt_facility_initialize(void)
125{
126  uint32_t int_stat = 0;
127
128  /* mask all interrupts */
129  *EP7312_INTMR1 = 0x0;
130  *EP7312_INTMR2 = 0x0;
131  *EP7312_INTMR3 = 0x0;
132 
133  /* clear all pending interrupt status' */
134  int_stat = *EP7312_INTSR1;
135  if(int_stat & EP7312_INTR1_EXTFIQ)
136  {
137  }
138  if(int_stat & EP7312_INTR1_BLINT)
139  {
140      *EP7312_BLEOI = 0xFFFFFFFF;
141  }
142  if(int_stat & EP7312_INTR1_WEINT)
143  {
144      *EP7312_TEOI = 0xFFFFFFFF;
145  }
146  if(int_stat & EP7312_INTR1_MCINT)
147  {
148  }
149  if(int_stat & EP7312_INTR1_CSINT)
150  {
151      *EP7312_COEOI = 0xFFFFFFFF;
152  }
153  if(int_stat & EP7312_INTR1_EINT1)
154  {
155  }
156  if(int_stat & EP7312_INTR1_EINT2)
157  {
158  }
159  if(int_stat & EP7312_INTR1_EINT3)
160  {
161  }
162  if(int_stat & EP7312_INTR1_TC1OI)
163  {
164      *EP7312_TC1EOI = 0xFFFFFFFF;
165  }
166  if(int_stat & EP7312_INTR1_TC2OI)
167  {
168      *EP7312_TC2EOI = 0xFFFFFFFF;
169  }
170  if(int_stat & EP7312_INTR1_RTCMI)
171  {
172      *EP7312_RTCEOI = 0xFFFFFFFF;
173  }
174  if(int_stat & EP7312_INTR1_TINT)
175  {
176      *EP7312_TEOI = 0xFFFFFFFF;
177  }
178  if(int_stat & EP7312_INTR1_URXINT1)
179  {
180  }
181  if(int_stat & EP7312_INTR1_UTXINT1)
182  {
183  }
184  if(int_stat & EP7312_INTR1_UMSINT)
185  {
186      *EP7312_UMSEOI = 0xFFFFFFFF;
187  }
188  if(int_stat & EP7312_INTR1_SSEOTI)
189  {
190      *EP7312_SYNCIO;
191  }
192  int_stat = *EP7312_INTSR1;
193 
194  int_stat = *EP7312_INTSR2;
195  if(int_stat & EP7312_INTR2_KBDINT)
196  {
197      *EP7312_KBDEOI = 0xFFFFFFFF;
198  }
199  if(int_stat & EP7312_INTR2_SS2RX)
200  {
201  }
202  if(int_stat & EP7312_INTR2_SS2TX)
203  {
204  }
205  if(int_stat & EP7312_INTR2_URXINT2)
206  {
207  }
208  if(int_stat & EP7312_INTR2_UTXINT2)
209  {
210  }
211  int_stat = *EP7312_INTSR2;
212 
213  int_stat = *EP7312_INTSR3;
214  if(int_stat & EP7312_INTR2_DAIINT)
215  {
216  }
217  int_stat = *EP7312_INTSR3;
218
219  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
220
221  return RTEMS_SUCCESSFUL;
222}
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