source: rtems/bsps/arm/edb7312/irq/irq.c @ 32f5a195

Last change on this file since 32f5a195 was 32f5a195, checked in by Sebastian Huber <sebastian.huber@…>, on 06/29/21 at 12:06:03

bsps/irq: bsp_interrupt_vector_disable()

Return a status code for bsp_interrupt_vector_disable().

Update #3269.

  • Property mode set to 100644
File size: 5.0 KB
Line 
1/*
2 * Cirrus EP7312 Intererrupt handler
3 */
4
5/*
6 * Copyright (c) 2010 embedded brains GmbH.
7 *
8 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
9 *
10 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15*/
16
17#include <rtems/score/armv4.h>
18
19#include <bsp.h>
20#include <bsp/irq.h>
21#include <bsp/irq-generic.h>
22
23#include <ep7312.h>
24
25void edb7312_interrupt_dispatch(rtems_vector_number vector)
26{
27  bsp_interrupt_handler_dispatch(vector);
28}
29
30rtems_status_code bsp_interrupt_get_attributes(
31  rtems_vector_number         vector,
32  rtems_interrupt_attributes *attributes
33)
34{
35  return RTEMS_SUCCESSFUL;
36}
37
38rtems_status_code bsp_interrupt_is_pending(
39  rtems_vector_number vector,
40  bool               *pending
41)
42{
43  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
44  bsp_interrupt_assert(pending != NULL);
45  *pending = false;
46  return RTEMS_UNSATISFIED;
47}
48
49rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
50{
51  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
52  return RTEMS_UNSATISFIED;
53}
54
55rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
56{
57  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
58  return RTEMS_UNSATISFIED;
59}
60
61rtems_status_code bsp_interrupt_vector_is_enabled(
62  rtems_vector_number vector,
63  bool               *enabled
64)
65{
66  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
67  bsp_interrupt_assert(enabled != NULL);
68  *enabled = false;
69  return RTEMS_UNSATISFIED;
70}
71
72rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
73{
74    bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
75
76    if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
77    {
78        /* interrupt managed by INTMR1 and INTSR1 */
79        *EP7312_INTMR1 |= (1 << vector);
80    }
81    else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
82    {
83        /* interrupt managed by INTMR2 and INTSR2 */
84        *EP7312_INTMR2 |= (1 << (vector - 16));
85    }
86    else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
87    {
88        /* interrupt managed by INTMR2 and INTSR2 */
89        *EP7312_INTMR2 |= (1 << (vector - 7));
90    }
91    else if(vector == BSP_DAIINT)
92    {
93        /* interrupt managed by INTMR3 and INTSR3 */
94        *EP7312_INTMR3 |= (1 << (vector - 21));
95    }
96
97    return RTEMS_SUCCESSFUL;
98}
99
100rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
101{
102    bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
103
104    if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
105    {
106        /* interrupt managed by INTMR1 and INTSR1 */
107        *EP7312_INTMR1 &= ~(1 << vector);
108    }
109    else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
110    {
111        /* interrupt managed by INTMR2 and INTSR2 */
112        *EP7312_INTMR2 &= ~(1 << (vector - 16));
113    }
114    else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
115    {
116        /* interrupt managed by INTMR2 and INTSR2 */
117        *EP7312_INTMR2 &= ~(1 << (vector - 7));
118    }
119    else if(vector == BSP_DAIINT)
120    {
121        /* interrupt managed by INTMR3 and INTSR3 */
122        *EP7312_INTMR3 &= ~(1 << (vector - 21));
123    }
124
125    return RTEMS_SUCCESSFUL;
126}
127
128rtems_status_code bsp_interrupt_facility_initialize(void)
129{
130  uint32_t int_stat = 0;
131
132  /* mask all interrupts */
133  *EP7312_INTMR1 = 0x0;
134  *EP7312_INTMR2 = 0x0;
135  *EP7312_INTMR3 = 0x0;
136 
137  /* clear all pending interrupt status' */
138  int_stat = *EP7312_INTSR1;
139  if(int_stat & EP7312_INTR1_EXTFIQ)
140  {
141  }
142  if(int_stat & EP7312_INTR1_BLINT)
143  {
144      *EP7312_BLEOI = 0xFFFFFFFF;
145  }
146  if(int_stat & EP7312_INTR1_WEINT)
147  {
148      *EP7312_TEOI = 0xFFFFFFFF;
149  }
150  if(int_stat & EP7312_INTR1_MCINT)
151  {
152  }
153  if(int_stat & EP7312_INTR1_CSINT)
154  {
155      *EP7312_COEOI = 0xFFFFFFFF;
156  }
157  if(int_stat & EP7312_INTR1_EINT1)
158  {
159  }
160  if(int_stat & EP7312_INTR1_EINT2)
161  {
162  }
163  if(int_stat & EP7312_INTR1_EINT3)
164  {
165  }
166  if(int_stat & EP7312_INTR1_TC1OI)
167  {
168      *EP7312_TC1EOI = 0xFFFFFFFF;
169  }
170  if(int_stat & EP7312_INTR1_TC2OI)
171  {
172      *EP7312_TC2EOI = 0xFFFFFFFF;
173  }
174  if(int_stat & EP7312_INTR1_RTCMI)
175  {
176      *EP7312_RTCEOI = 0xFFFFFFFF;
177  }
178  if(int_stat & EP7312_INTR1_TINT)
179  {
180      *EP7312_TEOI = 0xFFFFFFFF;
181  }
182  if(int_stat & EP7312_INTR1_URXINT1)
183  {
184  }
185  if(int_stat & EP7312_INTR1_UTXINT1)
186  {
187  }
188  if(int_stat & EP7312_INTR1_UMSINT)
189  {
190      *EP7312_UMSEOI = 0xFFFFFFFF;
191  }
192  if(int_stat & EP7312_INTR1_SSEOTI)
193  {
194      *EP7312_SYNCIO;
195  }
196  int_stat = *EP7312_INTSR1;
197 
198  int_stat = *EP7312_INTSR2;
199  if(int_stat & EP7312_INTR2_KBDINT)
200  {
201      *EP7312_KBDEOI = 0xFFFFFFFF;
202  }
203  if(int_stat & EP7312_INTR2_SS2RX)
204  {
205  }
206  if(int_stat & EP7312_INTR2_SS2TX)
207  {
208  }
209  if(int_stat & EP7312_INTR2_URXINT2)
210  {
211  }
212  if(int_stat & EP7312_INTR2_UTXINT2)
213  {
214  }
215  int_stat = *EP7312_INTSR2;
216 
217  int_stat = *EP7312_INTSR3;
218  if(int_stat & EP7312_INTR2_DAIINT)
219  {
220  }
221  int_stat = *EP7312_INTSR3;
222
223  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
224
225  return RTEMS_SUCCESSFUL;
226}
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