source: rtems/bsps/arm/csb337/start/start.S @ ff081aee

Last change on this file since ff081aee was ff081aee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 6, 2018 at 3:58:02 PM

score: Rename interrupt stack symbols

Rename

  • _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  • _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  • _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.

Update #3459.

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Cogent CSB337 startup code
3 *
4 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9*/
10
11#include <rtems/asm.h>
12#include <rtems/score/cpu.h>
13
14.text
15.globl  _start
16_start:
17        /*
18         * Since I don't plan to return to the bootloader,
19         * I don't have to save the registers.
20         */
21
22        /* Set end of interrupt stack area */
23        ldr     r7, =_ISR_Stack_area_end
24
25        /* Enter FIQ mode and set up the FIQ stack pointer */
26        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
27        msr     cpsr, r0
28        ldr     r1, =bsp_stack_fiq_size
29        mov     sp, r7
30        sub     r7, r7, r1
31
32        /* Enter ABT mode and set up the ABT stack pointer */
33        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
34        msr     cpsr, r0
35        ldr     r1, =bsp_stack_abt_size
36        mov     sp, r7
37        sub     r7, r7, r1
38
39        /* Enter UND mode and set up the UND stack pointer */
40        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
41        msr     cpsr, r0
42        ldr     r1, =bsp_stack_und_size
43        mov     sp, r7
44        sub     r7, r7, r1
45
46        /* Enter IRQ mode and set up the IRQ stack pointer */
47        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
48        msr     cpsr, r0
49        mov     sp, r7
50
51        /*
52         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
53         * (interrupts are disabled).
54         */
55        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
56        msr     cpsr, r0
57        mov     sp, r7
58
59        /* Stay in SVC mode */
60
61        /* zero the bss */
62        ldr     r1, =bsp_section_bss_end
63        ldr     r0, =bsp_section_bss_begin
64
65_bss_init:
66        mov     r2, #0
67        cmp     r0, r1
68        strlot  r2, [r0], #4
69        blo     _bss_init        /* loop while r0 < r1 */
70
71        /*
72         * Initialize the MMU. After we return, the MMU is enabled,
73         * and memory may be remapped. I hope we don't remap this
74         * memory away.
75         */
76        ldr     r0, =mem_map
77        bl      mmu_init
78
79        /*
80         * Initialize the exception vectors. This includes the
81         * exceptions vectors (0x00000000-0x0000001c), and the
82         * pointers to the exception handlers (0x00000020-0x0000003c).
83         */
84        mov     r0, #0
85        adr     r1, vector_block
86        ldmia   r1!, {r2-r9}
87        stmia   r0!, {r2-r9}
88        ldmia   r1!, {r2-r9}
89        stmia   r0!, {r2-r9}
90
91        /* Now we are prepared to start the BSP's C code */
92        mov     r0, #0
93        bl      boot_card
94
95        /*
96         * Theoretically, we could return to what started us up,
97         * but we'd have to have saved the registers and stacks.
98         * Instead, we'll just reset.
99         */
100        bl      bsp_reset
101
102        /* We shouldn't get here. If we do, hang */
103_hang:  b       _hang
104
105
106/*
107 * This is the exception vector table and the pointers to
108 * the functions that handle the exceptions. It's a total
109 * of 16 words (64 bytes)
110 */
111vector_block:
112        ldr    pc, handler_addr_reset
113        ldr    pc, handler_addr_undef
114        ldr    pc, handler_addr_swi
115        ldr    pc, handler_addr_prefetch
116        ldr    pc, handler_addr_abort
117        nop
118        ldr    pc, handler_addr_irq
119        ldr    pc, handler_addr_fiq
120
121handler_addr_reset:
122        .word  bsp_reset
123
124handler_addr_undef:
125        .word  _ARMV4_Exception_undef_default
126
127handler_addr_swi:
128        .word  _ARMV4_Exception_swi_default
129
130handler_addr_prefetch:
131        .word  _ARMV4_Exception_pref_abort_default
132
133handler_addr_abort:
134        .word  _ARMV4_Exception_data_abort_default
135
136handler_addr_reserved:
137        .word  _ARMV4_Exception_reserved_default
138
139handler_addr_irq:
140        .word  _ARMV4_Exception_interrupt
141
142handler_addr_fiq:
143        .word  _ARMV4_Exception_fiq_default
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