[b759b04] | 1 | /* |
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| 2 | * Cogent CSB337 startup code |
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| 3 | * |
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| 4 | * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> |
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[32b8506] | 5 | * |
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[b759b04] | 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[c499856] | 8 | * http://www.rtems.org/license/LICENSE. |
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[b759b04] | 9 | */ |
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| 10 | |
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[511dc4b] | 11 | #include <rtems/asm.h> |
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| 12 | #include <rtems/score/cpu.h> |
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[b759b04] | 13 | |
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| 14 | .text |
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| 15 | .globl _start |
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| 16 | _start: |
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[32b8506] | 17 | /* |
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[b759b04] | 18 | * Since I don't plan to return to the bootloader, |
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| 19 | * I don't have to save the registers. |
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| 20 | */ |
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[32b8506] | 21 | |
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[511dc4b] | 22 | /* Set end of interrupt stack area */ |
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| 23 | ldr r7, =_Configuration_Interrupt_stack_area_end |
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[b759b04] | 24 | |
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| 25 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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[511dc4b] | 26 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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[b759b04] | 27 | msr cpsr, r0 |
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[dda95953] | 28 | ldr r1, =bsp_stack_fiq_size |
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[511dc4b] | 29 | mov sp, r7 |
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| 30 | sub r7, r7, r1 |
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[b759b04] | 31 | |
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| 32 | /* Enter ABT mode and set up the ABT stack pointer */ |
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[511dc4b] | 33 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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[b759b04] | 34 | msr cpsr, r0 |
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[dda95953] | 35 | ldr r1, =bsp_stack_abt_size |
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[511dc4b] | 36 | mov sp, r7 |
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| 37 | sub r7, r7, r1 |
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| 38 | |
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| 39 | /* Enter UND mode and set up the UND stack pointer */ |
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| 40 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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| 41 | msr cpsr, r0 |
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| 42 | ldr r1, =bsp_stack_und_size |
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| 43 | mov sp, r7 |
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| 44 | sub r7, r7, r1 |
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[32b8506] | 45 | |
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[511dc4b] | 46 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 47 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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[b759b04] | 48 | msr cpsr, r0 |
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[511dc4b] | 49 | mov sp, r7 |
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| 50 | |
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| 51 | /* |
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| 52 | * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack |
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| 53 | * (interrupts are disabled). |
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| 54 | */ |
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| 55 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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| 56 | msr cpsr, r0 |
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| 57 | mov sp, r7 |
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| 58 | |
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| 59 | /* Stay in SVC mode */ |
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| 60 | |
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| 61 | /* zero the bss */ |
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| 62 | ldr r1, =bsp_section_bss_end |
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| 63 | ldr r0, =bsp_section_bss_begin |
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| 64 | |
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| 65 | _bss_init: |
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| 66 | mov r2, #0 |
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| 67 | cmp r0, r1 |
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| 68 | strlot r2, [r0], #4 |
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| 69 | blo _bss_init /* loop while r0 < r1 */ |
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[b759b04] | 70 | |
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[32b8506] | 71 | /* |
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[b759b04] | 72 | * Initialize the MMU. After we return, the MMU is enabled, |
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| 73 | * and memory may be remapped. I hope we don't remap this |
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| 74 | * memory away. |
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| 75 | */ |
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| 76 | ldr r0, =mem_map |
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[32b8506] | 77 | bl mmu_init |
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[b759b04] | 78 | |
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[32b8506] | 79 | /* |
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[b759b04] | 80 | * Initialize the exception vectors. This includes the |
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[32b8506] | 81 | * exceptions vectors (0x00000000-0x0000001c), and the |
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[b759b04] | 82 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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| 83 | */ |
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| 84 | mov r0, #0 |
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| 85 | adr r1, vector_block |
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| 86 | ldmia r1!, {r2-r9} |
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| 87 | stmia r0!, {r2-r9} |
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| 88 | ldmia r1!, {r2-r9} |
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| 89 | stmia r0!, {r2-r9} |
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| 90 | |
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| 91 | /* Now we are prepared to start the BSP's C code */ |
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[b767616d] | 92 | mov r0, #0 |
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[b759b04] | 93 | bl boot_card |
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| 94 | |
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[32b8506] | 95 | /* |
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[b759b04] | 96 | * Theoretically, we could return to what started us up, |
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| 97 | * but we'd have to have saved the registers and stacks. |
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| 98 | * Instead, we'll just reset. |
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| 99 | */ |
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| 100 | bl bsp_reset |
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| 101 | |
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| 102 | /* We shouldn't get here. If we do, hang */ |
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| 103 | _hang: b _hang |
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| 104 | |
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[32b8506] | 105 | |
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| 106 | /* |
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[b759b04] | 107 | * This is the exception vector table and the pointers to |
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| 108 | * the functions that handle the exceptions. It's a total |
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| 109 | * of 16 words (64 bytes) |
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| 110 | */ |
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[32b8506] | 111 | vector_block: |
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[2433a8ab] | 112 | ldr pc, handler_addr_reset |
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| 113 | ldr pc, handler_addr_undef |
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| 114 | ldr pc, handler_addr_swi |
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| 115 | ldr pc, handler_addr_prefetch |
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| 116 | ldr pc, handler_addr_abort |
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[b759b04] | 117 | nop |
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[2433a8ab] | 118 | ldr pc, handler_addr_irq |
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| 119 | ldr pc, handler_addr_fiq |
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| 120 | |
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| 121 | handler_addr_reset: |
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| 122 | .word bsp_reset |
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| 123 | |
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| 124 | handler_addr_undef: |
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| 125 | .word _ARMV4_Exception_undef_default |
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| 126 | |
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| 127 | handler_addr_swi: |
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| 128 | .word _ARMV4_Exception_swi_default |
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| 129 | |
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| 130 | handler_addr_prefetch: |
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| 131 | .word _ARMV4_Exception_pref_abort_default |
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| 132 | |
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| 133 | handler_addr_abort: |
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| 134 | .word _ARMV4_Exception_data_abort_default |
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| 135 | |
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| 136 | handler_addr_reserved: |
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| 137 | .word _ARMV4_Exception_reserved_default |
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| 138 | |
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| 139 | handler_addr_irq: |
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| 140 | .word _ARMV4_Exception_interrupt |
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| 141 | |
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| 142 | handler_addr_fiq: |
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| 143 | .word _ARMV4_Exception_fiq_default |
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