source: rtems/bsps/arm/csb337/start/memmap.c @ e0dd8a5a

5
Last change on this file since e0dd8a5a was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on 04/20/18 at 08:35:35

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 * CSB337 and CSB637 (KIT637_V6) Memory map
3 *
4 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
5 * File from the old CSB337 RTEMS BSP
6 *
7 *  Modified by Joel Sherill
8 *  from OAR Corporation and
9 *  Fernando Nicodemos <fgnicodemos@terra.com.br>
10 *  from NCB - Sistemas Embarcados Ltda. (Brazil)
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 */
16
17#include <rtems.h>
18#include <libcpu/mmu.h>
19
20#include <bspopts.h>
21
22/* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than
23 * that, you'll have TLB lookups, which could hurt performance.
24 */
25mmu_sect_map_t mem_map[] = {
26/*  <phys addr>  <virt addr> <size> <flags> */
27    {0x00200000, 0x00000000,   1,    MMU_CACHE_NONE},     /* SRAM */
28    {0x00200000, 0x00200000,   1,    MMU_CACHE_NONE},     /* SRAM */
29    {0x10000000, 0x10000000,   8,    MMU_CACHE_NONE},     /* FLASH */
30#if csb637 /* CSB637 or KIT637_V6 */
31    {0x20000000, 0x20000000,  64,    MMU_CACHE_WTHROUGH}, /* SDRAM */
32#elif kit637_v6
33    {0x20000000, 0x20000000,  64,    MMU_CACHE_WTHROUGH}, /* SDRAM */
34#else /* CSB337 */
35    {0x20000000, 0x20000000,  32,    MMU_CACHE_WTHROUGH}, /* SDRAM */
36#endif
37#if ENABLE_LCD /* KIT637_V6 Video buffer */
38    {0x30000000, 0x30000000,   8,    MMU_CACHE_NONE},     /* Video buffer - 8MB */
39#else /* CSB337 Video buffer */
40    {0x30000000, 0x30000000,   1,    MMU_CACHE_NONE},     /* Video buffer - 1MB */
41#endif
42    {0x40000000, 0x40000000,   1,    MMU_CACHE_NONE},     /* Expansion CS0 */
43    {0x50000000, 0x50000000,   1,    MMU_CACHE_NONE},     /* CF CE 1 */
44    {0x60000000, 0x60000000,   1,    MMU_CACHE_NONE},     /* CF CE 1 */
45    {0x70000000, 0x70000000,   1,    MMU_CACHE_NONE},     /* CF CE 2 */
46    {0x80000000, 0x80000000,   1,    MMU_CACHE_NONE},     /* Expansion CS0 */
47    {0xfff00000, 0xfff00000,   1,    MMU_CACHE_NONE},     /* Internal regs */
48    {0x00000000, 0x00000000,   0,    0}                   /* The end */
49};
50
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