[583ef3a5] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup arm_csb337 |
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| 5 | * |
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| 6 | * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) |
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| 7 | * 16-Bit access mode |
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| 8 | */ |
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| 9 | |
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[78c4a2f] | 10 | /** |
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| 11 | * @defgroup csb337_sed1356 SED Video Controller. |
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| 12 | * |
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| 13 | * @ingroup arm_csb337 |
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| 14 | * |
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| 15 | * @brief SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) |
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| 16 | * 16-Bit access mode |
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| 17 | */ |
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| 18 | |
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[e7bde492] | 19 | /* |
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[22fb181b] | 20 | * sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637) |
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| 21 | * 16-Bit access mode |
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[e7bde492] | 22 | * |
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| 23 | * Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/ |
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| 24 | * which includes this notice: |
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| 25 | * |
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| 26 | ************************************************************************** |
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| 27 | * General notice: |
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| 28 | * This code is part of a boot-monitor package developed as a generic base |
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| 29 | * platform for embedded system designs. As such, it is likely to be |
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| 30 | * distributed to various projects beyond the control of the original |
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| 31 | * author. Please notify the author of any enhancements made or bugs found |
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| 32 | * so that all may benefit from the changes. In addition, notification back |
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| 33 | * to the author will allow the new user to pick up changes that may have |
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| 34 | * been made by other users after this version of the code was distributed. |
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| 35 | * |
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| 36 | * Note1: the majority of this code was edited with 4-space tabs. |
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| 37 | * Note2: as more and more contributions are accepted, the term "author" |
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| 38 | * is becoming a mis-representation of credit. |
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| 39 | * |
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| 40 | * Original author: Ed Sutter |
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| 41 | * Email: esutter@alcatel-lucent.com |
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| 42 | * Phone: 908-582-2351 |
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| 43 | ************************************************************************** |
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| 44 | * |
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| 45 | * Ed Sutter has been informed that this code is being used in RTEMS. |
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| 46 | * |
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[22fb181b] | 47 | * The code has been reformatted by Joel Sherrill from OAR Corporation and |
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| 48 | * Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas |
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| 49 | * Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards |
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| 50 | * and to eliminate C++ style comments. |
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[e7bde492] | 51 | */ |
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| 52 | |
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| 53 | #ifndef __sed1356_16bit_h |
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| 54 | #define __sed1356_16bit_h |
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| 55 | |
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| 56 | #include "bits.h" |
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| 57 | /*------------------------------------------------------------------------ |
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| 58 | * cpu specific code must define the following board specific macros. |
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[32b8506] | 59 | * in cpuio.h. These examples assume the SED135x has been placed in |
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[e7bde492] | 60 | * the correct endian mode via hardware. |
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[32b8506] | 61 | * #define SED_MEM_BASE 0xf0600000 <-- just example addresses, |
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[e7bde492] | 62 | * #define SED_REG_BASE 0xf0400000 <-- define for each board |
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| 63 | * #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry |
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| 64 | * #define SED_REG16(_x_) *(vushortr *)(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers |
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| 65 | * #define RD_FB16(_reg_,_val_) ((_val_) = *((vushort *)((SED_MEM_BASE + (_reg_ * SED_STEP))))) |
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| 66 | * #define WR_FB16(_reg_,_val_) (*((vushort *)((SED_MEM_BASE + (_reg_ * 2)))) = (_val_)) |
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| 67 | * Big endian processors |
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| 68 | * #define H2SED(_x_) ((((x) & 0xff00U) >> 8) | (((x) & 0x00ffU) << 8)) |
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| 69 | * Little endian |
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| 70 | * #define H2SED(_x_) (_x_) |
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| 71 | * |
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| 72 | */ |
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| 73 | |
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| 74 | /* |
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| 75 | * SED1356 registers - 16-Bit Access Mode. The first register |
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| 76 | * referenced is the even addressed register. The byte offsets |
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| 77 | * of the odd registers are shown in the comments |
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| 78 | */ |
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| 79 | #define SED1356_REG_REV_and_MISC SED_REG16(0x00) |
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| 80 | #define SED1356_REG_GPIO_CFG SED_REG16(0x04) |
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| 81 | #define SED1356_REG_GPIO_CTL SED_REG16(0x08) |
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| 82 | #define SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c) |
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| 83 | #define SED1356_REG_MCLK_CFG SED_REG16(0x10) |
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| 84 | #define SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14) |
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| 85 | #define SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18) |
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| 86 | #define SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c) |
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| 87 | #define SED1356_REG_WAIT_STATE SED_REG16(0x1e) |
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| 88 | #define SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20) |
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| 89 | #define SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a) |
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| 90 | #define SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30) |
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| 91 | /* LCD Control registers */ |
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| 92 | #define SED1356_REG_LCD_HOR_DISP SED_REG16(0x32) |
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| 93 | #define SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34) |
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| 94 | #define SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36) |
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| 95 | #define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38) |
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| 96 | #define SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a) |
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| 97 | #define SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c) |
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| 98 | #define SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40) |
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| 99 | #define SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42) |
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| 100 | #define SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44) |
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| 101 | #define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46) |
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[32b8506] | 102 | #define SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48) |
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[e7bde492] | 103 | #define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a) |
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| 104 | /* CRT/TV Control registers */ |
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| 105 | #define SED1356_REG_CRT_HOR_DISP SED_REG16(0x50) |
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| 106 | #define SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52) |
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| 107 | #define SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54) |
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| 108 | #define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56) |
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| 109 | #define SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58) |
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| 110 | #define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a) |
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| 111 | #define SED1356_REG_CRT_DISP_MODE SED_REG16(0x60) |
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| 112 | #define SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62) |
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| 113 | #define SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64) |
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| 114 | #define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66) |
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| 115 | #define SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68) |
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| 116 | #define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a) |
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| 117 | /* LCD Cursor Control Registers */ |
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| 118 | #define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70) |
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| 119 | #define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72) |
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| 120 | #define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74) |
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| 121 | #define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76) |
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[32b8506] | 122 | #define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78) |
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[e7bde492] | 123 | #define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a) |
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| 124 | #define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c) |
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| 125 | #define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e) |
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| 126 | /* CRT Cursor Control Registers */ |
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| 127 | #define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80) |
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| 128 | #define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82) |
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| 129 | #define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84) |
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| 130 | #define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86) |
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| 131 | #define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88) |
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| 132 | #define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a) |
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| 133 | #define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c) |
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| 134 | #define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e) |
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| 135 | /* BitBlt Control Registers */ |
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| 136 | #define SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100) |
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| 137 | #define SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102) |
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| 138 | #define SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104) |
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| 139 | #define SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106) |
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| 140 | #define SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108) |
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| 141 | #define SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a) |
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| 142 | #define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c) |
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| 143 | #define SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110) |
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| 144 | #define SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112) |
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| 145 | #define SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114) |
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| 146 | #define SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118) |
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| 147 | /* Look-Up Table Control Registers */ |
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| 148 | #define SED1356_REG_LUT_MODE SED_REG16(0x1e0) |
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| 149 | #define SED1356_REG_LUT_ADD SED_REG16(0x1e2) |
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| 150 | #define SED1356_REG_LUT_DATA SED_REG16(0x1e4) |
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| 151 | /* Power and Miscellaneous Control Registers */ |
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| 152 | #define SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0) |
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| 153 | #define SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4) |
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| 154 | #define SED1356_REG_DISP_MODE SED_REG16(0x1fc) |
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| 155 | |
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| 156 | /* |
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| 157 | * Bit Assignments - Little Endian, Use H2SED() macro to access |
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| 158 | * |
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| 159 | * SED1356_REG_REV_and_MISC - even |
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| 160 | */ |
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| 161 | #define SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */ |
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| 162 | #define SED1356_REV_ID_1356 BIT4 |
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| 163 | #define SED1356_REV_ID_1355 BIT3 |
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| 164 | |
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| 165 | /* SED1356_REG_REV_and_MISC - odd */ |
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| 166 | #define SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */ |
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| 167 | |
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| 168 | /* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */ |
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| 169 | #define SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */ |
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| 170 | #define SED1356_GPIO_GPIO2 BIT2 |
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| 171 | #define SED1356_GPIO_GPIO1 BIT1 |
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| 172 | |
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| 173 | /* SED1356_REG_MCLK_CFG */ |
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[32b8506] | 174 | #define SED1356_MCLK_DIV2 BIT4 |
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| 175 | #define SED1356_MCLK_SRC_BCLK BIT0 |
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[e7bde492] | 176 | #define SED1356_MCLK_SRC_CLKI 0x00 |
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| 177 | |
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| 178 | /* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG |
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| 179 | * and SED1356_REG_MEDIA_PCLK_CFG |
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| 180 | */ |
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| 181 | #define SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */ |
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| 182 | #define SED1356_PCLK_DIV1 0x00 << 4 |
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| 183 | #define SED1356_PCLK_DIV2 0x01 << 4 |
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| 184 | #define SED1356_PCLK_DIV3 0x02 << 4 |
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| 185 | #define SED1356_PCLK_DIV4 0x03 << 4 |
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| 186 | #define SED1356_PCLK_SRC_CLKI 0x00 |
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| 187 | #define SED1356_PCLK_SRC_BCLK 0x01 |
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| 188 | #define SED1356_PCLK_SRC_CLKI2 0x02 |
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| 189 | #define SED1356_PCLK_SRC_MCLK 0x03 |
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| 190 | |
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| 191 | /* SED1356_REG_MEM_CFG_and_REF_RATE - even */ |
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[32b8506] | 192 | #define SED1356_MEM_CFG_2CAS_EDO 0x00 |
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| 193 | #define SED1356_MEM_CFG_2CAS_FPM 0x01 |
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| 194 | #define SED1356_MEM_CFG_2WE_EDO 0x02 |
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| 195 | #define SED1356_MEM_CFG_2WE_FPM 0x03 |
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| 196 | #define SED1356_MEM_CFG_MASK 0x03 |
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[e7bde492] | 197 | |
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| 198 | /* SED1356_REG_MEM_CFG_and_REF_RATE - odd */ |
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| 199 | #define SED1356_REF_TYPE_CBR 0x00 << 6 << 8 |
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| 200 | #define SED1356_REF_TYPE_SELF 0x01 << 6 << 8 |
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| 201 | #define SED1356_REF_TYPE_NONE 0x02 << 6 << 8 |
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| 202 | #define SED1356_REF_TYPE_MASK 0x03 << 6 << 8 |
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| 203 | #define SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */ |
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| 204 | #define SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */ |
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| 205 | #define SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */ |
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| 206 | #define SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */ |
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| 207 | #define SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */ |
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| 208 | #define SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */ |
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| 209 | #define SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */ |
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| 210 | #define SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */ |
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| 211 | #define SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */ |
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| 212 | |
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| 213 | /* SED1356_REG_MEM_TMG0_and_1 - even */ |
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| 214 | #define SED1356_MEM_TMG0_EDO50_MCLK40 0x01 |
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| 215 | #define SED1356_MEM_TMG0_EDO50_MCLK33 0x01 |
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| 216 | #define SED1356_MEM_TMG0_EDO60_MCLK33 0x01 |
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| 217 | #define SED1356_MEM_TMG0_EDO50_MCLK30 0x12 |
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| 218 | #define SED1356_MEM_TMG0_EDO60_MCLK30 0x01 |
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| 219 | #define SED1356_MEM_TMG0_EDO70_MCLK30 0x00 |
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| 220 | #define SED1356_MEM_TMG0_EDO50_MCLK25 0x12 |
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| 221 | #define SED1356_MEM_TMG0_EDO60_MCLK25 0x12 |
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| 222 | #define SED1356_MEM_TMG0_EDO70_MCLK25 0x01 |
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| 223 | #define SED1356_MEM_TMG0_EDO80_MCLK25 0x00 |
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| 224 | #define SED1356_MEM_TMG0_EDO50_MCLK20 0x12 |
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| 225 | #define SED1356_MEM_TMG0_EDO60_MCLK20 0x12 |
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| 226 | #define SED1356_MEM_TMG0_EDO70_MCLK20 0x12 |
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| 227 | #define SED1356_MEM_TMG0_EDO80_MCLK20 0x01 |
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| 228 | #define SED1356_MEM_TMG0_FPM50_MCLK25 0x12 |
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| 229 | #define SED1356_MEM_TMG0_FPM60_MCLK25 0x01 |
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| 230 | #define SED1356_MEM_TMG0_FPM50_MCLK20 0x12 |
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| 231 | #define SED1356_MEM_TMG0_FPM60_MCLK20 0x12 |
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| 232 | #define SED1356_MEM_TMG0_FPM70_MCLK20 0x11 |
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| 233 | #define SED1356_MEM_TMG0_FPM80_MCLK20 0x01 |
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| 234 | |
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| 235 | /* SED1356_REG_MEM_TMG0_and_1 - odd */ |
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| 236 | #define SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8 |
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| 237 | #define SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8 |
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| 238 | #define SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8 |
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| 239 | #define SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8 |
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| 240 | #define SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8 |
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| 241 | #define SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8 |
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| 242 | #define SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8 |
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| 243 | #define SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8 |
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| 244 | #define SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8 |
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| 245 | #define SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8 |
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| 246 | #define SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8 |
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| 247 | #define SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8 |
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| 248 | #define SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8 |
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| 249 | #define SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8 |
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| 250 | #define SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8 |
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| 251 | #define SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8 |
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| 252 | #define SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8 |
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| 253 | #define SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8 |
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| 254 | #define SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8 |
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| 255 | #define SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8 |
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| 256 | |
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| 257 | |
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[32b8506] | 258 | /* Bit definitions |
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[e7bde492] | 259 | * |
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| 260 | * SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even |
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| 261 | */ |
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| 262 | #define SED1356_PANEL_TYPE_EL BIT7 |
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| 263 | #define SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */ |
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| 264 | #define SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */ |
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| 265 | #define SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */ |
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| 266 | #define SED1356_PANEL_TYPE_MASK (0x03 << 4) |
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| 267 | #define SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */ |
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| 268 | #define SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */ |
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| 269 | #define SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */ |
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| 270 | #define SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */ |
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| 271 | |
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| 272 | /* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE, |
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| 273 | * SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE |
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| 274 | */ |
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| 275 | #define SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ |
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| 276 | #define SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */ |
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| 277 | #define SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */ |
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| 278 | |
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| 279 | /* SED1356_LCD_DISP_MODE_and_MISC - even */ |
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| 280 | #define SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */ |
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| 281 | #define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */ |
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| 282 | #define SED1356_LCD_DISP_SWIV_90 (0x00 << 4) |
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| 283 | #define SED1356_LCD_DISP_SWIV_180 (0x01 << 4) |
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| 284 | #define SED1356_LCD_DISP_SWIV_270 (0x01 << 4) |
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| 285 | #define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4) |
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| 286 | #define SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ |
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| 287 | #define SED1356_LCD_DISP_15BPP 0x04 |
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| 288 | #define SED1356_LCD_DISP_8BPP 0x03 |
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| 289 | #define SED1356_LCD_DISP_4BPP 0x02 |
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| 290 | #define SED1356_LCD_DISP_BPP_MASK 0x07 |
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| 291 | |
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| 292 | /* SED1356_LCD_DISP_MODE_and_MISC - odd */ |
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| 293 | #define SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */ |
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| 294 | #define SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */ |
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| 295 | |
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| 296 | /* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */ |
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| 297 | #define SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */ |
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| 298 | #define SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */ |
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| 299 | #define SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */ |
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| 300 | #define SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */ |
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| 301 | #define SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */ |
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| 302 | |
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| 303 | /* SED1356_REG_CRT_DISP_MODE */ |
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| 304 | #define SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */ |
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| 305 | #define SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */ |
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| 306 | #define SED1356_CRT_DISP_15BPP 0x04 |
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| 307 | #define SED1356_CRT_DISP_8BPP 0x03 |
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| 308 | #define SED1356_CRT_DISP_4BPP 0x02 |
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| 309 | #define SED1356_CRT_DISP_BPP_MASK 0x07 |
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| 310 | |
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| 311 | /* SED1356_DISP_MODE */ |
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| 312 | #define SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */ |
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| 313 | #define SED1356_DISP_SWIV_90 (0x01 << 6) |
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| 314 | #define SED1356_DISP_SWIV_180 (0x00 << 6) |
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| 315 | #define SED1356_DISP_SWIV_270 (0x01 << 6) |
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| 316 | #define SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */ |
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| 317 | #define SED1356_DISP_MODE_LCD 0x01 /* LCD Only */ |
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| 318 | #define SED1356_DISP_MODE_CRT 0x02 /* CRT Only */ |
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| 319 | #define SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */ |
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| 320 | #define SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */ |
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| 321 | #define SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */ |
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| 322 | #define SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */ |
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| 323 | #define SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */ |
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| 324 | |
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| 325 | /* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */ |
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| 326 | #define SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */ |
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| 327 | #define SED1356_PWR_MCLK BIT0 |
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| 328 | |
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| 329 | /* SED1356_REG_VER_NONDISP */ |
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| 330 | #define SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */ |
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| 331 | |
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| 332 | /* Display size defines */ |
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| 333 | extern long PIXELS_PER_ROW; |
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| 334 | extern long PIXELS_PER_COL; |
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| 335 | #define BYTES_PER_PIXEL 2 |
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| 336 | extern long COLS_PER_SCREEN; |
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| 337 | extern long ROWS_PER_SCREEN; |
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| 338 | |
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| 339 | /* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the */ |
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| 340 | /* LCD Interface, while the LSB of GREEN is loaded as 0 */ |
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| 341 | #define RED_SUBPIXEL(n) ((n & 0x1f) << 11) |
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| 342 | #define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5) |
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| 343 | #define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0) |
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| 344 | |
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| 345 | /* define a simple VGA style 16-color pallette */ |
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| 346 | #if 0 |
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| 347 | #define LU_BLACK (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) |
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| 348 | #define LU_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) |
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| 349 | #define LU_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) |
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| 350 | #define LU_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) |
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| 351 | #define LU_RED (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) |
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| 352 | #define LU_VIOLET (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x0f)) |
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| 353 | #define LU_YELLOW (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x00)) |
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| 354 | #define LU_GREY (RED_SUBPIXEL(0x0f) | GREEN_SUBPIXEL(0x0f) | BLUE_SUBPIXEL(0x0f)) |
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| 355 | #define LU_WHITE (RED_SUBPIXEL(0x17) | GREEN_SUBPIXEL(0x17) | BLUE_SUBPIXEL(0x17)) |
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| 356 | #define LU_BRT_BLUE (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) |
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| 357 | #define LU_BRT_GREEN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) |
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| 358 | #define LU_BRT_CYAN (RED_SUBPIXEL(0x00) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) |
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| 359 | #define LU_BRT_RED (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x00)) |
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| 360 | #define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x00) | BLUE_SUBPIXEL(0x1f)) |
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| 361 | #define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x00)) |
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| 362 | #define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) | GREEN_SUBPIXEL(0x1f) | BLUE_SUBPIXEL(0x1f)) |
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| 363 | /* RED, GREEN, BLUE Entry */ |
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| 364 | { 0x00, 0x00, 0x00, }, /* LU_BLACK */ |
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| 365 | { 0x00, 0x00, 0xA0, }, /* LU_BLUE */ |
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| 366 | { 0x00, 0xA0, 0x00, }, /* LU_GREEN */ |
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| 367 | { 0x00, 0xA0, 0xA0, }, /* LU_CYAN */ |
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| 368 | { 0xA0, 0x00, 0x00, }, /* LU_RED */ |
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| 369 | { 0xA0, 0x00, 0xA0, }, /* LU_VIOLET */ |
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| 370 | { 0xA0, 0xA0, 0x00, }, /* LU_YELLOW */ |
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| 371 | { 0xA0, 0xA0, 0xA0, }, /* LU_WHITE */ |
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| 372 | { 0x50, 0x50, 0x50, }, /* LU_GREY */ |
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| 373 | { 0x50, 0x50, 0xF0, }, /* LU_BRT_BLUE */ |
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| 374 | { 0x50, 0xF0, 0x50, }, /* LU_BRT_GREEN */ |
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| 375 | { 0x50, 0xF0, 0xF0, }, /* LU_BRT_CYAN */ |
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| 376 | { 0xF0, 0x50, 0x50, }, /* LU_BRT_RED */ |
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| 377 | { 0xF0, 0x50, 0xF0, }, /* LU_BRT_VIOLET */ |
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| 378 | { 0xF0, 0xF0, 0x50, }, /* LU_BRT_YELLOW */ |
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| 379 | { 0xF0, 0xF0, 0xF0, }, /* LU_BRT_WHITE */ |
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| 380 | #endif |
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| 381 | |
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| 382 | #define BLUE (0x14 << 0) |
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| 383 | #define GREEN (0x14 << 6) |
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| 384 | #define RED (0x14 << 11) |
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| 385 | |
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| 386 | #define HALF_BLUE (0x0a << 0) |
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| 387 | #define HALF_GREEN (0x0a << 6) |
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| 388 | #define HALF_RED (0x0a << 11) |
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| 389 | |
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| 390 | |
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| 391 | #define BRT_BLUE (0x1e << 0) |
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| 392 | #define BRT_GREEN (0x1e << 6) |
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| 393 | #define BRT_RED (0x1e << 11) |
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| 394 | |
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| 395 | #define LU_BLACK 0 |
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| 396 | #define LU_BLUE (BLUE) |
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| 397 | #define LU_GREEN (GREEN) |
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| 398 | #define LU_CYAN (GREEN | BLUE) |
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| 399 | #define LU_RED (RED) |
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| 400 | #define LU_VIOLET (RED | BLUE) |
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| 401 | #define LU_YELLOW (RED | GREEN) |
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| 402 | #define LU_WHITE (RED | GREEN | BLUE) |
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| 403 | #define LU_GREY (HALF_RED | HALF_GREEN | HALF_BLUE) |
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| 404 | #define LU_BRT_BLUE (HALF_RED | HALF_GREEN | BRT_BLUE) |
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| 405 | #define LU_BRT_GREEN (HALF_RED | BRT_GREEN | HALF_BLUE) |
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| 406 | #define LU_BRT_CYAN (HALF_RED | BRT_GREEN | BRT_BLUE) |
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| 407 | #define LU_BRT_RED (BRT_RED | HALF_GREEN | HALF_BLUE) |
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| 408 | #define LU_BRT_VIOLET (BRT_RED | HALF_GREEN | BRT_BLUE) |
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| 409 | #define LU_BRT_YELLOW (BRT_RED | BRT_GREEN | HALF_BLUE) |
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| 410 | #define LU_BRT_WHITE (BRT_RED | BRT_GREEN | BRT_BLUE) |
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| 411 | |
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| 412 | const ushort vga_lookup[] = { |
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| 413 | LU_BLACK, /* 0 */ |
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| 414 | LU_BLUE, /* 1 */ |
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| 415 | LU_GREEN, /* 2 */ |
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| 416 | LU_CYAN, /* 3 */ |
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| 417 | LU_RED, /* 4 */ |
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| 418 | LU_VIOLET, /* 5 */ |
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| 419 | LU_YELLOW, /* 6 */ |
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| 420 | LU_WHITE, /* 7 */ |
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| 421 | LU_GREY, /* 8 */ |
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| 422 | LU_BRT_BLUE, /* 9 */ |
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| 423 | LU_BRT_GREEN, /* 10 */ |
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| 424 | LU_BRT_CYAN, /* 11 */ |
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| 425 | LU_BRT_RED, /* 12 */ |
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| 426 | LU_BRT_VIOLET, /* 13 */ |
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| 427 | LU_BRT_YELLOW, /* 14 */ |
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| 428 | LU_BRT_WHITE /* 15 */ |
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| 429 | }; |
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| 430 | |
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| 431 | /* default foreground and background colors */ |
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| 432 | #define SED_BG_DEF 1 |
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| 433 | #define SED_FG_DEF 14 |
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| 434 | |
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| 435 | /* Draw defines */ |
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| 436 | #define TOP 0 |
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| 437 | #define BOTTOM (PIXELS_PER_COL-1) |
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| 438 | #define LEFT 0 |
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| 439 | #define RIGHT (PIXELS_PER_ROW-1) |
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| 440 | #define CENTER_X (PIXELS_PER_ROW/2) |
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| 441 | #define CENTER_Y (PIXELS_PER_COL/2) |
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| 442 | |
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| 443 | |
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| 444 | /* Vertical and Horizontal Pulse, Start and Non-Display values vary depending |
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| 445 | * upon the mode. The following section gives some insight into how the |
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| 446 | * values are arrived at. |
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[32b8506] | 447 | * ms = milliseconds, us = microseconds, ns = nanoseconds |
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| 448 | * Mhz = Megaherz, Khz = Kiloherz, Hz = Herz |
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[e7bde492] | 449 | * |
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[32b8506] | 450 | * *************************************************************************************************** |
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[e7bde492] | 451 | * CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns) |
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[32b8506] | 452 | * *************************************************************************************************** |
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[e7bde492] | 453 | * |
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[32b8506] | 454 | * CRT MODE HORIZONTAL TIMING PARAMETERS |
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[e7bde492] | 455 | * |
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[32b8506] | 456 | * |<-------Tha------->| |
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| 457 | * |___________________| ______ |
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| 458 | * Display Enable _____________________| |____________________| |
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| 459 | * | | |
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| 460 | * Horizontal Pulse __ ________|___________________|________ __________ |
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| 461 | * |_________| | | |________| |
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| 462 | * |<- Thp ->| | | | |
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| 463 | * | |<-Thbp->| | | |
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| 464 | * | |<-Thfp->| |
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| 465 | * |<----------------------Tht-------------------->| |
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[e7bde492] | 466 | * |
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[32b8506] | 467 | * Tha - Active Display Time = 640 pixels |
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| 468 | * Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels |
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| 469 | * Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels |
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| 470 | * Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels |
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| 471 | * Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz |
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[e7bde492] | 472 | * |
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[32b8506] | 473 | * Correlation between horizontal timing parameters and SED registers |
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[e7bde492] | 474 | */ |
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| 475 | #define SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */ |
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| 476 | #define SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */ |
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| 477 | #define SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */ |
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| 478 | /* |
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[32b8506] | 479 | * CRT MODE VERTICAL TIMING PARAMTERS |
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[e7bde492] | 480 | * |
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[32b8506] | 481 | * |<-------Tva------->| |
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| 482 | * |___________________| ______ |
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| 483 | * Display Enable _____________________| |_____________________| |
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| 484 | * | | |
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| 485 | * Vertical Pulse __ ________|___________________|________ __________ |
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| 486 | * |_________| | | |________| |
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| 487 | * |<- Tvp ->| | | | |
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| 488 | * | |<-Tvbp->| | | |
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| 489 | * | |<-Tvfp->| |
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| 490 | * |<----------------------Tvt-------------------->| |
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[e7bde492] | 491 | * |
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[32b8506] | 492 | * Tva - Active Display Time = 480 lines |
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| 493 | * Tvp - Vertical Pulse = 3 lines |
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| 494 | * Tvfp - Vertical Front Porch = 9 lines |
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| 495 | * Tvbp - Vertical Back Porch = 28 lines |
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| 496 | * Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz |
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[e7bde492] | 497 | * |
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[32b8506] | 498 | * Correlation between vertical timing parameters and SED registers |
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[e7bde492] | 499 | */ |
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| 500 | #define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 |
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[32b8506] | 501 | #define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1 |
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[e7bde492] | 502 | #define SED_VER_NONDISP_CRT 0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 |
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| 503 | /* |
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[32b8506] | 504 | ***************************************************************************************************** |
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[e7bde492] | 505 | * DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns) |
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[32b8506] | 506 | ***************************************************************************************************** |
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[e7bde492] | 507 | * |
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[32b8506] | 508 | * LCD MODE HORIZONTAL TIMING PARAMTERS |
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[e7bde492] | 509 | * |
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[32b8506] | 510 | * |<-------Tha------->| |
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| 511 | * |___________________| ______ |
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| 512 | * Display Enable _____________________| |____________________| |
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| 513 | * | | |
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| 514 | * Horizontal Pulse __ ________|___________________|________ __________ |
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| 515 | * |_________| | | |________| |
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| 516 | * |<- Thp ->| | | | |
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| 517 | * | |<-Thbp->| | | |
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| 518 | * | |<-Thfp->| |
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| 519 | * |<----------------------Tht-------------------->| |
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[e7bde492] | 520 | * |
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[32b8506] | 521 | * Tha - Active Display Time = 640 pixels |
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| 522 | * Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels |
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| 523 | * Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels |
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| 524 | * Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels |
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| 525 | * Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz |
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[e7bde492] | 526 | * |
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[32b8506] | 527 | * Correlation between horizontal timing parameters and SED registers |
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[e7bde492] | 528 | *#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1 |
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| 529 | *#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2 |
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| 530 | *#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 |
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| 531 | */ |
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| 532 | extern long SED_HOR_PULSE_WIDTH_LCD; |
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| 533 | extern long SED_HOR_PULSE_START_LCD; |
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| 534 | extern long SED_HOR_NONDISP_LCD; |
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| 535 | |
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| 536 | /* |
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| 537 | * |
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[32b8506] | 538 | * LCD MODE VERTICAL TIMING PARAMTERS |
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[e7bde492] | 539 | * |
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[32b8506] | 540 | * |<-------Tva------->| |
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| 541 | * |___________________| ______ |
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| 542 | * Display Enable _____________________| |_____________________| |
---|
| 543 | * | | |
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| 544 | * Vertical Pulse __ ________|___________________|________ __________ |
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| 545 | * |_________| | | |________| |
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| 546 | * |<- Tvp ->| | | | |
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| 547 | * | |<-Tvbp->| | | |
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| 548 | * | |<-Tvfp->| |
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| 549 | * |<----------------------Tvt-------------------->| |
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[e7bde492] | 550 | * |
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[32b8506] | 551 | * Tva - Active Display Time = 480 lines |
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| 552 | * Tvp - Vertical Pulse = 2 lines |
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| 553 | * Tvfp - Vertical Front Porch = 10 lines |
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| 554 | * Tvbp - Vertical Backporch = 33 lines |
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| 555 | * Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz |
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[e7bde492] | 556 | * |
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[32b8506] | 557 | * Correlation between vertical timing parameters and SED registers |
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[e7bde492] | 558 | *#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1 |
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[32b8506] | 559 | *#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1 |
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[e7bde492] | 560 | *#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1 |
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| 561 | */ |
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| 562 | extern long SED_VER_PULSE_WIDTH_LCD; |
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| 563 | extern long SED_VER_PULSE_START_LCD; |
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| 564 | extern long SED_VER_NONDISP_LCD; |
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| 565 | |
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| 566 | #endif |
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