source: rtems/bsps/arm/csb337/include/at91rm9200_dbgu.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Atmel AT91RM9200_DBGU Register definitions
3 *
4 * Copyright (c) 2003 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11#ifndef __AT91RM9200_DBGU_H__
12#define __AT91RM9200_DBGU_H__
13
14#include "bits.h"
15
16/* Register Offsets */
17#define DBGU_CR         0x00            /* Control Register */
18#define DBGU_MR         0x04            /* Mode Register */
19#define DBGU_IER        0x08            /* Interrupt Enable Register */
20#define DBGU_IDR        0x0C            /* Interrupt Disable Register */
21#define DBGU_IMR        0x10            /* Interrupt Mask Register */
22#define DBGU_SR         0x14            /* Channel Status Register */
23#define DBGU_RHR        0x18            /* Receiver Holding Register */
24#define DBGU_THR        0x1C            /* Transmitter Holding Register */
25#define DBGU_BRGR       0x20            /* Baud Rate Generator Register */
26#define DBGU_C1R        0x40            /* Chip ID1 Register */
27#define DBGU_C2R        0x44            /* Chip ID2 Register */
28#define DBGU_FNTR       0x48            /* Force NTRST Register */
29
30/* Bit Defines */
31/* Control Register, DBGU_CR, Offset 0x00 */
32#define DBGU_CR_RSTRX   BIT2            /* 1 = Reset and disable receiver */
33#define DBGU_CR_RSTTX   BIT3            /* 1 = Reset and disable transmitter */
34#define DBGU_CR_RXEN    BIT4            /* 1 = Receiver enable */
35#define DBGU_CR_RXDIS   BIT5            /* 1 = Receiver disable */
36#define DBGU_CR_TXEN    BIT6            /* 1 = Transmitter enable */
37#define DBGU_CR_TXDIS   BIT7            /* 1 = Transmitter disable */
38#define DBGU_CR_RSTSTA  BIT8            /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
39
40/* Mode Register. DBGU_MR. Offset 0x04 */
41#define DBGU_MR_PAR_EVEN    (0x0 <<  9) /* Even Parity */
42#define DBGU_MR_PAR_ODD     (0x1 <<  9) /* Odd Parity */
43#define DBGU_MR_PAR_SPACE   (0x2 <<  9) /* Parity forced to 0 (Space) */
44#define DBGU_MR_PAR_MARK    (0x3 <<  9) /* Parity forced to 1 (Mark) */
45#define DBGU_MR_PAR_NONE    (0x4 <<  9) /* No Parity */
46#define DBGU_MR_PAR_MDROP   (0x6 <<  9) /* Multi-drop mode */
47#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */
48#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */
49#define DBGU_MR_CHMODE_LOC  (0x2 << 14) /* Local Loopback: TXD drives RXD */
50#define DBGU_MR_CHMODE_REM  (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
51
52/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */
53/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */
54/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */
55/* Channel Status Register, DBGU_SR, Offset 0x14 */
56#define DBGU_INT_RXRDY      BIT0        /* RXRDY Interrupt */
57#define DBGU_INT_TXRDY      BIT1        /* TXRDY Interrupt */
58#define DBGU_INT_ENDRX      BIT3        /* End of Receive Transfer Interrupt */
59/*efine DBGU_INT_ENDTX      BIT4        /* End of Transmit Interrupt */
60#define DBGU_INT_OVRE       BIT5        /* Overrun Interrupt */
61#define DBGU_INT_FRAME      BIT6        /* Framing Error Interrupt */
62#define DBGU_INT_PARE       BIT7        /* Parity Error Interrupt */
63#define DBGU_INT_TXEMPTY    BIT9        /* TXEMPTY Interrupt */
64#define DBGU_INT_TXBUFE     BIT11       /* TXBUFE Interrupt */
65#define DBGU_INT_RXBUFF     BIT12       /* RXBUFF Interrupt */
66#define DBGU_INT_COMM_TX    BIT30       /* COMM_TX Interrupt */
67#define DBGU_INT_COMM_RX    BIT31       /* COMM_RX Interrupt */
68#define DBGU_INT_ALL        0xC0001AFB  /* all assigned bits */
69
70/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */
71#define DBGU_FNTR_NTRST         BIT0    /* 1 = Force NTRST low in JTAG */
72
73typedef struct {
74    volatile uint32_t cr;
75    volatile uint32_t mr;
76    volatile uint32_t ier;
77    volatile uint32_t idr;
78    volatile uint32_t imr;
79    volatile uint32_t sr;
80    volatile uint32_t rhr;
81    volatile uint32_t thr;
82    volatile uint32_t brgr;
83    volatile uint32_t _res0[7];
84    volatile uint32_t cidr;
85    volatile uint32_t exid;
86    volatile uint32_t fnr;
87} at91rm9200_dbgu_regs_t;
88
89#endif /* __AT91RM9200_DBGU_H__ */
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