source: rtems/bsps/arm/csb337/include/at91rm9200.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 16.7 KB
Line 
1/*
2 * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637)
3 *
4 * Copyright (c) 2003 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *
7 * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
8 * from NCB - Sistemas Embarcados Ltda. (Brazil)
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13*/
14
15
16#ifndef __AT91RM9200_H__
17#define __AT91RM9200_H__
18
19#include "bits.h"
20
21typedef volatile unsigned long vulong;
22
23/* Source Mode Register - 32 of them */
24#define AIC_SMR_BASE            0xFFFFF000
25#define AIC_SMR_REG(_x_)        *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c))
26
27/* Source Vector Register - 32 of them */
28#define AIC_SVR_BASE            0xFFFFF080
29#define AIC_SVR_REG(_x_)        *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
30
31/* Control Register - 32 of them */
32#define AIC_CTL_BASE            0xFFFFF100
33#define AIC_CTL_REG(_x_)        *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
34
35/* Register Offsets */
36/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */
37#define AIC_SMR_FIQ             0x00    /* Advanced Interrupt Controller FIQ */
38#define AIC_SMR_SYSIRQ          0x04    /* Advanced Interrupt Controller SYSIRQ */
39#define AIC_SMR_PIOA            0x08    /* Parallel I/O Controller A */
40#define AIC_SMR_PIOB            0x0c    /* Parallel I/O Controller B */
41#define AIC_SMR_PIOC            0x10    /* Parallel I/O Controller C */
42#define AIC_SMR_PIOD            0x14    /* Parallel I/O Controller D */
43#define AIC_SMR_US0             0x18    /* USART 0 */
44#define AIC_SMR_US1             0x1c    /* USART 1 */
45#define AIC_SMR_US2             0x20    /* USART 2 */
46#define AIC_SMR_US3             0x24    /* USART 3 */
47#define AIC_SMR_MCI             0x28    /* Multimedia Card Interface */
48#define AIC_SMR_UDP             0x2c    /* USB Device Port */
49#define AIC_SMR_TWI             0x30    /* Two-wire Interface */
50#define AIC_SMR_SPI             0x34    /* Serial Peripheral Interface */
51#define AIC_SMR_SSC0            0x38    /* Synchronous Serial Controller 0 */
52#define AIC_SMR_SSC1            0x3c    /* Synchronous Serial Controller 1 */
53#define AIC_SMR_SSC2            0x40    /* Synchronous Serial Controller 2 */
54#define AIC_SMR_TC0             0x44    /* Timer/Counter 0 */
55#define AIC_SMR_TC1             0x48    /* Timer/Counter 1 */
56#define AIC_SMR_TC2             0x4c    /* Timer/Counter 2 */
57#define AIC_SMR_TC3             0x50    /* Timer/Counter 3 */
58#define AIC_SMR_TC4             0x54    /* Timer/Counter 4 */
59#define AIC_SMR_TC5             0x58    /* Timer/Counter 5 */
60#define AIC_SMR_UHP             0x5c    /* USB Host Port */
61#define AIC_SMR_EMAC            0x60    /* Ethernet MAC */
62#define AIC_SMR_IRQ0            0x64    /* Advanced Interrupt Controller IRQ0 */
63#define AIC_SMR_IRQ1            0x68    /* Advanced Interrupt Controller IRQ1 */
64#define AIC_SMR_IRQ2            0x6c    /* Advanced Interrupt Controller IRQ2 */
65#define AIC_SMR_IRQ3            0x70    /* Advanced Interrupt Controller IRQ3 */
66#define AIC_SMR_IRQ4            0x74    /* Advanced Interrupt Controller IRQ4 */
67#define AIC_SMR_IRQ5            0x78    /* Advanced Interrupt Controller IRQ5 */
68#define AIC_SMR_IRQ6            0x7c    /* Advanced Interrupt Controller IRQ6 */
69
70/* from AIC_CTL_BASE */
71#define AIC_IVR                 0x00    /* IRQ Vector Register */
72#define AIC_FVR                 0x04    /* FIQ Vector Register */
73#define AIC_ISR                 0x08    /* Interrupt Status Register */
74#define AIC_IPR                 0x0C    /* Interrupt Pending Register */
75#define AIC_IMR                 0x10    /* Interrupt Mask Register */
76#define AIC_CISR                0x14    /* Core Interrupt Status Register */
77#define AIC_IECR                0x20    /* Interrupt Enable Command Register */
78#define AIC_IDCR                0x24    /* Interrupt Disable Command Register */
79#define AIC_ICCR                0x28    /* Interrupt Clear Command Register */
80#define AIC_ISCR                0x2C    /* Interrupt Set Command Register */
81#define AIC_EOICR               0x30    /* End of Interrupt Command Register */
82#define AIC_SPU                 0x34    /* Spurious Vector Register */
83#define AIC_DCR                 0x38    /* Debug Control Register (Protect) */
84#define AIC_FFER                0x40    /* Fast Forcing Enable Register */
85#define AIC_FFDR                0x44    /* Fast Forcing Disable Register */
86#define AIC_FFSR                0x48    /* Fast Forcing Status Register */
87
88/* Bit Defines */
89/* AIC_ISR - Interrupt Status Register */
90#define AIC_ISR_IRQID_MASK      0x1f    /* current interrupt ID          */
91
92/* AIC_CISR - Core Interrupt Status Register */
93#define AIC_CISR_IRQ            BIT1    /* 1 = Core IRQ is active */
94#define AIC_CISR_FIQ            BIT0    /* 1 = Core FIQ is active */
95
96/* AIC_DCR - Debug Control Register (Protect) */
97#define AIC_DCR_GMSK            BIT1    /* 0 = AIC controls IRQ and FIQ */
98#define AIC_DCR_PROT            BIT0    /* 1 = enable protection mode */
99
100/* AIC_SMR */
101#define AIC_SMR_PRIOR(_x_)      ((_x_ & 0x07) << 0)
102#define AIC_SMR_SRC_LVL_LOW     (0 << 5)        /* Are these right? docs don't say which is high/low     */
103#define AIC_SMR_SRC_EDGE_LOW    (1 << 5)
104#define AIC_SMR_SRC_LVL_HI      (2 << 5)
105#define AIC_SMR_SRC_EDGE_HI     (3 << 5)
106
107/**************************************************************************/
108/* Debug Unit                                                             */
109/**************************************************************************/
110#define DBGU_BASE               0xFFFFF200
111#define DBGU_REG(_x_)   *(vulong *)(DBGU_BASE + _x_)
112
113/* Register Offsets */
114#define DBGU_CR                 0x00    /* Control Register */
115#define DBGU_MR                 0x04    /* Mode Register */
116#define DBGU_IER                0x08    /* Interrupt Enable Register */
117#define DBGU_IDR                0x0C    /* Interrupt Disable Register */
118#define DBGU_IMR                0x10    /* Interrupt Mask Register */
119#define DBGU_CSR                0x14    /* Channel Status Register */
120#define DBGU_RHR                0x18    /* Receiver Holding Register */
121#define DBGU_THR                0x1C    /* Transmitter Holding Register */
122#define DBGU_BRGR               0x20    /* Baud Rate Generator Register */
123#define DBGU_C1R                0x40    /* Chip ID1 Register */
124#define DBGU_C2R                0x44    /* Chip ID2 Register */
125#define DBGU_FNTR               0x48    /* Force NTRST Register */
126
127/**************************************************************************/
128/* USART 0-3                                                              */
129/**************************************************************************/
130#define USART0_BASE             0xFFFC0000
131#define USART1_BASE             0xFFFC4000
132#define USART2_BASE             0xFFFC8000
133#define USART3_BASE             0xFFFCC000
134/*
135 *  WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!!
136 *  Manual revision: Rev. 1768H-ATARM–16-Jun-09
137 *  USART3_BASE is NOT 0xFFECC000
138 */
139
140/****************/
141/* System Timer */
142/****************/
143#define ST_BASE                 0xFFFFFD00
144#define ST_REG(_x_)             *(vulong *)(ST_BASE + _x_)
145
146/* Register Offsets */
147#define ST_CR                   0x00    /* Control Register */
148#define ST_PIMR                 0x04    /* Period Interval Mode Register */
149#define ST_WDMR                 0x08    /* Watchdog Mode Register */
150#define ST_RTMR                 0x0C    /* Real-time Mode Register */
151#define ST_SR                   0x10    /* Status Register */
152#define ST_IER                  0x14    /* Interrupt Enable Register */
153#define ST_IDR                  0x18    /* Interrupt Disable Register */
154#define ST_IMR                  0x1C    /* Interrupt Mask Register */
155#define ST_RTAR                 0x20    /* Real-time Alarm Register */
156#define ST_CRTR                 0x24    /* Current Real-time Register */
157
158/* Bit Defines */
159/* ST_CR - Control Register */
160#define ST_CR_WDRST                     BIT0    /* write 1 to reload WD counter  */
161
162/* ST_PIMR - Period Interval Mode Register */
163#define ST_PIMR_PIV_MASK        0x0000ffff
164
165/* ST_WDMR - Watchdog Mode Register */
166#define ST_WDMR_EXTEN           BIT17   /* WDOVF is not implemented on AT91RM9200 */
167#define ST_WDMR_RSTEN           BIT16   /* 1 = reset the AT91RM9200 when WD overflows */
168#define ST_WDMR_WDV_MASK        0x0000ffff      /* WD counter is in the lower 16-bits */
169
170/* ST_RTMR - Real-time Mode Register */
171#define ST_RTMR_RTPRES_MASK     0x0000ffff      /* Real-Time Prescaler */
172
173/* ST_SR - Status Register - Read Only */
174/* ST_IER - Interrupt Enable Register - Write Only */
175/* ST_IDR - Interrupt Disable Register - Write Only */
176/* ST_IMR - Interrupt Mask Register - Read Only */
177#define ST_SR_ALMS                      BIT3
178#define ST_SR_RTTINC            BIT2
179#define ST_SR_WDOVF                     BIT1
180#define ST_SR_PITS                      BIT0
181
182/* ST_RTAR - Real-time Alarm Register */
183#define ST_RTAR_ALMV_MASK       0x000fffff
184
185/* ST_CRTR - Current Real-time Register */
186#define ST_CRTR_CRTV_MASK       0x000fffff
187
188
189/**************************************************************************
190 * Peripheral Data Control (DMA)
191 * Note that each of the following peripherals has it's own
192 * set of these registers starting at offset 0x100 from it's
193 * base address: DBGU, SPI, USART and SSC
194 * To access the DMA for a peripheral, use the macro for that
195 * peripheral but with these register offsets
196 **************************************************************************/
197/* Register Offsets */
198#define PDC_RPR         0x100   /* Receive Pointer Register */
199#define PDC_RCR         0x104   /* Receive Counter Register */
200#define PDC_TPR         0x108   /* Transmit Pointer Register */
201#define PDC_TCR         0x10c   /* Transmit Counter Register */
202#define PDC_RNPR        0x110   /* Receive Next Pointer Register */
203#define PDC_RNCR        0x114   /* Receive Next Counter Register */
204#define PDC_TNPR        0x118   /* Transmit Next Pointer Register */
205#define PDC_TNCR        0x11c   /* Transmit Next Counter Register */
206#define PDC_PTCR        0x120   /* PDC Transfer Control Register */
207#define PDC_PTSR        0x124   /* PDC Transfer Status Register */
208
209/**************************************************************************
210 * Parallel I/O Unit
211 * There are four PIO blocks - A, B, C and D.  They all have the
212 * same register set, but different base addresses
213 **************************************************************************/
214/* Port A */
215#define PIOA_BASE               0xFFFFF400
216#define PIOA_REG(_x_)   *(vulong *)(PIOA_BASE + _x_)
217
218/* Port B */
219#define PIOB_BASE               0xFFFFF600
220#define PIOB_REG(_x_)   *(vulong *)(PIOB_BASE + _x_)
221
222/* Port C */
223#define PIOC_BASE               0xFFFFF800
224#define PIOC_REG(_x_)   *(vulong *)(PIOC_BASE + _x_)
225
226/* Port D */
227#define PIOD_BASE               0xFFFFFA00
228#define PIOD_REG(_x_)   *(vulong *)(PIOD_BASE + _x_)
229
230/**************************************************************************
231 * Power Management and Clock Control
232 *************************************************************************/
233#define PMC_BASE                0xFFFFFC00
234#define PMC_REG(_x_)    *(vulong *)(PMC_BASE + _x_)
235
236/**************************************************************************
237 * MAC Unit
238 *************************************************************************/
239#define EMAC_BASE               0xFFFBC000
240#define EMAC_REG(_x_)   *(vulong *)(EMAC_BASE + _x_)
241
242/**************************************************************************
243 * Timer/Counter Unit
244 **************************************************************************/
245#define TC_BASE         0xFFFA0000
246#define TC_REG(_x_)     *(vulong *)(TC_BASE + 0x00 + _x_)
247#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
248#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_)
249#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_)
250
251/* Offsets from TC_TC?_REG  */
252#define TC_CCR      0x00    /* Channel Control Register  */
253#define TC_CMR      0x04    /* Channel Mode Register  */
254#define TC_CV       0x10    /* Counter Value  */
255#define TC_RA       0x14    /* Register A  */
256#define TC_RB       0x18    /* Register B  */
257#define TC_RC       0x1C    /* Register C  */
258#define TC_SR       0x20    /* Status Register  */
259#define TC_IER      0x24    /* Interrupt Enable Register  */
260#define TC_IDR      0x28    /* Interrupt Disable Register  */
261#define TC_IMR      0x2C    /* Interrupt Mask Register  */
262
263/* Offsets from TC_BASE */
264#define TC_BCR      0xc0    /* Channel Control Register  */
265#define TC_BMR      0xc4    /* Channel Control Register  */
266
267/* Block control register */
268#define TC_BCR_SYNC    BIT1       /* Set to syncronize channels */
269
270/* Block mode register */
271#define TC_BMR_TC0(_x_)    ((_x_ & 0x3) << 0)   /* TC0 clock source */
272#define TC_BMR_TC1(_x_)    ((_x_ & 0x3) << 2)   /* TC1 clock source */
273#define TC_BMR_TC2(_x_)    ((_x_ & 0x3) << 4)   /* TC2 clock source */
274
275/* Channel Control register */
276#define TC_CCR_CLKEN     BIT0       /* Enable clock */
277#define TC_CCR_CLKDIS    BIT1       /* Disable clock */
278#define TC_CCR_SWTRG     BIT2       /* Software trigger command */
279
280/* Channel mode register */
281#define TC_CMR_TCCLKS(_x_)   ((_x_ & 0x7) << 0)  /* Clock source */
282#define TC_CMR_CLKI          BIT3                /* Clock invert */
283#define TC_BURST(_x_)        ((_x_ & 0x3 << 4)   /* Burst signal selection */
284#define TC_WAVE              BIT15               /* 0 for catpure, 1 for wave */
285
286/* Channel mode register - capture mode (TC_WAVE = 0) */
287#define TC_CMR_LDBSTOP       BIT6                /* Set to stop clock when RB loads */
288#define TC_CMR_LDBDIS        BIT7                /* Set to disable clock when RB loads */
289#define TC_CMR_ETRGEDG(_x_)  ((_x_ & 0x3) << 8)  /* Select edge triggering mode */
290#define TC_CMR_ABETRG        BIT10               /* Select ext trigger source */
291#define TC_CMR_CPCTRG        BIT14               /* RC Compare trigger enable */
292#define TC_CMR_LDRA(_x_)     ((_x_ & 0x3) << 16) /* RA loading selection */
293#define TC_CMR_LDRB(_x_)     ((_x_ & 0x3) << 18) /* RB loading selection */
294
295/* Channel mode register - wave mode (TC_WAVE = 1) */
296#define TC_CMR_CPCSTOP       BIT6                 /* Clock stopped w/ RC compare */
297#define TC_CMR_CPCDIS        BIT7                 /* Clock disabled w/ RC compare */
298#define TC_CMR_EEVTEDG(_x_)  ((_x_ & 0x3) << 8)   /* Ext event edge selection */
299#define TC_CMR_EEVT(_x_)     ((_x_ & 0x3) << 10)  /* Ext event selection */
300#define TC_CMR_ENETRG        BIT12                /* Ext event trigger enable */
301#define TC_CMR_WAVESEL(_x_)  ((_x_ & 0x3) << 13)  /* Waveform selection */
302#define TC_CMR_ACPA(_x_)     ((_x_ & 0x3) << 16)  /* RA compare effect on TIOA */
303#define TC_CMR_ACPC(_x_)     ((_x_ & 0x3) << 18)  /* RC compare effect on TIOA */
304#define TC_CMR_AEEVT(_x_)    ((_x_ & 0x3) << 20)  /* Ext event effect on TIOA */
305#define TC_CMR_ASWTRG(_x_)   ((_x_ & 0x3) << 22)  /* SW trigger effect on TIOA */
306#define TC_CMR_BCPB(_x_)     ((_x_ & 0x3) << 24)  /* RB compare effect on TIOB */
307#define TC_CMR_BCPC(_x_)     ((_x_ & 0x3) << 26)  /* RC compare effect on TIOB */
308#define TC_CMR_BEEVT(_x_)    ((_x_ & 0x3) << 28)  /* Ext event effect on TIOB */
309#define TC_CMR_BSWTRG(_x_)   ((_x_ & 0x3) << 30)  /* SW trigger effect on TIOB */
310
311/* Counter value */
312#define TC_CV_MASK            0xffff              /* Timer counter mask */
313
314/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */
315#define TC_SR_COVFS     BIT0        /* Counter overflow status */
316#define TC_SR_LOVRS     BIT1        /* Load overrun status */
317#define TC_SR_CPAS      BIT2        /* RA compare status */
318#define TC_SR_CPBS      BIT3        /* RB compare status */
319#define TC_SR_CPCS      BIT4        /* RC compare status */
320#define TC_SR_LDRAS     BIT5        /* RA loading status */
321#define TC_SR_LDRBS     BIT6        /* RB loading  status */
322#define TC_SR_ETRGS     BIT7        /* External trigger status */
323#define TC_SR_CLKSTA    BIT16       /* Clock enabling status */
324#define TC_SR_MTIOA     BIT17       /* TIOA Mirror */
325#define TC_SR_MTIOB     BIT18       /* TIOB Mirror */
326
327/***************************************************************************
328 * External Bus Interface Unit
329 **************************************************************************/
330#define EBI_BASE                        0xFFFFFF60
331#define EBI_REG(_x_)            *(vulong *)(EBI_BASE + _x_)
332
333/***************************************************************************
334 * Static Memory Interface Unit
335 ***************************************************************************/
336#define SMC_REG(_x_)            *(vulong *)(EBI_BASE + 0x10 + _x_)
337
338/**************************************************************************
339 * SDRAM Memory Interface Unit
340 **************************************************************************/
341#define SDRC_REG(_x_)           *(vulong *)(EBI_BASE + 0x30 + _x_)
342
343#endif /* __AT91RM9200_H__ */
344
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