source: rtems/bsps/arm/csb336/start/start.S @ ff081aee

Last change on this file since ff081aee was ff081aee, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 6, 2018 at 3:58:02 PM

score: Rename interrupt stack symbols

Rename

  • _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  • _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  • _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>. The new names are considerable
shorter and in the right namespace.

Update #3459.

  • Property mode set to 100644
File size: 4.0 KB
Line 
1/*
2 * Cogent CSB336 startup code
3 *
4 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#include <rtems/asm.h>
12#include <rtems/score/cpu.h>
13
14.section .bsp_start_text,"ax"
15         .code 32
16_start_jump_at_origin:
17        ldr     pc, _start_address
18_start_address:
19        .word   _start
20
21.text
22.globl  _start
23_start:
24        /*
25         * Since I don't plan to return to the bootloader,
26         * I don't have to save the registers.
27         */
28
29        /* Set end of interrupt stack area */
30        ldr     r7, =_ISR_Stack_area_end
31
32        /* Enter FIQ mode and set up the FIQ stack pointer */
33        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
34        msr     cpsr, r0
35        ldr     r1, =bsp_stack_fiq_size
36        mov     sp, r7
37        sub     r7, r7, r1
38
39        /* Enter ABT mode and set up the ABT stack pointer */
40        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
41        msr     cpsr, r0
42        ldr     r1, =bsp_stack_abt_size
43        mov     sp, r7
44        sub     r7, r7, r1
45
46        /* Enter UND mode and set up the UND stack pointer */
47        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
48        msr     cpsr, r0
49        ldr     r1, =bsp_stack_und_size
50        mov     sp, r7
51        sub     r7, r7, r1
52
53        /* Enter IRQ mode and set up the IRQ stack pointer */
54        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
55        msr     cpsr, r0
56        mov     sp, r7
57
58        /*
59         * Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
60         * (interrupts are disabled).
61         */
62        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
63        msr     cpsr, r0
64        mov     sp, r7
65
66        /* Stay in SVC mode */
67
68        /* zero the bss */
69        ldr     r1, =bsp_section_bss_end
70        ldr     r0, =bsp_section_bss_begin
71
72_bss_init:
73        mov     r2, #0
74        cmp     r0, r1
75        strlot  r2, [r0], #4
76        blo     _bss_init        /* loop while r0 < r1 */
77
78        /*
79         * Initialize the MMU. After we return, the MMU is enabled,
80         * and memory may be remapped. I hope we don't remap this
81         * memory away.
82         */
83        ldr     r0, =mem_map
84        bl      mmu_init
85
86        /*
87         * Initialize the exception vectors. This includes the
88         * exceptions vectors (0x00000000-0x0000001c), and the
89         * pointers to the exception handlers (0x00000020-0x0000003c).
90         */
91        mov     r0, #0
92        adr     r1, vector_block
93        ldmia   r1!, {r2-r9}
94        stmia   r0!, {r2-r9}
95        ldmia   r1!, {r2-r9}
96        stmia   r0!, {r2-r9}
97
98        /* Now we are prepared to start the BSP's C code */
99        mov     r0, #0
100        bl      boot_card
101
102        /*
103         * Theoretically, we could return to what started us up,
104         * but we'd have to have saved the registers and stacks.
105         * Instead, we'll just reset.
106         */
107        bl      bsp_reset
108
109        /* We shouldn't get here. If we do, hang */
110_hang:  b       _hang
111
112
113/*
114 * This is the exception vector table and the pointers to
115 * the functions that handle the exceptions. It's a total
116 * of 16 words (64 bytes)
117 */
118vector_block:
119        ldr    pc, handler_addr_reset
120        ldr    pc, handler_addr_undef
121        ldr    pc, handler_addr_swi
122        ldr    pc, handler_addr_prefetch
123        ldr    pc, handler_addr_abort
124        nop
125        ldr    pc, handler_addr_irq
126        ldr    pc, handler_addr_fiq
127
128handler_addr_reset:
129        .word  bsp_reset
130
131handler_addr_undef:
132        .word  _ARMV4_Exception_undef_default
133
134handler_addr_swi:
135        .word  _ARMV4_Exception_swi_default
136
137handler_addr_prefetch:
138        .word  _ARMV4_Exception_pref_abort_default
139
140handler_addr_abort:
141        .word  _ARMV4_Exception_data_abort_default
142
143handler_addr_reserved:
144        .word  _ARMV4_Exception_reserved_default
145
146handler_addr_irq:
147        .word  _ARMV4_Exception_interrupt
148
149handler_addr_fiq:
150        .word  _ARMV4_Exception_fiq_default
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