[1a3d1f3e] | 1 | /* |
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| 2 | * Cogent CSB336 startup code |
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| 3 | * |
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| 4 | * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> |
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[32b8506] | 5 | * |
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[1a3d1f3e] | 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[c499856] | 8 | * http://www.rtems.org/license/LICENSE. |
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[1a3d1f3e] | 9 | */ |
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| 10 | |
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[8d992be9] | 11 | #include <bsp/linker-symbols.h> |
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| 12 | |
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[1a3d1f3e] | 13 | /* Some standard definitions...*/ |
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| 14 | .equ PSR_MODE_USR, 0x10 |
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| 15 | .equ PSR_MODE_FIQ, 0x11 |
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| 16 | .equ PSR_MODE_IRQ, 0x12 |
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| 17 | .equ PSR_MODE_SVC, 0x13 |
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| 18 | .equ PSR_MODE_ABT, 0x17 |
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| 19 | .equ PSR_MODE_UNDEF, 0x1B |
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| 20 | .equ PSR_MODE_SYS, 0x1F |
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| 21 | |
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| 22 | .equ PSR_I, 0x80 |
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| 23 | .equ PSR_F, 0x40 |
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| 24 | .equ PSR_T, 0x20 |
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| 25 | |
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[2a2f559] | 26 | .section .bsp_start_text,"ax" |
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| 27 | .code 32 |
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| 28 | _start_jump_at_origin: |
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| 29 | ldr pc, _start_address |
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| 30 | _start_address: |
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| 31 | .word _start |
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| 32 | |
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[1a3d1f3e] | 33 | .text |
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| 34 | .globl _start |
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| 35 | _start: |
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[32b8506] | 36 | /* |
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[1a3d1f3e] | 37 | * Since I don't plan to return to the bootloader, |
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| 38 | * I don't have to save the registers. |
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| 39 | * |
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[32b8506] | 40 | * I'll just set the CPSR for SVC mode, interrupts |
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[1a3d1f3e] | 41 | * off, and ARM instructions. |
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| 42 | */ |
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| 43 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) |
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| 44 | msr cpsr, r0 |
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[32b8506] | 45 | |
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[1a3d1f3e] | 46 | /* zero the bss */ |
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[8d992be9] | 47 | ldr r1, =bsp_section_bss_end |
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| 48 | ldr r0, =bsp_section_bss_begin |
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[1a3d1f3e] | 49 | |
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[32b8506] | 50 | _bss_init: |
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[1a3d1f3e] | 51 | mov r2, #0 |
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| 52 | cmp r0, r1 |
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| 53 | strlot r2, [r0], #4 |
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[32b8506] | 54 | blo _bss_init /* loop while r0 < r1 */ |
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[1a3d1f3e] | 55 | |
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| 56 | |
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| 57 | /* --- Initialize stack pointer registers */ |
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| 58 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 59 | mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ |
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| 60 | msr cpsr, r0 |
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[8d992be9] | 61 | ldr r1, =bsp_stack_irq_size |
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| 62 | ldr sp, =bsp_stack_irq_begin |
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[1a3d1f3e] | 63 | add sp, sp, r1 |
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| 64 | |
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| 65 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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| 66 | mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ |
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| 67 | msr cpsr, r0 |
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[8d992be9] | 68 | ldr r1, =bsp_stack_fiq_size |
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| 69 | ldr sp, =bsp_stack_fiq_begin |
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[1a3d1f3e] | 70 | add sp, sp, r1 |
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| 71 | |
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| 72 | /* Enter ABT mode and set up the ABT stack pointer */ |
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| 73 | mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ |
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| 74 | msr cpsr, r0 |
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[8d992be9] | 75 | ldr r1, =bsp_stack_abt_size |
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| 76 | ldr sp, =bsp_stack_abt_begin |
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[1a3d1f3e] | 77 | add sp, sp, r1 |
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[32b8506] | 78 | |
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[0eede05] | 79 | /* Enter UNDEF mode and set up the UNDEF stack pointer */ |
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| 80 | mov r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F) /* No interrupts */ |
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| 81 | msr cpsr, r0 |
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[8d992be9] | 82 | ldr r1, =bsp_stack_und_size |
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| 83 | ldr sp, =bsp_stack_und_begin |
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[0eede05] | 84 | add sp, sp, r1 |
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[32b8506] | 85 | |
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[1a3d1f3e] | 86 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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| 87 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ |
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| 88 | msr cpsr, r0 |
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[8d992be9] | 89 | ldr r1, =bsp_stack_svc_size |
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| 90 | ldr sp, =bsp_stack_svc_begin |
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[1a3d1f3e] | 91 | add sp, sp, r1 |
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[32b8506] | 92 | sub sp, sp, #0x64 |
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[1a3d1f3e] | 93 | |
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[32b8506] | 94 | /* |
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[1a3d1f3e] | 95 | * Initialize the MMU. After we return, the MMU is enabled, |
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| 96 | * and memory may be remapped. I hope we don't remap this |
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| 97 | * memory away. |
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| 98 | */ |
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| 99 | ldr r0, =mem_map |
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[32b8506] | 100 | bl mmu_init |
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[1a3d1f3e] | 101 | |
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[32b8506] | 102 | /* |
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[1a3d1f3e] | 103 | * Initialize the exception vectors. This includes the |
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[32b8506] | 104 | * exceptions vectors (0x00000000-0x0000001c), and the |
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[1a3d1f3e] | 105 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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| 106 | */ |
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| 107 | mov r0, #0 |
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| 108 | adr r1, vector_block |
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| 109 | ldmia r1!, {r2-r9} |
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| 110 | stmia r0!, {r2-r9} |
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| 111 | ldmia r1!, {r2-r9} |
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| 112 | stmia r0!, {r2-r9} |
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| 113 | |
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| 114 | /* Now we are prepared to start the BSP's C code */ |
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[09d053e8] | 115 | mov r0, #0 |
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[1a3d1f3e] | 116 | bl boot_card |
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| 117 | |
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[32b8506] | 118 | /* |
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[1a3d1f3e] | 119 | * Theoretically, we could return to what started us up, |
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| 120 | * but we'd have to have saved the registers and stacks. |
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| 121 | * Instead, we'll just reset. |
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| 122 | */ |
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| 123 | bl bsp_reset |
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| 124 | |
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| 125 | /* We shouldn't get here. If we do, hang */ |
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| 126 | _hang: b _hang |
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| 127 | |
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[32b8506] | 128 | |
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| 129 | /* |
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[1a3d1f3e] | 130 | * This is the exception vector table and the pointers to |
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| 131 | * the functions that handle the exceptions. It's a total |
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| 132 | * of 16 words (64 bytes) |
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| 133 | */ |
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[32b8506] | 134 | vector_block: |
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[2433a8ab] | 135 | ldr pc, handler_addr_reset |
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| 136 | ldr pc, handler_addr_undef |
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| 137 | ldr pc, handler_addr_swi |
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| 138 | ldr pc, handler_addr_prefetch |
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| 139 | ldr pc, handler_addr_abort |
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[1a3d1f3e] | 140 | nop |
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[2433a8ab] | 141 | ldr pc, handler_addr_irq |
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| 142 | ldr pc, handler_addr_fiq |
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| 143 | |
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| 144 | handler_addr_reset: |
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| 145 | .word bsp_reset |
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| 146 | |
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| 147 | handler_addr_undef: |
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| 148 | .word _ARMV4_Exception_undef_default |
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| 149 | |
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| 150 | handler_addr_swi: |
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| 151 | .word _ARMV4_Exception_swi_default |
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| 152 | |
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| 153 | handler_addr_prefetch: |
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| 154 | .word _ARMV4_Exception_pref_abort_default |
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| 155 | |
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| 156 | handler_addr_abort: |
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| 157 | .word _ARMV4_Exception_data_abort_default |
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| 158 | |
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| 159 | handler_addr_reserved: |
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| 160 | .word _ARMV4_Exception_reserved_default |
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| 161 | |
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| 162 | handler_addr_irq: |
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| 163 | .word _ARMV4_Exception_interrupt |
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| 164 | |
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| 165 | handler_addr_fiq: |
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| 166 | .word _ARMV4_Exception_fiq_default |
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