source: rtems/bsps/arm/csb336/start/bspstart.c @ a3fe23c

5
Last change on this file since a3fe23c was 9964895, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 20, 2018 at 8:35:35 AM

bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * Cogent CSB336 - MC9328MXL SBC startup code
3 */
4
5/*
6 * Copyright (c) 2004 by Cogent Computer Systems
7 * Written by Jay Monkman <jtm@lopingdog.com>
8 *
9 * The license and distribution terms for this file may be
10 * found in the file LICENSE in this distribution or at
11 * http://www.rtems.org/license/LICENSE.
12 */
13
14#include <bsp.h>
15#include <bsp/irq-generic.h>
16#include <rtems/bspIo.h>
17#include <mc9328mxl.h>
18#include <libcpu/mmu.h>
19
20/*
21 * bsp_start_default - BSP initialization function
22 *
23 *   This function is called before RTEMS is initialized and used
24 *   adjust the kernel's configuration.
25 *
26 *   This function also configures the CPU's memory protection unit.
27 *
28 * RESTRICTIONS/LIMITATIONS:
29 *   Since RTEMS is not configured, no RTEMS functions can be called.
30 *
31 */
32static void bsp_start_default( void )
33{
34  int i;
35
36  /* Set the MCU prescaler to divide by 1 */
37  MC9328MXL_PLL_CSCR &= ~MC9328MXL_PLL_CSCR_PRESC;
38
39  /* Enable the MCU PLL */
40  MC9328MXL_PLL_CSCR |= MC9328MXL_PLL_CSCR_MPEN;
41
42  /* Delay to allow time for PLL to get going */
43  for (i = 0; i < 100; i++) {
44    __asm__ volatile ("nop\n");
45  }
46
47  /* Set the CPU to asynchrous clock mode, so it uses its fastest clock */
48  mmu_set_cpu_async_mode();
49
50  /* disable interrupts */
51  MC9328MXL_AITC_INTENABLEL = 0;
52  MC9328MXL_AITC_INTENABLEH = 0;
53
54  /* Set interrupt priority to -1 (allow all priorities) */
55  MC9328MXL_AITC_NIMASK = 0x1f;
56
57  /*
58   * Init rtems interrupt management
59   */
60  bsp_interrupt_initialize();
61} /* bsp_start */
62
63/* Calcuate the frequency for perclk1 */
64int get_perclk1_freq(void)
65{
66  unsigned int fin;
67  unsigned int fpll;
68  unsigned int pd;
69  unsigned int mfd;
70  unsigned int mfi;
71  unsigned int mfn;
72  uint32_t reg;
73  int perclk1;
74
75  if (MC9328MXL_PLL_CSCR & MC9328MXL_PLL_CSCR_SYSSEL) {
76    /* Use external oscillator */
77    fin = BSP_OSC_FREQ;
78  } else {
79    /* Use scaled xtal freq */
80    fin = BSP_XTAL_FREQ * 512;
81  }
82
83  /* calculate the output of the system PLL */
84  reg = MC9328MXL_PLL_SPCTL0;
85  pd = ((reg & MC9328MXL_PLL_SPCTL_PD_MASK) >>
86        MC9328MXL_PLL_SPCTL_PD_SHIFT);
87  mfd = ((reg & MC9328MXL_PLL_SPCTL_MFD_MASK) >>
88         MC9328MXL_PLL_SPCTL_MFD_SHIFT);
89  mfi = ((reg & MC9328MXL_PLL_SPCTL_MFI_MASK) >>
90         MC9328MXL_PLL_SPCTL_MFI_SHIFT);
91  mfn = ((reg & MC9328MXL_PLL_SPCTL_MFN_MASK) >>
92         MC9328MXL_PLL_SPCTL_MFN_SHIFT);
93
94#if 0
95  printk("fin = %d\n", fin);
96  printk("pd = %d\n", pd);
97  printk("mfd = %d\n", mfd);
98  printk("mfi = %d\n", mfi);
99  printk("mfn = %d\n", mfn);
100  printk("rounded (fin * mfi) / (pd + 1) = %d\n", (fin * mfi) / (pd + 1));
101  printk("rounded (fin * mfn) / ((pd + 1) * (mfd + 1)) = %d\n",
102         ((long long)fin * mfn) / ((pd + 1) * (mfd + 1)));
103#endif
104
105  fpll = 2 * ( ((fin * mfi  + (pd + 1) / 2) / (pd + 1)) +
106               (((long long)fin * mfn + ((pd + 1) * (mfd + 1)) / 2) /
107               ((pd + 1) * (mfd + 1))) );
108
109  /* calculate the output of the PERCLK1 divider */
110  reg = MC9328MXL_PLL_PCDR;
111  perclk1 = fpll / (1 + ((reg & MC9328MXL_PLL_PCDR_PCLK1_MASK) >>
112                         MC9328MXL_PLL_PCDR_PCLK1_SHIFT));
113
114  return perclk1;
115}
116
117/*
118 *  By making this a weak alias for bsp_start_default, a brave soul
119 *  can override the actual bsp_start routine used.
120 */
121void bsp_start (void) __attribute__ ((weak, alias("bsp_start_default")));
122
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