1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_csb336 |
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5 | * |
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6 | * @brief SMSC LAN91C11x ethernet devices definitions. |
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7 | */ |
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8 | |
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9 | /** |
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10 | * @defgroup arm_csb336_lan91c11x SMSC LAN91C11x |
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11 | * |
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12 | * @ingroup arm_csb336 |
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13 | * |
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14 | * @brief SMSC LAN91C11x ethernet devices definitions. |
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15 | */ |
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16 | |
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17 | /* |
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18 | * Header file for SMSC LAN91C11x ethernet devices |
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19 | * |
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20 | * Copyright (c) 2004 by Cogent Computer Systems |
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21 | * Written by Jay Monkman <jtm@lopingdog.com> |
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22 | * |
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23 | * The license and distribution terms for this file may be |
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24 | * found in the file LICENSE in this distribution or at |
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25 | * http://www.rtems.org/license/LICENSE. |
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26 | */ |
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27 | #ifndef __LAN91C11X_H__ |
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28 | #define __LAN91C11X_H__ |
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29 | |
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30 | #include <rtems.h> |
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31 | #include <bsp.h> |
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32 | |
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33 | uint16_t lan91c11x_read_reg(int); |
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34 | void lan91c11x_write_reg(int, uint16_t); |
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35 | uint16_t lan91c11x_read_reg_fast(int); |
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36 | void lan91c11x_write_reg_fast(int, uint16_t); |
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37 | void lan91c11x_write_phy_reg(int , uint16_t); |
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38 | uint16_t lan91c11x_read_phy_reg(int); |
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39 | void lan91c11x_unlock(void); |
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40 | void lan91c11x_lock(void); |
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41 | |
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42 | #define LAN91C11X_BASE_ADDR 0x12000000 |
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43 | |
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44 | #define LAN91C11X_REG(_b_, _r_) ((((_b_) & 0xf) << 4) | ((_r_) & 0xf)) |
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45 | |
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46 | |
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47 | #define LAN91C11X_TCR (LAN91C11X_REG(0, 0x0)) |
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48 | #define LAN91C11X_EPHSTAT (LAN91C11X_REG(0, 0x2)) |
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49 | #define LAN91C11X_RCR (LAN91C11X_REG(0, 0x4)) |
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50 | #define LAN91C11X_CNTR (LAN91C11X_REG(0, 0x6)) |
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51 | #define LAN91C11X_MIR (LAN91C11X_REG(0, 0x8)) |
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52 | #define LAN91C11X_RPCR (LAN91C11X_REG(0, 0xa)) |
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53 | #define LAN91C11X_BANK (LAN91C11X_REG(0, 0xe)) |
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54 | #define LAN91C11X_CONFIG (LAN91C11X_REG(1, 0x0)) |
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55 | #define LAN91C11X_BASE (LAN91C11X_REG(1, 0x2)) |
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56 | #define LAN91C11X_IA0 (LAN91C11X_REG(1, 0x4)) |
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57 | #define LAN91C11X_IA2 (LAN91C11X_REG(1, 0x6)) |
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58 | #define LAN91C11X_IA4 (LAN91C11X_REG(1, 0x8)) |
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59 | #define LAN91C11X_GNRL (LAN91C11X_REG(1, 0xa)) |
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60 | #define LAN91C11X_CTRL (LAN91C11X_REG(1, 0xc)) |
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61 | #define LAN91C11X_MMUCMD (LAN91C11X_REG(2, 0x0)) |
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62 | #define LAN91C11X_PNR (LAN91C11X_REG(2, 0x2)) |
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63 | #define LAN91C11X_FIFO (LAN91C11X_REG(2, 0x4)) |
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64 | #define LAN91C11X_PTR (LAN91C11X_REG(2, 0x6)) |
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65 | #define LAN91C11X_DATA (LAN91C11X_REG(2, 0x8)) |
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66 | #define LAN91C11X_INT (LAN91C11X_REG(2, 0xc)) |
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67 | #define LAN91C11X_MT0 (LAN91C11X_REG(3, 0x0)) |
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68 | #define LAN91C11X_MT2 (LAN91C11X_REG(3, 0x2)) |
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69 | #define LAN91C11X_MT4 (LAN91C11X_REG(3, 0x4)) |
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70 | #define LAN91C11X_MT6 (LAN91C11X_REG(3, 0x6)) |
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71 | #define LAN91C11X_MGMT (LAN91C11X_REG(3, 0x8)) |
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72 | #define LAN91C11X_REV (LAN91C11X_REG(3, 0xa)) |
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73 | #define LAN91C11X_ERCV (LAN91C11X_REG(3, 0xc)) |
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74 | |
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75 | |
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76 | #define LAN91C11X_TCR_TXENA (bit(0)) |
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77 | #define LAN91C11X_TCR_LOOP (bit(1)) |
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78 | #define LAN91C11X_TCR_FORCOL (bit(2)) |
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79 | #define LAN91C11X_TCR_PADEN (bit(7)) |
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80 | #define LAN91C11X_TCR_NOCRC (bit(8)) |
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81 | #define LAN91C11X_TCR_MONCSN (bit(10)) |
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82 | #define LAN91C11X_TCR_FDUPLX (bit(11)) |
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83 | #define LAN91C11X_TCR_STPSQET (bit(12)) |
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84 | #define LAN91C11X_TCR_EPHLOOP (bit(13)) |
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85 | #define LAN91C11X_TCR_SWFDUP (bit(15)) |
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86 | |
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87 | #define LAN91C11X_EPHSTAT_TXSUC (bit(0)) |
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88 | #define LAN91C11X_EPHSTAT_SNGLCOL (bit(1)) |
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89 | #define LAN91C11X_EPHSTAT_MULCOL (bit(2)) |
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90 | #define LAN91C11X_EPHSTAT_LTXMUL (bit(3)) |
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91 | #define LAN91C11X_EPHSTAT_16COL (bit(4)) |
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92 | #define LAN91C11X_EPHSTAT_SQET (bit(5)) |
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93 | #define LAN91C11X_EPHSTAT_LTXBRD (bit(6)) |
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94 | #define LAN91C11X_EPHSTAT_TXDFR (bit(7)) |
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95 | #define LAN91C11X_EPHSTAT_LATCOL (bit(9)) |
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96 | #define LAN91C11X_EPHSTAT_LOST (bit(10)) |
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97 | #define LAN91C11X_EPHSTAT_EXCDEF (bit(11)) |
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98 | #define LAN91C11X_EPHSTAT_CTRROL (bit(12)) |
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99 | #define LAN91C11X_EPHSTAT_LINK (bit(14)) |
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100 | #define LAN91C11X_EPHSTAT_TXUNRN (bit(15)) |
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101 | |
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102 | #define LAN91C11X_RCR_RXABT (bit(0)) |
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103 | #define LAN91C11X_RCR_PRMS (bit(1)) |
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104 | #define LAN91C11X_RCR_ALMUL (bit(2)) |
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105 | #define LAN91C11X_RCR_RXEN (bit(8)) |
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106 | #define LAN91C11X_RCR_STRIP (bit(9)) |
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107 | #define LAN91C11X_RCR_ABTENB (bit(13)) |
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108 | #define LAN91C11X_RCR_FILT (bit(14)) |
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109 | #define LAN91C11X_RCR_RST (bit(15)) |
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110 | |
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111 | #define LAN91C11X_RPCR_LS0B (bit(2)) |
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112 | #define LAN91C11X_RPCR_LS1B (bit(3)) |
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113 | #define LAN91C11X_RPCR_LS2B (bit(4)) |
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114 | #define LAN91C11X_RPCR_LS0A (bit(5)) |
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115 | #define LAN91C11X_RPCR_LS1A (bit(6)) |
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116 | #define LAN91C11X_RPCR_LS2A (bit(7)) |
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117 | #define LAN91C11X_RPCR_ANEG (bit(11)) |
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118 | #define LAN91C11X_RPCR_DPLX (bit(12)) |
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119 | #define LAN91C11X_RPCR_SPEED (bit(13)) |
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120 | |
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121 | #define LAN91C11X_CONFIG_EXTPHY (bit(9)) |
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122 | #define LAN91C11X_CONFIG_GPCTRL (bit(10)) |
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123 | #define LAN91C11X_CONFIG_NOWAIT (bit(12)) |
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124 | #define LAN91C11X_CONFIG_PWR (bit(15)) |
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125 | |
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126 | #define LAN91C11X_CTRL_STORE (bit(0)) |
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127 | #define LAN91C11X_CTRL_RELOAD (bit(1)) |
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128 | #define LAN91C11X_CTRL_EEPROM (bit(2)) |
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129 | #define LAN91C11X_CTRL_TEEN (bit(5)) |
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130 | #define LAN91C11X_CTRL_CREN (bit(6)) |
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131 | #define LAN91C11X_CTRL_LEEN (bit(7)) |
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132 | #define LAN91C11X_CTRL_AUTO (bit(11)) |
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133 | #define LAN91C11X_CTRL_RCVBAD (bit(14)) |
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134 | |
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135 | #define LAN91C11X_MMUCMD_BUSY (bit(0)) |
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136 | #define LAN91C11X_MMUCMD_NOOP (0 << 5) |
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137 | #define LAN91C11X_MMUCMD_ALLOCTX (1 << 5) |
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138 | #define LAN91C11X_MMUCMD_RESETMMU (2 << 5) |
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139 | #define LAN91C11X_MMUCMD_REMFRM (3 << 5) |
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140 | #define LAN91C11X_MMUCMD_REMTOP (4 << 5) |
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141 | #define LAN91C11X_MMUCMD_RELEASE (5 << 5) |
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142 | #define LAN91C11X_MMUCMD_ENQUEUE (6 << 5) |
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143 | #define LAN91C11X_MMUCMD_RESETTX (7 << 5) |
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144 | |
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145 | #define LAN91C11X_PTR_MASK (0x7ff) |
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146 | #define LAN91C11X_PTR_NE (bit(11)) |
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147 | #define LAN91C11X_PTR_ETEN (bit(12)) |
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148 | #define LAN91C11X_PTR_READ (bit(13)) |
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149 | #define LAN91C11X_PTR_AUTOINC (bit(14)) |
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150 | #define LAN91C11X_PTR_RCV (bit(15)) |
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151 | |
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152 | #define LAN91C11X_INT_RX (bit(0)) |
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153 | #define LAN91C11X_INT_TX (bit(1)) |
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154 | #define LAN91C11X_INT_TXE (bit(2)) |
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155 | #define LAN91C11X_INT_ALLOC (bit(3)) |
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156 | #define LAN91C11X_INT_RXOV (bit(4)) |
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157 | #define LAN91C11X_INT_EPH (bit(5)) |
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158 | #define LAN91C11X_INT_ERX (bit(6)) |
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159 | #define LAN91C11X_INT_MD (bit(7)) |
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160 | #define LAN91C11X_INT_RXMASK (bit(8)) |
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161 | #define LAN91C11X_INT_TXMASK (bit(9)) |
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162 | #define LAN91C11X_INT_TXEMASK (bit(10)) |
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163 | #define LAN91C11X_INT_ALLOCMASK (bit(11)) |
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164 | #define LAN91C11X_INT_RXOVMASK (bit(12)) |
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165 | #define LAN91C11X_INT_EPHMASK (bit(13)) |
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166 | #define LAN91C11X_INT_ERXMASK (bit(14)) |
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167 | #define LAN91C11X_INT_MDMASK (bit(15)) |
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168 | |
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169 | #define LAN91C11X_MGMT_MDO (bit(0)) |
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170 | #define LAN91C11X_MGMT_MDI (bit(1)) |
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171 | #define LAN91C11X_MGMT_MCLK (bit(2)) |
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172 | #define LAN91C11X_MGMT_MDOE (bit(3)) |
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173 | #define LAN91C11X_MGMT_MSKCRS100 (bit(14)) |
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174 | |
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175 | |
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176 | #define LAN91C11X_PKT_CTRL_CRC (bit(4)) |
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177 | #define LAN91C11X_PKT_CTRL_ODD (bit(5)) |
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178 | |
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179 | |
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180 | /* PHY Registers */ |
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181 | #define PHY_CTRL 0x00 /* PHY Control */ |
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182 | #define PHY_STAT 0x01 /* PHY Status */ |
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183 | #define PHY_ID1 0x02 /* PHY Identifier 1 */ |
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184 | #define PHY_ID2 0x03 /* PHY Identifier 2 */ |
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185 | #define PHY_AD 0x04 /* PHY Auto-negotiate Control */ |
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186 | #define PHY_RMT 0x05 /* PHY Auto-neg Remote End Cap Register */ |
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187 | #define PHY_CFG1 0x10 /* PHY Configuration 1 */ |
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188 | #define PHY_CFG2 0x11 /* PHY Configuration 2 */ |
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189 | #define PHY_INT 0x12 /* Status Output (Interrupt Status) */ |
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190 | #define PHY_MASK 0x13 /* Interrupt Mask */ |
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191 | |
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192 | /* PHY Control Register Bit Defines */ |
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193 | #define PHY_CTRL_RST 0x8000 /* PHY Reset */ |
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194 | #define PHY_CTRL_LPBK 0x4000 /* PHY Loopback */ |
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195 | #define PHY_CTRL_SPEED 0x2000 /* 100Mbps, 0=10Mpbs */ |
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196 | #define PHY_CTRL_ANEGEN 0x1000 /* Enable Auto negotiation */ |
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197 | #define PHY_CTRL_PDN 0x0800 /* PHY Power Down mode */ |
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198 | #define PHY_CTRL_MIIDIS 0x0400 /* MII 4 bit interface disabled */ |
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199 | #define PHY_CTRL_ANEGRST 0x0200 /* Reset Auto negotiate */ |
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200 | #define PHY_CTRL_DPLX 0x0100 /* Full Duplex, 0=Half Duplex */ |
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201 | #define PHY_CTRL_COLTST 0x0080 /* MII Colision Test */ |
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202 | |
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203 | #define PHY_STAT_CAPT4 0x8000 |
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204 | #define PHY_STAT_CAPTXF 0x4000 |
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205 | #define PHY_STAT_CAPTXH 0x2000 |
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206 | #define PHY_STAT_CAPTF 0x1000 |
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207 | #define PHY_STAT_CAPTH 0x0800 |
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208 | #define PHY_STAT_CAPSUPR 0x0040 |
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209 | #define PHY_STAT_ANEGACK 0x0020 |
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210 | #define PHY_STAT_REMFLT 0x0010 |
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211 | #define PHY_STAT_CAPANEG 0x0008 |
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212 | #define PHY_STAT_LINK 0x0004 |
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213 | #define PHY_STAT_JAB 0x0002 |
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214 | #define PHY_STAT_EXREG 0x0001 |
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215 | |
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216 | #define PHY_ADV_NP 0x8000 |
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217 | #define PHY_ADV_ACK 0x4000 |
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218 | #define PHY_ADV_RF 0x2000 |
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219 | #define PHY_ADV_T4 0x0200 |
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220 | #define PHY_ADV_TXFDX 0x0100 |
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221 | #define PHY_ADV_TXHDX 0x0080 |
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222 | #define PHY_ADV_10FDX 0x0040 |
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223 | #define PHY_ADV_10HDX 0x0020 |
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224 | #define PHY_ADV_CSMA 0x0001 |
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225 | |
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226 | |
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227 | |
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228 | |
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229 | #endif /* __LAN91C11X_H__ */ |
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