1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_csb336 |
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5 | * |
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6 | * @brief Helper functions for SMSC LAN91C11x |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Helper functions for SMSC LAN91C11x |
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11 | * |
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12 | * Copyright (c) 2004 by Cogent Computer Systems |
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13 | * Written by Jay Monkman <jtm@lopingdog.com> |
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14 | * |
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15 | * The license and distribution terms for this file may be |
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16 | * found in the file LICENSE in this distribution or at |
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17 | * http://www.rtems.org/license/LICENSE. |
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18 | */ |
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19 | |
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20 | #define __INSIDE_RTEMS_BSD_TCPIP_STACK__ |
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21 | |
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22 | #include <rtems.h> |
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23 | #include "lan91c11x.h" |
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24 | |
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25 | uint16_t lan91c11x_read_reg(int reg) |
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26 | { |
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27 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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28 | uint16_t old_bank; |
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29 | uint16_t val; |
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30 | rtems_interrupt_level level; |
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31 | |
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32 | rtems_interrupt_disable(level); |
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33 | |
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34 | /* save the bank register */ |
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35 | old_bank = ptr[7] & 0x7; |
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36 | |
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37 | /* set the bank register */ |
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38 | ptr[7] = (reg >> 4) & 0x7; |
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39 | |
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40 | val = ptr[((reg & 0xf) >> 1)]; |
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41 | |
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42 | /* restore the bank register */ |
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43 | ptr[7] = old_bank; |
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44 | |
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45 | rtems_interrupt_enable(level); |
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46 | return val; |
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47 | } |
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48 | |
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49 | void lan91c11x_write_reg(int reg, uint16_t value) |
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50 | { |
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51 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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52 | uint16_t old_bank; |
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53 | rtems_interrupt_level level; |
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54 | |
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55 | rtems_interrupt_disable(level); |
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56 | |
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57 | /* save the bank register */ |
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58 | old_bank = ptr[7] & 0x7; |
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59 | |
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60 | /* set the bank register */ |
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61 | ptr[7] = (reg >> 4) & 0x7; |
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62 | |
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63 | ptr[((reg & 0xf) >> 1)] = value; |
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64 | |
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65 | /* restore the bank register */ |
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66 | ptr[7] = old_bank; |
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67 | |
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68 | rtems_interrupt_enable(level); |
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69 | } |
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70 | |
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71 | uint16_t lan91c11x_read_reg_fast(int reg) |
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72 | { |
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73 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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74 | uint16_t val; |
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75 | |
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76 | val = ptr[((reg & 0xf) >> 1)]; |
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77 | |
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78 | return val; |
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79 | } |
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80 | |
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81 | void lan91c11x_write_reg_fast(int reg, uint16_t value) |
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82 | { |
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83 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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84 | |
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85 | ptr[((reg & 0xf) >> 1)] = value; |
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86 | } |
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87 | |
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88 | |
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89 | uint16_t lan91c11x_read_phy_reg(int reg) |
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90 | { |
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91 | int i; |
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92 | uint16_t mask; |
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93 | uint16_t bits[64]; |
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94 | int clk_idx = 0; |
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95 | int input_idx = 0; |
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96 | uint16_t phydata; |
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97 | |
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98 | /* 32 consecutive ones on MDO to establish sync */ |
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99 | for (i = 0; i < 32; ++i) { |
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100 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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101 | } |
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102 | |
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103 | /* Start code <01> */ |
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104 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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105 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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106 | |
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107 | /* Read command <10> */ |
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108 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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109 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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110 | |
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111 | /* Output the PHY address, msb first - Internal PHY is address 0 */ |
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112 | for (i = 0; i < 5; ++i) { |
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113 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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114 | } |
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115 | |
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116 | /* Output the phy register number, msb first */ |
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117 | mask = 0x10; |
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118 | for (i = 0; i < 5; ++i) { |
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119 | if (reg & mask) { |
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120 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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121 | } else { |
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122 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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123 | } |
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124 | |
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125 | |
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126 | /* Shift to next lowest bit */ |
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127 | mask >>= 1; |
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128 | } |
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129 | |
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130 | /* 1 bit time for turnaround */ |
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131 | bits[clk_idx++] = 0; |
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132 | |
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133 | /* Input starts at this bit time */ |
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134 | input_idx = clk_idx; |
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135 | |
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136 | /* Will input 16 bits */ |
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137 | for (i = 0; i < 16; ++i) { |
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138 | bits[clk_idx++] = 0; |
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139 | } |
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140 | |
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141 | /* Final clock bit */ |
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142 | bits[clk_idx++] = 0; |
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143 | |
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144 | /* Turn off all MII Interface bits */ |
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145 | lan91c11x_write_reg(LAN91C11X_MGMT, |
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146 | lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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147 | |
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148 | /* Clock all 64 cycles */ |
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149 | for (i = 0; i < sizeof bits; ++i) { |
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150 | /* Clock Low - output data */ |
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151 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i]); |
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152 | rtems_task_wake_after(1); |
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153 | |
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154 | /* Clock Hi - input data */ |
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155 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i] | LAN91C11X_MGMT_MCLK); |
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156 | rtems_task_wake_after(1); |
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157 | bits[i] |= lan91c11x_read_reg(LAN91C11X_MGMT) & LAN91C11X_MGMT_MDI; |
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158 | } |
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159 | |
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160 | /* Return to idle state */ |
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161 | /* Set clock to low, data to low, and output tristated */ |
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162 | lan91c11x_write_reg(LAN91C11X_MGMT, lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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163 | rtems_task_wake_after(1); |
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164 | |
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165 | /* Recover input data */ |
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166 | phydata = 0; |
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167 | for (i = 0; i < 16; ++i) { |
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168 | phydata <<= 1; |
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169 | |
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170 | if (bits[input_idx++] & LAN91C11X_MGMT_MDI) { |
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171 | phydata |= 0x0001; |
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172 | } |
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173 | } |
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174 | |
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175 | return phydata; |
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176 | } |
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177 | |
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178 | |
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179 | |
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180 | void lan91c11x_write_phy_reg(int reg, uint16_t phydata) |
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181 | { |
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182 | int i; |
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183 | ushort mask; |
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184 | ushort bits[64]; |
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185 | int clk_idx = 0; |
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186 | |
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187 | /* 32 consecutive ones on MDO to establish sync */ |
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188 | for (i = 0; i < 32; ++i) { |
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189 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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190 | } |
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191 | |
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192 | /* Start code <01> */ |
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193 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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194 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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195 | |
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196 | /* Write command <01> */ |
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197 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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198 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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199 | |
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200 | /* Output the PHY address, msb first - Internal PHY is address 0 */ |
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201 | for (i = 0; i < 5; ++i) { |
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202 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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203 | } |
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204 | |
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205 | /* Output the phy register number, msb first */ |
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206 | mask = 0x10; |
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207 | for (i = 0; i < 5; ++i) { |
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208 | if (reg & mask) { |
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209 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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210 | } else { |
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211 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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212 | } |
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213 | |
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214 | /* Shift to next lowest bit */ |
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215 | mask >>= 1; |
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216 | } |
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217 | |
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218 | /* 2 extra bit times for turnaround */ |
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219 | bits[clk_idx++] = 0; |
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220 | bits[clk_idx++] = 0; |
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221 | |
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222 | /* Write out 16 bits of data, msb first */ |
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223 | mask = 0x8000; |
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224 | for (i = 0; i < 16; ++i) { |
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225 | if (phydata & mask) { |
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226 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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227 | } else { |
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228 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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229 | } |
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230 | |
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231 | /* Shift to next lowest bit */ |
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232 | mask >>= 1; |
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233 | } |
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234 | |
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235 | /* Turn off all MII Interface bits */ |
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236 | lan91c11x_write_reg(LAN91C11X_MGMT, |
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237 | lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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238 | |
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239 | /* Clock all 64 cycles */ |
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240 | for (i = 0; i < sizeof bits; ++i) { |
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241 | /* Clock Low - output data */ |
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242 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i]); |
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243 | rtems_task_wake_after(1); |
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244 | |
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245 | /* Clock Hi - input data */ |
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246 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i] | LAN91C11X_MGMT_MCLK); |
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247 | rtems_task_wake_after(1); |
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248 | bits[i] |= lan91c11x_read_reg(LAN91C11X_MGMT) & LAN91C11X_MGMT_MDI; |
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249 | } |
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250 | |
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251 | /* Return to idle state */ |
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252 | /* Set clock to low, data to low, and output tristated */ |
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253 | lan91c11x_write_reg(LAN91C11X_MGMT, |
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254 | lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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255 | rtems_task_wake_after(1); |
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256 | |
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257 | } |
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258 | |
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259 | |
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260 | |
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