1 | Pulse Width Modulation subsystem includes EPWM, ECAP , EQEP. There are |
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2 | different instances available for each one. For PWM there are three |
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3 | different individual EPWM module 0 , 1 and 2. So wherever pwmss word is |
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4 | used that affects whole PWM sub system such as EPWM, ECAP and EQEP. This code |
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5 | has only implementation Non high resolution PWM module. APIs for high |
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6 | resolution PWM has been yet to develop. |
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7 | |
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8 | For Each EPWM instance, has two PWM channels, e.g. EPWM0 has two channel |
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9 | EPWM0A and EPWM0B. If you configure two PWM outputs(e.g. EPWM0A , EPWM0B) |
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10 | in the same device, then they *must* be configured with the same frequency. |
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11 | Changing frequency on one channel (e.g EPWMxA) will automatically change |
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12 | frequency on another channel(e.g. EPWMxB). However, it is possible to set |
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13 | different pulse-width/duty cycle to different channel at a time. So always |
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14 | set the frequency first and then pulse-width/duty cycle. |
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15 | |
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16 | For more you can refer : |
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17 | http://www.ofitselfso.com/BBBCSIO/Source/PWMPortEnum.cs.html |
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18 | |
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19 | Pulse Width Modulation uses the system frequency of Beagle Bone Black. |
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20 | |
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21 | System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT(By Default) |
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22 | SYCLKOUT = 100 MHz |
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23 | |
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24 | Please visit following link to check why SYSCLKDIV = 100MHz: |
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25 | https://groups.google.com/forum/#!topic/beagleboard/Ed2J9Txe_E4 |
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26 | (Refer Technical Reference Manual (TRM) Table 15-41 as well) |
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27 | |
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28 | To generate different frequencies with the help of PWM module , SYSCLKOUT |
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29 | need to be scaled down, which will act as TBCLK and TBCLK will be base clock |
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30 | for the pwm subsystem. |
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31 | |
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32 | TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV) |
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33 | |
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34 | |----------------| |
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35 | | clock | |
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36 | SYSCLKOUT---> | |---> TBCLK |
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37 | | prescale | |
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38 | |----------------| |
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39 | ^ ^ |
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40 | | | |
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41 | TBCTL[CLKDIV]----- ------TBCTL[HSPCLKDIV] |
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42 | |
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43 | |
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44 | CLKDIV and HSPCLKDIV bits are part of the TBCTL register (Refer TRM). |
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45 | CLKDIV - These bits determine part of the time-base clock prescale value. |
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46 | Please use the following values of CLKDIV to scale down sysclk respectively. |
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47 | 0h (R/W) = /1 |
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48 | 1h (R/W) = /2 |
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49 | 2h (R/W) = /4 |
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50 | 3h (R/W) = /8 |
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51 | 4h (R/W) = /16 |
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52 | 5h (R/W) = /32 |
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53 | 6h (R/W) = /64 |
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54 | 7h (R/W) = /128 |
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55 | |
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56 | These bits determine part of the time-base clock prescale value. |
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57 | Please use following value of HSPCLKDIV to scale down sysclk respectively |
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58 | 0h (R/W) = /1 |
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59 | 1h (R/W) = /2 |
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60 | 2h (R/W) = /4 |
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61 | 3h (R/W) = /6 |
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62 | 4h (R/W) = /8 |
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63 | 5h (R/W) = /10 |
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64 | 6h (R/W) = /12 |
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65 | 7h (R/W) = /14 |
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66 | |
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67 | For example, if you set CLKDIV = 3h and HSPCLKDIV= 2h Then |
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68 | SYSCLKOUT will be divided by (1/8)(1/4). It means SYSCLKOUT/32 |
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69 | |
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70 | How to generate frequency ? |
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71 | |
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72 | freq = 1/Period |
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73 | |
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74 | TBPRD register is responsible to generate the frequency. These bits determine |
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75 | the period of the time-base counter. |
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76 | |
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77 | By default TBCLK = SYSCLKOUT = 100 MHz |
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78 | |
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79 | Here by default period is 1/100MHz = 10 nsec |
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80 | |
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81 | Following example shows value to be loaded into TBPRD |
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82 | |
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83 | e.g. TBPRD = 1 = 1 count |
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84 | count x Period = 1 x 1ns = 1ns |
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85 | freq = 1/Period = 1 / 1ns = 100 MHz |
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86 | |
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87 | For duty cycle CMPA and CMPB are the responsible registers. |
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88 | |
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89 | To generate single with 50% Duty cycle & 100MHz freq. |
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90 | |
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91 | CMPA = count x Duty Cycle |
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92 | = TBPRD x Duty Cycle |
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93 | = 1 x 50/100 |
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94 | = 0.2 |
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95 | |
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96 | The value in the active CMPA register is continuously compared to |
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97 | the time-base counter (TBCNT). When the values are equal, the |
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98 | counter-compare module generates a "time-base counter equal to |
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99 | counter compare A" event. This event is sent to the action-qualifier |
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100 | where it is qualified and converted it into one or more actions. |
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101 | These actions can be applied to either the EPWMxA or the |
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102 | EPWMxB output depending on the configuration of the AQCTLA and |
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103 | AQCTLB registers. |
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104 | |
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105 | List of pins for that can be used for different PWM instance : |
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106 | |
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107 | ------------------------------------------------ |
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108 | | EPWM2 | EPWM1 | EPWM0 | |
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109 | ------------------------------------------------ |
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110 | | BBB_P8_13_2B | BBB_P8_34_1B | BBB_P9_21_0B | |
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111 | | BBB_P8_19_2A | BBB_P8_36_1A | BBB_P9_22_0A | |
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112 | | BBB_P8_45_2A | BBB_P9_14_1A | BBB_P9_29_0B | |
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113 | | BBB_P8_46_2B | BBB_P9_16_1B | BBB_P9_31_0A | |
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114 | ------------------------------------------------ |
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115 | BBB_P8_13_2B represents P8 Header , pin number 13 , 2nd PWM instance and B channel. |
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116 | |
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117 | Following sample program can be used to generate 7 Hz frequency. |
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118 | |
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119 | #ifdef HAVE_CONFIG_H |
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120 | #include "config.h" |
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121 | #endif |
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122 | |
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123 | #include <rtems/test.h> |
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124 | #include <bsp.h> |
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125 | #include <bsp/gpio.h> |
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126 | #include <stdio.h> |
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127 | #include <stdlib.h> |
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128 | #include <bsp/bbb-pwm.h> |
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129 | |
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130 | const char rtems_test_name[] = "Testing PWM driver"; |
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131 | rtems_printer rtems_test_printer; |
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132 | |
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133 | static void inline delay_sec(int sec) |
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134 | { |
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135 | rtems_task_wake_after(sec*rtems_clock_get_ticks_per_second()); |
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136 | } |
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137 | |
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138 | rtems_task Init(rtems_task_argument argument); |
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139 | |
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140 | rtems_task Init( |
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141 | rtems_task_argument ignored |
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142 | ) |
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143 | { |
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144 | rtems_test_begin(); |
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145 | printf("Starting PWM Testing"); |
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146 | |
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147 | /*Initialize GPIO pins in BBB*/ |
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148 | rtems_gpio_initialize(); |
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149 | |
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150 | /* Set P9 Header , 21 Pin number , PWM B channel and 0 PWM instance to generate frequency*/ |
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151 | beagle_epwm_pinmux_setup(BBB_P9_21_0B,BBB_PWMSS0); |
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152 | |
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153 | /** Initialize clock for PWM sub system |
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154 | * Turn on time base clock for PWM o instance |
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155 | */ |
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156 | beagle_pwm_init(BBB_PWMSS0); |
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157 | |
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158 | float PWM_HZ = 7.0f ; /* 7 Hz */ |
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159 | float duty_A = 20.0f ; /* 20% Duty cycle for PWM 0_A output */ |
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160 | const float duty_B = 50.0f ; /* 50% Duty cycle for PWM 0_B output*/ |
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161 | |
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162 | /*Note: Always check whether pwmss clocks are enabled or not before configuring PWM*/ |
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163 | bool is_running = beagle_pwmss_is_running(BBB_PWMSS2); |
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164 | |
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165 | if(is_running) { |
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166 | |
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167 | /*To analyse the two different duty cycle Output should be observed at P8_45 and P8_46 pin number */ |
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168 | beagle_pwm_configure(BBB_PWMSS0, PWM_HZ ,duty_A , duty_B); |
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169 | printf("PWM enable for 10s ....\n"); |
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170 | |
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171 | /*Set Up counter and enable pwm module */ |
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172 | beagle_pwm_enable(BBB_PWMSS0); |
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173 | delay_sec(10); |
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174 | |
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175 | /*freeze the counter and disable pwm module*/ |
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176 | beagle_epwm_disable(BBB_PWMSS0); |
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177 | } |
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178 | } |
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179 | |
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180 | /* NOTICE: the clock driver is enabled */ |
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181 | #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER |
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182 | #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER |
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183 | |
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184 | #define CONFIGURE_MAXIMUM_TASKS 1 |
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185 | #define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM |
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186 | |
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187 | #define CONFIGURE_MAXIMUM_SEMAPHORES 1 |
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188 | |
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189 | #define CONFIGURE_RTEMS_INIT_TASKS_TABLE |
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190 | |
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191 | #define CONFIGURE_EXTRA_TASK_STACKS (2 * RTEMS_MINIMUM_STACK_SIZE) |
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192 | |
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193 | #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION |
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194 | |
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195 | #define CONFIGURE_INIT |
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196 | #include <rtems/confdefs.h> |
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197 | |
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