source: rtems/bsps/arm/beagle/include/bsp/soc_AM335x.h @ 26d50bd

Last change on this file since 26d50bd was 26d50bd, checked in by Prashanth S <fishesprashanth@…>, on 10/26/22 at 18:27:35

bsps/arm/beagle/dcan: Added DCAN support
  • Property mode set to 100755
File size: 9.6 KB
Line 
1/** ============================================================================
2 *   \file  soc_AM33XX.h
3 *
4 *   \brief This file contains the peripheral information for AM33XX SoC
5 *
6 *  ============================================================================
7 */
8
9/*
10* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
11*/
12/*
13*  Redistribution and use in source and binary forms, with or without
14*  modification, are permitted provided that the following conditions
15*  are met:
16*
17*    Redistributions of source code must retain the above copyright
18*    notice, this list of conditions and the following disclaimer.
19*
20*    Redistributions in binary form must reproduce the above copyright
21*    notice, this list of conditions and the following disclaimer in the
22*    documentation and/or other materials provided with the
23*    distribution.
24*
25*    Neither the name of Texas Instruments Incorporated nor the names of
26*    its contributors may be used to endorse or promote products derived
27*    from this software without specific prior written permission.
28*
29*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40*
41*/
42
43
44#ifndef _SOC_AM33XX_H_
45#define _SOC_AM33XX_H_
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
51/** Cache Line size in ARM Cortex-A8.                                         */
52#define SOC_CACHELINE_SIZE_MAX               (64)
53
54/** @brief Base address of AINTC memory mapped registers                      */
55#define SOC_AINTC_REGS                       (0x48200000)
56
57/** @brief Base addresses of UART memory mapped registers                     */
58#define SOC_UART_0_REGS                      (0x44E09000)
59#define SOC_UART_1_REGS                      (0x48022000)
60#define SOC_UART_2_REGS                      (0x48024000)
61#define SOC_UART_3_REGS                      (0x481A6000)
62#define SOC_UART_4_REGS                      (0x481A8000)
63#define SOC_UART_5_REGS                      (0x481AA000)
64
65/** @brief Base addresses of USB memory mapped registers                     */
66#define SOC_USB_0_BASE                       (0x47401400)
67#define SOC_USB_1_BASE                       (0x47401C00)
68/** @brief Base addresses of SPI memory mapped registers                      */
69#define SOC_SPI_0_REGS                       (0x48030000)
70#define SOC_SPI_1_REGS                       (0x481A0000)
71
72/** @brief Base addresses of GPIO memory mapped registers                     */
73#define SOC_GPIO_0_REGS                      (0x44E07000)
74#define SOC_GPIO_1_REGS                      (0x4804C000)
75#define SOC_GPIO_2_REGS                      (0x481AC000)
76#define SOC_GPIO_3_REGS                      (0x481AE000)
77
78/** @brief Base addresses of DMTIMER memory mapped registers                  */
79#define SOC_DMTIMER_0_REGS                   (0x44E05000)
80#define SOC_DMTIMER_1_REGS                   (0x44E31000)
81#define SOC_DMTIMER_2_REGS                   (0x48040000)
82#define SOC_DMTIMER_3_REGS                   (0x48042000)
83#define SOC_DMTIMER_4_REGS                   (0x48044000)
84#define SOC_DMTIMER_5_REGS                   (0x48046000)
85#define SOC_DMTIMER_6_REGS                   (0x48048000)
86#define SOC_DMTIMER_7_REGS                   (0x4804A000)
87
88/** @brief Base address of MMC memory mapped registers                        */
89#define SOC_MMCHS_0_REGS                     (0x48060000)
90#define SOC_MMCHS_1_REGS                     (0x481D8000)
91#define SOC_MMCHS_2_REGS                     (0x47810000)
92
93/** @brief Base address of GPMC memory mapped registers                       */
94#define SOC_GPMC_0_REGS                      (0x50000000)
95
96/** @brief Base address of GPMC memory mapped registers                       */
97#define SOC_ELM_0_REGS                       (0x48080000)
98
99/** @brief Base address of I2C memory mapped registers                        */
100#define SOC_I2C_0_REGS                       (0x44E0B000)
101#define SOC_I2C_1_REGS                       (0x4802A000)
102#define SOC_I2C_2_REGS                       (0x4819C000)
103
104/** @brief Base address of WDT memory mapped registers                        */
105#define SOC_WDT_0_REGS                       (0x44E33000)
106#define SOC_WDT_1_REGS                       (0x44E35000)
107
108/** @brief Base address of WDT memory mapped registers                        */
109#define SOC_CPSW_SS_REGS                     (0x4A100000)
110#define SOC_CPSW_MDIO_REGS                   (0x4A101000)
111#define SOC_CPSW_WR_REGS                     (0x4A101200)
112#define SOC_CPSW_CPDMA_REGS                  (0x4A100800)
113#define SOC_CPSW_ALE_REGS                    (0x4A100D00)
114#define SOC_CPSW_STAT_REGS                   (0x4A100900)
115#define SOC_CPSW_PORT_0_REGS                 (0x4A100100)
116#define SOC_CPSW_PORT_1_REGS                 (0x4A100200)
117#define SOC_CPSW_SLIVER_1_REGS               (0x4A100D80)
118#define SOC_CPSW_PORT_2_REGS                 (0x4A100300)
119#define SOC_CPSW_SLIVER_2_REGS               (0x4A100DC0)
120#define SOC_CPSW_CPPI_RAM_REGS               (0x4A102000)
121
122/** @brief Base address of McASP memory mapped registers                      */
123#define SOC_MCASP_0_CTRL_REGS                (0x48038000)
124#define SOC_MCASP_0_FIFO_REGS                (SOC_MCASP_0_CTRL_REGS + 0x1000)
125#define SOC_MCASP_0_DATA_REGS                (0x46000000)
126#define SOC_MCASP_1_CTRL_REGS                (0x4803C000)
127#define SOC_MCASP_1_FIFO_REGS                (SOC_MCASP_1_CTRL_REGS + 0x1000)
128#define SOC_MCASP_1_DATA_REGS                (0x46400000)
129
130/** @brief Base address of EMIF memory mapped registers                       */
131#define SOC_EMIF_0_REGS                      (0x4C000000)
132
133/** @brief Base addresses of RTC memory mapped registers                      */
134#define SOC_RTC_0_REGS                       (0x44E3E000)
135
136/** @brief Base addresses of PRCM memory mapped registers                     */
137#define SOC_PRCM_REGS                        (0x44E00000)
138#define SOC_CM_PER_REGS                      (SOC_PRCM_REGS + 0)
139#define SOC_CM_WKUP_REGS                     (SOC_PRCM_REGS + 0x400)
140#define SOC_CM_DPLL_REGS                     (SOC_PRCM_REGS + 0x500)
141#define SOC_CM_MPU_REGS                      (SOC_PRCM_REGS + 0x600)
142#define SOC_CM_DEVICE_REGS                   (SOC_PRCM_REGS + 0x700)
143#define SOC_CM_RTC_REGS                      (SOC_PRCM_REGS + 0x800)
144#define SOC_CM_GFX_REGS                      (SOC_PRCM_REGS + 0x900)
145#define SOC_CM_CEFUSE_REGS                   (SOC_PRCM_REGS + 0xA00)
146#define SOC_OCP_SOCKET_RAM_REGS              (SOC_PRCM_REGS + 0xB00)
147#define SOC_PRM_PER_REGS                     (SOC_PRCM_REGS + 0xC00)
148#define SOC_PRM_WKUP_REGS                    (SOC_PRCM_REGS + 0xD00)
149#define SOC_PRM_MPU_REGS                     (SOC_PRCM_REGS + 0xE00)
150#define SOC_PRM_DEVICE_REGS                  (SOC_PRCM_REGS + 0xF00)
151#define SOC_PRM_RTC_REGS                     (SOC_PRCM_REGS + 0x1000)
152#define SOC_PRM_GFX_REGS                     (SOC_PRCM_REGS + 0x1100)
153#define SOC_PRM_CEFUSE_REGS                  (SOC_PRCM_REGS + 0x1200)
154
155/** @brief Base address of control module memory mapped registers             */
156#define SOC_CONTROL_REGS                     (0x44E10000)
157
158
159/** @brief Base address of Channel controller  memory mapped registers        */
160#define SOC_EDMA30CC_0_REGS                  (0x49000000)
161
162/** @brief Base address of DCAN module memory mapped registers                */
163#define SOC_DCAN_0_REGS                      (0x481CC000)
164#define SOC_DCAN_1_REGS                      (0x481D0000)
165
166/******************************************************************************\
167*  Parameterizable Configuration:- These are fed directly from the RTL
168*  parameters for the given SOC
169\******************************************************************************/
170#define TPCC_MUX(n)                         0xF90 + ((n) * 4)
171
172
173#define SOC_LCDC_0_REGS                     0x4830E000
174
175#define SOC_ADC_TSC_0_REGS                  0x44E0D000
176
177/** @brief Base addresses of PWMSS memory mapped registers.                   */
178
179#define SOC_PWMSS0_REGS                     (0x48300000)
180#define SOC_PWMSS1_REGS                     (0x48302000)
181#define SOC_PWMSS2_REGS                     (0x48304000)
182
183#define SOC_ECAP_REGS                       (0x00000100)
184#define SOC_EQEP_REGS                       (0x00000180)
185#define SOC_EPWM_REGS                       (0x00000200)
186
187#define SOC_ECAP_0_REGS                     (SOC_PWMSS0_REGS + SOC_ECAP_REGS)
188#define SOC_ECAP_1_REGS                     (SOC_PWMSS1_REGS + SOC_ECAP_REGS)
189#define SOC_ECAP_2_REGS                     (SOC_PWMSS2_REGS + SOC_ECAP_REGS)
190
191#define SOC_EQEP_0_REGS                     (SOC_PWMSS0_REGS + SOC_EQEP_REGS)
192#define SOC_EQEP_1_REGS                     (SOC_PWMSS1_REGS + SOC_EQEP_REGS)
193#define SOC_EQEP_2_REGS                     (SOC_PWMSS2_REGS + SOC_EQEP_REGS)
194
195#define SOC_EPWM_0_REGS                     (SOC_PWMSS0_REGS + SOC_EPWM_REGS)
196#define SOC_EPWM_1_REGS                     (SOC_PWMSS1_REGS + SOC_EPWM_REGS)
197#define SOC_EPWM_2_REGS                     (SOC_PWMSS2_REGS + SOC_EPWM_REGS)
198
199
200#define SOC_EPWM_MODULE_FREQ                 100
201 
202#ifdef __cplusplus
203}
204#endif
205
206#endif  /* _SOC_AM33XX_H_ */
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