1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_beagle |
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5 | * |
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6 | * @brief I2C support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2012 Claas Ziemke. All rights reserved. |
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11 | * |
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12 | * Claas Ziemke |
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13 | * Kernerstrasse 11 |
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14 | * 70182 Stuttgart |
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15 | * Germany |
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16 | * <claas.ziemke@gmx.net> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_BEAGLE_I2C_H |
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24 | #define LIBBSP_ARM_BEAGLE_I2C_H |
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25 | |
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26 | #include <rtems.h> |
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27 | #include <dev/i2c/i2c.h> |
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28 | #include <bsp.h> |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif /* __cplusplus */ |
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33 | |
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34 | |
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35 | /* I2C Configuration Register (I2C_CON): */ |
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36 | |
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37 | #define BBB_I2C_CON_EN (1 << 15) /* I2C module enable */ |
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38 | #define BBB_I2C_CON_BE (1 << 14) /* Big endian mode */ |
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39 | #define BBB_I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ |
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40 | #define BBB_I2C_CON_MST (1 << 10) /* Master/slave mode */ |
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41 | #define BBB_I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ |
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42 | /* (master mode only) */ |
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43 | #define BBB_I2C_CON_XA (1 << 8) /* Expand address */ |
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44 | #define BBB_I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ |
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45 | #define BBB_I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ |
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46 | #define BBB_I2C_CON_CLR 0x0 /* Clear configuration register */ |
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47 | /* I2C Status Register (I2C_STAT): */ |
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48 | |
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49 | #define BBB_I2C_STAT_SBD (1 << 15) /* Single byte data */ |
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50 | #define BBB_I2C_STAT_BB (1 << 12) /* Bus busy */ |
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51 | #define BBB_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
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52 | #define BBB_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
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53 | #define BBB_I2C_STAT_AAS (1 << 9) /* Address as slave */ |
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54 | #define BBB_I2C_STAT_GC (1 << 5) |
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55 | #define BBB_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
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56 | #define BBB_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ |
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57 | #define BBB_I2C_STAT_ARDY (1 << 2) /* Register access ready */ |
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58 | #define BBB_I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ |
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59 | #define BBB_I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ |
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60 | |
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61 | /* I2C Interrupt Enable Register (I2C_IE): */ |
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62 | #define BBB_I2C_IE_GC_IE (1 << 5) |
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63 | #define BBB_I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ |
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64 | #define BBB_I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ |
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65 | #define BBB_I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ |
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66 | #define BBB_I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ |
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67 | #define BBB_I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ |
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68 | |
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69 | /* I2C SYSC Register (I2C_SYSC): */ |
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70 | #define BBB_I2C_SYSC_SRST (1 << 1) |
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71 | |
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72 | #define BBB_I2C_TIMEOUT 1000 |
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73 | |
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74 | #define BBB_I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ |
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75 | |
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76 | #define BBB_CONFIG_SYS_I2C_SPEED 100000 |
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77 | #define BBB_CONFIG_SYS_I2C_SLAVE 1 |
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78 | #define BBB_I2C_ALL_FLAGS 0x7FFF |
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79 | #define BBB_I2C_ALL_IRQ_FLAGS 0xFFFF |
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80 | |
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81 | #define BBB_I2C_SYSCLK 48000000 |
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82 | #define BBB_I2C_INTERNAL_CLK 12000000 |
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83 | #define BBB_I2C_SPEED_CLK 100000 |
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84 | |
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85 | #define BBB_I2C_IRQ_ERROR \ |
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86 | ( AM335X_I2C_IRQSTATUS_NACK \ |
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87 | | AM335X_I2C_IRQSTATUS_ROVR \ |
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88 | | AM335X_I2C_IRQSTATUS_AL \ |
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89 | | AM335X_I2C_IRQSTATUS_ARDY \ |
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90 | | AM335X_I2C_IRQSTATUS_RRDY \ |
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91 | | AM335X_I2C_IRQSTATUS_XRDY \ |
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92 | | AM335X_I2C_IRQSTATUS_XUDF ) |
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93 | |
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94 | #define BBB_I2C_IRQ_USED \ |
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95 | ( AM335X_I2C_IRQSTATUS_ARDY \ |
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96 | | AM335X_I2C_IRQSTATUS_XRDY ) |
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97 | |
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98 | #define BBB_I2C_0_BUS_PATH "/dev/i2c-0" |
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99 | #define BBB_I2C_1_BUS_PATH "/dev/i2c-1" |
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100 | #define BBB_I2C_2_BUS_PATH "/dev/i2c-2" |
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101 | |
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102 | #define BBB_I2C0_IRQ 70 |
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103 | #define BBB_I2C1_IRQ 71 |
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104 | #define BBB_I2C2_IRQ 30 |
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105 | |
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106 | #define BBB_MODE2 2 |
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107 | #define BBB_MODE3 3 |
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108 | |
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109 | typedef enum { |
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110 | I2C0, |
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111 | I2C1, |
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112 | I2C2, |
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113 | I2C_COUNT |
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114 | } bbb_i2c_id_t; |
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115 | |
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116 | typedef struct i2c_regs { |
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117 | uint32_t BBB_I2C_REVNB_LO; |
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118 | uint32_t BBB_I2C_REVNB_HI; |
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119 | uint32_t dummy1[ 2 ]; |
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120 | uint32_t BBB_I2C_SYSC; |
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121 | uint32_t dummy2[ 4 ]; |
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122 | uint32_t BBB_I2C_IRQSTATUS_RAW; |
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123 | uint32_t BBB_I2C_IRQSTATUS; |
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124 | uint32_t BBB_I2C_IRQENABLE_SET; |
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125 | uint32_t BBB_I2C_IRQENABLE_CLR; |
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126 | uint32_t BBB_I2C_WE; |
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127 | uint32_t BBB_I2C_DMARXENABLE_SET; |
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128 | uint32_t BBB_I2C_DMATXENABLE_SET; |
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129 | uint32_t BBB_I2C_DMARXENABLE_CLR; |
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130 | uint32_t BBB_I2C_DMATXENABLE_CLR; |
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131 | uint32_t BBB_I2C_DMARXWAKE_EN; |
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132 | uint32_t BBB_I2C_DMATXWAKE_EN; |
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133 | uint32_t dummy3[ 16 ]; |
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134 | uint32_t BBB_I2C_SYSS; |
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135 | uint32_t BBB_I2C_BUF; |
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136 | uint32_t BBB_I2C_CNT; |
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137 | uint32_t BBB_I2C_DATA; |
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138 | uint32_t dummy4; |
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139 | uint32_t BBB_I2C_CON; |
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140 | uint32_t BBB_I2C_OA; |
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141 | uint32_t BBB_I2C_SA; |
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142 | uint32_t BBB_I2C_PSC; |
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143 | uint32_t BBB_I2C_SCLL; |
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144 | uint32_t BBB_I2C_SCLH; |
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145 | uint32_t BBB_I2C_SYSTEST; |
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146 | uint32_t BBB_I2C_BUFSTAT; |
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147 | uint32_t BBB_I2C_OA1; |
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148 | uint32_t BBB_I2C_OA2; |
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149 | uint32_t BBB_I2C_OA3; |
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150 | uint32_t BBB_I2C_ACTOA; |
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151 | uint32_t BBB_I2C_SBLOCK; |
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152 | } bbb_i2c_regs; |
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153 | |
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154 | typedef struct bbb_i2c_bus { |
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155 | i2c_bus base; |
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156 | volatile bbb_i2c_regs *regs; |
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157 | i2c_msg *msgs; |
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158 | uint32_t msg_todo; |
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159 | uint32_t current_msg_todo; |
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160 | uint8_t *current_msg_byte; |
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161 | uint32_t current_todo; |
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162 | bool read; |
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163 | bool hold; |
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164 | rtems_id task_id; |
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165 | rtems_vector_number irq; |
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166 | uint32_t input_clock; |
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167 | uint32_t already_transferred; |
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168 | } bbb_i2c_bus; |
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169 | |
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170 | int am335x_i2c_bus_register( |
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171 | const char *bus_path, |
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172 | uintptr_t register_base, |
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173 | uint32_t input_clock, |
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174 | rtems_vector_number irq |
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175 | ); |
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176 | |
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177 | static inline int bbb_register_i2c_0( void ) |
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178 | { |
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179 | return am335x_i2c_bus_register( |
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180 | BBB_I2C_0_BUS_PATH, |
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181 | AM335X_I2C0_BASE, |
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182 | I2C_BUS_CLOCK_DEFAULT, |
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183 | BBB_I2C0_IRQ |
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184 | ); |
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185 | } |
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186 | |
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187 | static inline int bbb_register_i2c_1( void ) |
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188 | { |
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189 | return am335x_i2c_bus_register( |
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190 | BBB_I2C_1_BUS_PATH, |
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191 | AM335X_I2C1_BASE, |
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192 | I2C_BUS_CLOCK_DEFAULT, |
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193 | BBB_I2C1_IRQ |
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194 | ); |
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195 | } |
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196 | |
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197 | static inline int bbb_register_i2c_2( void ) |
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198 | { |
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199 | return am335x_i2c_bus_register( |
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200 | BBB_I2C_2_BUS_PATH, |
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201 | AM335X_I2C2_BASE, |
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202 | I2C_BUS_CLOCK_DEFAULT, |
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203 | BBB_I2C2_IRQ |
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204 | ); |
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205 | } |
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206 | |
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207 | #ifdef __cplusplus |
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208 | } |
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209 | #endif /* __cplusplus */ |
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210 | |
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211 | #endif /* LIBBSP_ARM_BEAGLE_I2C_H */ |
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