source: rtems/bsps/arm/beagle/include/bsp.h @ 61c51db

5
Last change on this file since 61c51db was 61c51db, checked in by Sebastian Huber <sebastian.huber@…>, on 07/24/18 at 06:25:35

bsp/beagle: Fix warnings

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File size: 8.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup arm_beagle
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
11 *
12 *  Claas Ziemke
13 *  Kernerstrasse 11
14 *  70182 Stuttgart
15 *  Germany
16 *  <claas.ziemke@gmx.net>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 *
22 * Modified by Ben Gras <beng@shrike-systems.com> to add lots
23 * of beagleboard/beaglebone definitions, delete lpc32xx specific
24 * ones, and merge with some other header files.
25 */
26
27#ifndef LIBBSP_ARM_BEAGLE_BSP_H
28#define LIBBSP_ARM_BEAGLE_BSP_H
29
30#include <bspopts.h>
31#include <stdint.h>
32#include <bsp/start.h>
33#include <bsp/default-initial-extension.h>
34#include <bsp/beagleboneblack.h>
35
36#include <rtems.h>
37#include <rtems/irq-extension.h>
38
39#include <libcpu/omap3.h>
40#include <libcpu/am335x.h>
41
42#define BSP_FEATURE_IRQ_EXTENSION
43
44/* UART base clock frequency */
45#define UART_CLOCK     48000000
46
47/* Access memory-mapped I/O devices */
48#define mmio_read(a)    (*(volatile uint32_t *)(a))
49#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
50#define mmio_set(a,v)   mmio_write((a), mmio_read((a)) | (v))
51#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
52
53#define REG16(x)(*((volatile uint16_t *)(x)))
54#define REG(x)(*((volatile uint32_t *)(x)))
55#define BIT(x)(0x1 << x)
56
57#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
58
59/* Write a uint32_t value to a memory address. */
60static inline void
61write32(uint32_t address, uint32_t value)
62{
63    REG(address) = value;
64}
65
66/* Read an uint32_t from a memory address */
67static inline uint32_t
68read32(uint32_t address)
69{
70    return REG(address);
71}
72
73/* Set a 32 bits value depending on a mask */
74static inline void
75set32(uint32_t address, uint32_t mask, uint32_t value)
76{
77    uint32_t val;
78    val = read32(address);
79    /* clear the bits */
80    val &= ~(mask);
81    /* apply the value using the mask */
82    val |= (value & mask);
83    write32(address, val);
84}
85
86/* Write a uint16_t value to a memory address. */
87static inline void
88write16(uint32_t address, uint16_t value)
89{
90    REG16(address) = value;
91}
92
93/* Read an uint16_t from a memory address */
94static inline uint16_t
95read16(uint32_t address)
96{
97    return REG16(address);
98}
99
100/* Data synchronization barrier */
101static inline void dsb(void)
102{
103    asm volatile("dsb" : : : "memory");
104}
105
106/* Instruction synchronization barrier */
107static inline void isb(void)
108{
109    asm volatile("isb" : : : "memory");
110}
111
112/* flush data cache */
113static inline void flush_data_cache(void)
114{
115    asm volatile(
116        "mov r0, #0\n"
117        "mcr p15, #0, r0, c7, c10, #4\n"
118        : /* No outputs */
119        : /* No inputs */
120        : "r0","memory"
121    );
122}
123
124#define __arch_getb(a)      (*(volatile unsigned char *)(a))
125#define __arch_getw(a)      (*(volatile unsigned short *)(a))
126#define __arch_getl(a)      (*(volatile unsigned int *)(a))
127
128#define __arch_putb(v,a)    (*(volatile unsigned char *)(a) = (v))
129#define __arch_putw(v,a)    (*(volatile unsigned short *)(a) = (v))
130#define __arch_putl(v,a)    (*(volatile unsigned int *)(a) = (v))
131
132#define writeb(v,c) ({ unsigned char  __v = v; __arch_putb(__v,c); __v; })
133#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
134#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
135
136#define readb(c)  ({ unsigned char  __v = __arch_getb(c); __v; })
137#define readw(c)  ({ unsigned short __v = __arch_getw(c); __v; })
138#define readl(c)  ({ unsigned int __v = __arch_getl(c); __v; })
139
140#define SYSTEM_CLOCK_12       12000000
141#define SYSTEM_CLOCK_13       13000000
142#define SYSTEM_CLOCK_192      19200000
143#define SYSTEM_CLOCK_96       96000000
144
145#if !defined(IS_DM3730) && !defined(IS_AM335X)
146#error Unrecognized BSP configured.
147#endif
148
149#if IS_DM3730
150#define BSP_DEVICEMEM_START 0x48000000
151#define BSP_DEVICEMEM_END   0x5F000000
152#endif
153
154#if IS_AM335X
155#define BSP_DEVICEMEM_START 0x44000000
156#define BSP_DEVICEMEM_END   0x57000000
157#endif
158
159/* per-target uart config */
160#if IS_AM335X
161#define BSP_CONSOLE_UART        1
162#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_1
163#define BSP_CONSOLE_UART_IRQ    OMAP3_UART1_IRQ
164#define BEAGLE_BASE_UART_1      0x44E09000
165#define BEAGLE_BASE_UART_2      0x48022000
166#define BEAGLE_BASE_UART_3      0x48024000
167#endif
168
169/* per-target uart config */
170#if IS_DM3730
171#define BSP_CONSOLE_UART        3
172#define BSP_CONSOLE_UART_BASE   BEAGLE_BASE_UART_3
173#define BSP_CONSOLE_UART_IRQ    OMAP3_UART3_IRQ
174#define BEAGLE_BASE_UART_1      0x4806A000
175#define BEAGLE_BASE_UART_2      0x4806C000
176#define BEAGLE_BASE_UART_3      0x49020000
177#endif
178
179/* GPIO pin config */
180#if IS_AM335X
181#define BSP_GPIO_PIN_COUNT 128
182#define BSP_GPIO_PINS_PER_BANK 32
183#endif
184
185#if IS_DM3730
186#define BSP_GPIO_PIN_COUNT 192
187#define BSP_GPIO_PINS_PER_BANK 32
188#endif
189
190#if BSP_START_COPY_FDT_FROM_U_BOOT
191#define BSP_FDT_IS_SUPPORTED
192#endif
193
194/* i2c stuff */
195typedef struct {
196    uint32_t rx_or_tx;
197    uint32_t stat;
198    uint32_t ctrl;
199    uint32_t clk_hi;
200    uint32_t clk_lo;
201    uint32_t adr;
202    uint32_t rxfl;
203    uint32_t txfl;
204    uint32_t rxb;
205    uint32_t txb;
206    uint32_t s_tx;
207    uint32_t s_txfl;
208} beagle_i2c;
209
210/* sctlr */
211/* Read System Control Register */
212static inline uint32_t read_sctlr(void)
213{
214    uint32_t ctl;
215
216    asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
217        : [ctl] "=r" (ctl));
218    return ctl;
219}
220
221/* Write System Control Register */
222static inline void write_sctlr(uint32_t ctl)
223{
224    asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
225        : : [ctl] "r" (ctl));
226    isb();
227}
228
229/* Read Auxiliary Control Register */
230static inline uint32_t read_actlr(void)
231{
232    uint32_t ctl;
233
234    asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
235            : [ctl] "=r" (ctl));
236    return ctl;
237}
238
239/* Write Auxiliary Control Register */
240static inline void write_actlr(uint32_t ctl)
241{
242    asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
243        : : [ctl] "r" (ctl));
244    isb();
245}
246
247/* Write Translation Table Base Control Register */
248static inline void write_ttbcr(uint32_t bcr)
249{
250        asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
251                        : : [bcr] "r" (bcr));
252
253        isb();
254}
255
256/* Read Domain Access Control Register */
257static inline uint32_t read_dacr(void)
258{
259        uint32_t dacr;
260
261        asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
262                        : [dacr] "=r" (dacr));
263
264        return dacr;
265}
266
267
268/* Write Domain Access Control Register */
269static inline void write_dacr(uint32_t dacr)
270{
271        asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
272                        : : [dacr] "r" (dacr));
273
274        isb();
275}
276
277static inline void refresh_tlb(void)
278{
279    dsb();
280
281    /* Invalidate entire unified TLB */
282    asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
283        : : [zero] "r" (0));
284
285    /* Invalidate all instruction caches to PoU.
286     * Also flushes branch target cache. */
287    asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
288        : : [zero] "r" (0));
289
290    /* Invalidate entire branch predictor array */
291    asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
292        : : [zero] "r" (0)); /* flush BTB */
293
294    dsb();
295    isb();
296}
297
298/* Read Translation Table Base Register 0 */
299static inline uint32_t read_ttbr0(void)
300{
301    uint32_t bar;
302
303    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
304        : [bar] "=r" (bar));
305
306    return bar & ARM_TTBR_ADDR_MASK;
307}
308
309
310/* Read Translation Table Base Register 0 */
311static inline uint32_t read_ttbr0_unmasked(void)
312{
313    uint32_t bar;
314
315    asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
316        : [bar] "=r" (bar));
317
318    return bar;
319}
320
321/* Write Translation Table Base Register 0 */
322static inline void write_ttbr0(uint32_t bar)
323{
324    dsb();
325    isb();
326    /* In our setup TTBR contains the base address *and* the flags
327       but other pieces of the kernel code expect ttbr to be the
328       base address of the l1 page table. We therefore add the
329       flags here and remove them in the read_ttbr0 */
330    uint32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
331    asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
332        : : [bar] "r" (v));
333
334    refresh_tlb();
335}
336
337/* Behaviour on fatal error; default: test-friendly.
338 * set breakpoint to bsp_fatal_extension.
339 */
340/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
341/*#define  BSP_PRESS_KEY_FOR_RESET     1 */
342#define    BSP_PRINT_EXCEPTION_CONTEXT 1
343    /* human-readable exception info */
344#define    BSP_RESET_BOARD_AT_EXIT 1
345    /* causes qemu to exit, signaling end of test */
346
347
348/**
349 * @defgroup arm_beagle Beaglebone, Beagleboard Support
350 *
351 * @ingroup bsp_arm
352 *
353 * @brief Beaglebones and beagleboards support package
354 *
355 */
356
357/**
358 * @brief Beagleboard specific set up of the MMU.
359 *
360 * Provide in the application to override.
361 */
362BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
363
364#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
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