[8f550d2] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup arm_beagle |
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| 5 | * |
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| 6 | * @brief BeagleBoard I2C bus initialization and API Support. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[369372c3] | 10 | * Copyright (c) 2016 Punit Vara <punitvara@gmail.com> |
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[8f550d2] | 11 | * Copyright (c) 2017 Sichen Zhao <zsc19940506@gmail.com> |
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[b89d6cc] | 12 | * Copyright (c) 2019 Christian Mauderer <christian.mauderer@embedded-brains.de> |
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[8f550d2] | 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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| 16 | * http://www.rtems.org/license/LICENSE. |
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| 17 | */ |
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| 18 | |
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[b89d6cc] | 19 | #include <rtems/bspIo.h> |
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[8f550d2] | 20 | #include <stdio.h> |
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| 21 | #include <bsp/i2c.h> |
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| 22 | #include <libcpu/am335x.h> |
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| 23 | #include <rtems/irq-extension.h> |
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| 24 | #include <rtems/counter.h> |
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| 25 | #include <bsp/bbb-gpio.h> |
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| 26 | #include <rtems/score/assert.h> |
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[b89d6cc] | 27 | #include <dev/i2c/i2c.h> |
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[8f550d2] | 28 | |
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[b89d6cc] | 29 | typedef struct bbb_i2c_bus { |
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| 30 | i2c_bus base; |
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| 31 | volatile bbb_i2c_regs *regs; |
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| 32 | struct { |
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| 33 | volatile uint32_t *ctrl_clkctrl; |
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| 34 | volatile uint32_t *i2c_clkctrl; |
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| 35 | volatile uint32_t *clkstctrl; |
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| 36 | } clkregs; |
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| 37 | struct { |
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| 38 | volatile uint32_t *conf_sda; |
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| 39 | uint32_t mmode_sda; |
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| 40 | volatile uint32_t *conf_scl; |
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| 41 | uint32_t mmode_scl; |
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| 42 | } pinregs; |
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| 43 | rtems_id task_id; |
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| 44 | rtems_vector_number irq; |
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| 45 | i2c_msg *buffer; |
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| 46 | size_t buffer_pos; |
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| 47 | int error; |
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| 48 | uint32_t con_reg; |
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| 49 | } bbb_i2c_bus; |
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| 50 | |
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| 51 | #define TRANSFER_TIMEOUT_COUNT 100 |
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| 52 | #define FIFO_THRESHOLD 5 |
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| 53 | #define min(l,r) ((l) < (r) ? (l) : (r)) |
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| 54 | #if 0 |
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| 55 | #define debug_print(fmt, args...) printk("bbb-i2c: " fmt, ## args) |
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| 56 | #else |
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| 57 | #define debug_print(fmt, args...) |
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| 58 | #endif |
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| 59 | |
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| 60 | static int am335x_i2c_fill_registers( |
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| 61 | bbb_i2c_bus *bus, |
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| 62 | uintptr_t register_base |
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| 63 | ) |
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[8f550d2] | 64 | { |
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[b89d6cc] | 65 | /* FIXME: The pin handling should be replaced by a proper pin handling during |
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| 66 | * initialization. This one is heavily board specific. */ |
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| 67 | #if ! IS_AM335X |
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| 68 | printk ("The I2C driver currently only works on Beagle Bone. Please add your pin configs.") |
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| 69 | return EINVAL; |
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| 70 | #endif |
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| 71 | bus->regs = (volatile bbb_i2c_regs *) register_base; |
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| 72 | switch ((intptr_t) bus->regs) { |
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| 73 | case AM335X_I2C0_BASE: |
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| 74 | bus->clkregs.ctrl_clkctrl = ®(AM335X_SOC_CM_WKUP_REGS + |
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| 75 | AM335X_CM_WKUP_CONTROL_CLKCTRL); |
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| 76 | bus->clkregs.i2c_clkctrl = ®(AM335X_SOC_CM_WKUP_REGS + |
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| 77 | AM335X_CM_WKUP_I2C0_CLKCTRL); |
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| 78 | bus->clkregs.clkstctrl = ®(AM335X_SOC_CM_WKUP_REGS + |
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| 79 | AM335X_CM_WKUP_CLKSTCTRL); |
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| 80 | bus->pinregs.conf_sda = ®(AM335X_PADCONF_BASE + AM335X_CONF_I2C0_SDA); |
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| 81 | bus->pinregs.mmode_sda = 0; |
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| 82 | bus->pinregs.conf_scl = ®(AM335X_PADCONF_BASE + AM335X_CONF_I2C0_SCL); |
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| 83 | bus->pinregs.mmode_scl = 0; |
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| 84 | break; |
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| 85 | case AM335X_I2C1_BASE: |
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| 86 | bus->clkregs.ctrl_clkctrl = ®(AM335X_SOC_CM_WKUP_REGS + |
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| 87 | AM335X_CM_WKUP_CONTROL_CLKCTRL); |
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| 88 | bus->clkregs.i2c_clkctrl = ®(AM335X_CM_PER_ADDR + |
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| 89 | AM335X_CM_PER_I2C1_CLKCTRL); |
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| 90 | bus->clkregs.clkstctrl = NULL; |
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| 91 | bus->pinregs.conf_sda = ®(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D1); |
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| 92 | bus->pinregs.mmode_sda = 2; |
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| 93 | bus->pinregs.conf_scl = ®(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_CS0); |
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| 94 | bus->pinregs.mmode_scl = 2; |
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| 95 | break; |
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| 96 | case AM335X_I2C2_BASE: |
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| 97 | bus->clkregs.ctrl_clkctrl = ®(AM335X_SOC_CM_WKUP_REGS + |
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| 98 | AM335X_CM_WKUP_CONTROL_CLKCTRL); |
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| 99 | bus->clkregs.i2c_clkctrl = ®(AM335X_CM_PER_ADDR + |
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| 100 | AM335X_CM_PER_I2C2_CLKCTRL); |
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| 101 | bus->clkregs.clkstctrl = NULL; |
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| 102 | bus->pinregs.conf_sda = ®(AM335X_PADCONF_BASE + AM335X_CONF_UART1_CTSN); |
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| 103 | bus->pinregs.mmode_sda = 3; |
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| 104 | bus->pinregs.conf_scl = ®(AM335X_PADCONF_BASE + AM335X_CONF_UART1_RTSN); |
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| 105 | bus->pinregs.mmode_scl = 3; |
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| 106 | break; |
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| 107 | default: |
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| 108 | return EINVAL; |
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| 109 | } |
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| 110 | return 0; |
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| 111 | } |
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[8f550d2] | 112 | |
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[b89d6cc] | 113 | static void am335x_i2c_pinmux( bbb_i2c_bus *bus ) |
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| 114 | { |
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| 115 | *bus->pinregs.conf_sda = |
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| 116 | ( BBB_RXACTIVE | BBB_SLEWCTRL | bus->pinregs.mmode_sda); |
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| 117 | |
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| 118 | *bus->pinregs.conf_scl = |
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| 119 | ( BBB_RXACTIVE | BBB_SLEWCTRL | bus->pinregs.mmode_scl); |
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[8f550d2] | 120 | } |
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| 121 | |
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[b89d6cc] | 122 | static void am335x_i2c_module_clk_enable( bbb_i2c_bus *bus ) |
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[8f550d2] | 123 | { |
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[b89d6cc] | 124 | volatile uint32_t *ctrl_clkctrl = bus->clkregs.ctrl_clkctrl; |
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| 125 | volatile uint32_t *i2c_clkctrl = bus->clkregs.i2c_clkctrl; |
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| 126 | volatile uint32_t *clkstctrl = bus->clkregs.clkstctrl; |
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| 127 | |
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[8f550d2] | 128 | /* Writing to MODULEMODE field of AM335X_CM_WKUP_I2C0_CLKCTRL register. */ |
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[b89d6cc] | 129 | *i2c_clkctrl |= AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE; |
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[8f550d2] | 130 | |
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| 131 | /* Waiting for MODULEMODE field to reflect the written value. */ |
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| 132 | while ( AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE_ENABLE != |
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[b89d6cc] | 133 | ( *i2c_clkctrl & AM335X_CM_WKUP_I2C0_CLKCTRL_MODULEMODE ) ) |
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| 134 | { /* busy wait */ } |
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[8f550d2] | 135 | |
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| 136 | /* |
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[369372c3] | 137 | * Waiting for IDLEST field in AM335X_CM_WKUP_CONTROL_CLKCTRL |
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| 138 | * register to attain desired value. |
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| 139 | */ |
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[8f550d2] | 140 | while ( ( AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC << |
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| 141 | AM335X_CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT ) != |
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[b89d6cc] | 142 | ( *ctrl_clkctrl & AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST ) ) |
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| 143 | { /* busy wait */ } |
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| 144 | |
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| 145 | if ( clkstctrl != NULL ) { |
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| 146 | /* |
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| 147 | * Waiting for CLKACTIVITY_I2C0_GFCLK field in AM335X_CM_WKUP_CLKSTCTRL |
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| 148 | * register to attain desired value. |
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| 149 | */ |
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| 150 | while ( AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK != |
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| 151 | ( *clkstctrl & AM335X_CM_WKUP_CLKSTCTRL_CLKACTIVITY_I2C0_GFCLK ) ) |
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| 152 | { /* busy wait */ } |
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| 153 | } |
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[8f550d2] | 154 | |
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| 155 | /* |
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[369372c3] | 156 | * Waiting for IDLEST field in AM335X_CM_WKUP_I2C0_CLKCTRL register to attain |
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| 157 | * desired value. |
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| 158 | */ |
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[8f550d2] | 159 | while ( ( AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_FUNC << |
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| 160 | AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST_SHIFT ) != |
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[b89d6cc] | 161 | ( *i2c_clkctrl & AM335X_CM_WKUP_I2C0_CLKCTRL_IDLEST ) ) ; |
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[8f550d2] | 162 | } |
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| 163 | |
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[b89d6cc] | 164 | static int am335x_i2c_set_clock( |
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| 165 | i2c_bus *base, |
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| 166 | unsigned long clock |
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[8f550d2] | 167 | ) |
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| 168 | { |
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[b89d6cc] | 169 | bbb_i2c_bus *bus = (bbb_i2c_bus *) base; |
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| 170 | uint32_t prescaler, divider; |
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[8f550d2] | 171 | |
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[b89d6cc] | 172 | prescaler = ( BBB_I2C_SYSCLK / BBB_I2C_INTERNAL_CLK ) - 1; |
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| 173 | bus->regs->BBB_I2C_PSC = prescaler; |
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| 174 | divider = BBB_I2C_INTERNAL_CLK / ( 2 * clock ); |
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| 175 | bus->regs->BBB_I2C_SCLL = ( divider - 7 ); |
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| 176 | bus->regs->BBB_I2C_SCLH = ( divider - 5 ); |
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[8f550d2] | 177 | |
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[b89d6cc] | 178 | return 0; |
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[8f550d2] | 179 | } |
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| 180 | |
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[b89d6cc] | 181 | static int am335x_i2c_reset( bbb_i2c_bus *bus ) |
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[8f550d2] | 182 | { |
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[b89d6cc] | 183 | volatile bbb_i2c_regs *regs = bus->regs; |
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| 184 | int timeout = 100; |
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| 185 | int err; |
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[8f550d2] | 186 | |
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[b89d6cc] | 187 | bus->con_reg = 0; |
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| 188 | regs->BBB_I2C_CON = bus->con_reg; |
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| 189 | udelay( 50000 ); |
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[8f550d2] | 190 | |
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[b89d6cc] | 191 | regs->BBB_I2C_SYSC = AM335X_I2C_SYSC_SRST; |
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| 192 | udelay( 1000 ); |
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| 193 | regs->BBB_I2C_CON = AM335X_I2C_CON_I2C_EN; |
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[8f550d2] | 194 | |
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[b89d6cc] | 195 | while ( !( regs->BBB_I2C_SYSS & AM335X_I2C_SYSS_RDONE ) |
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| 196 | && timeout >= 0 ) { |
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| 197 | --timeout; |
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| 198 | udelay( 100 ); |
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| 199 | } |
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[8f550d2] | 200 | |
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[b89d6cc] | 201 | if ( timeout <= 0 ) { |
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| 202 | puts( "ERROR: Timeout in soft-reset\n" ); |
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| 203 | return ETIMEDOUT; |
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[8f550d2] | 204 | } |
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| 205 | |
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[b89d6cc] | 206 | /* Disable again after reset */ |
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| 207 | regs->BBB_I2C_CON = bus->con_reg; |
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[8f550d2] | 208 | |
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[b89d6cc] | 209 | err = am335x_i2c_set_clock( &bus->base, I2C_BUS_CLOCK_DEFAULT ); |
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| 210 | if (err) { |
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| 211 | return err; |
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| 212 | } |
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[8f550d2] | 213 | |
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[b89d6cc] | 214 | regs->BBB_I2C_BUF = AM335X_I2C_BUF_TXTRSH(FIFO_THRESHOLD) | |
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| 215 | AM335X_I2C_BUF_RXTRSH(FIFO_THRESHOLD); |
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[8f550d2] | 216 | |
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[b89d6cc] | 217 | /* Enable the I2C controller in master mode. */ |
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| 218 | bus->con_reg |= AM335X_I2C_CON_I2C_EN | AM335X_I2C_CON_MST; |
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| 219 | regs->BBB_I2C_CON = bus->con_reg; |
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[8f550d2] | 220 | |
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[b89d6cc] | 221 | regs->BBB_I2C_IRQENABLE_SET = |
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| 222 | AM335X_I2C_IRQSTATUS_XDR | AM335X_I2C_IRQSTATUS_XRDY | |
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| 223 | AM335X_I2C_IRQSTATUS_RDR | AM335X_I2C_IRQSTATUS_RRDY | |
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| 224 | AM335X_I2C_IRQSTATUS_ARDY | AM335X_I2C_IRQSTATUS_NACK | |
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| 225 | AM335X_I2C_IRQSTATUS_AL; |
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[8f550d2] | 226 | |
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[b89d6cc] | 227 | return 0; |
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[8f550d2] | 228 | } |
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| 229 | |
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[b89d6cc] | 230 | /* Return true if done. */ |
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| 231 | static bool am335x_i2c_transfer_intr(bbb_i2c_bus *bus, uint32_t status) |
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[8f550d2] | 232 | { |
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[b89d6cc] | 233 | size_t i; |
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| 234 | size_t amount = 0; |
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| 235 | volatile bbb_i2c_regs *regs = bus->regs; |
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[8f550d2] | 236 | |
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[b89d6cc] | 237 | /* Handle errors */ |
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| 238 | if ((status & AM335X_I2C_IRQSTATUS_NACK) != 0) { |
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| 239 | debug_print("NACK\n"); |
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| 240 | regs->BBB_I2C_IRQSTATUS = AM335X_I2C_IRQSTATUS_NACK; |
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| 241 | bus->error = ENXIO; |
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| 242 | } else if ((status & AM335X_I2C_IRQSTATUS_AL) != 0) { |
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| 243 | debug_print("Arbitration lost\n"); |
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| 244 | regs->BBB_I2C_IRQSTATUS = AM335X_I2C_IRQSTATUS_AL; |
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| 245 | bus->error = ENXIO; |
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| 246 | } |
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[8f550d2] | 247 | |
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[b89d6cc] | 248 | /* Transfer finished? */ |
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| 249 | if ((status & AM335X_I2C_IRQSTATUS_ARDY) != 0) { |
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| 250 | debug_print("ARDY transaction complete\n"); |
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| 251 | if (bus->error != 0 && (bus->buffer->flags & I2C_M_STOP) == 0) { |
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| 252 | regs->BBB_I2C_CON = bus->con_reg | AM335X_I2C_CON_STOP; |
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| 253 | } |
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| 254 | regs->BBB_I2C_IRQSTATUS = AM335X_I2C_IRQSTATUS_ARDY | |
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| 255 | AM335X_I2C_IRQSTATUS_RDR | |
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| 256 | AM335X_I2C_IRQSTATUS_RRDY | |
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| 257 | AM335X_I2C_IRQSTATUS_XDR | |
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| 258 | AM335X_I2C_IRQSTATUS_XRDY; |
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| 259 | return true; |
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[8f550d2] | 260 | } |
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| 261 | |
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[b89d6cc] | 262 | if (bus->buffer->flags & I2C_M_RD) { |
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| 263 | if (status & AM335X_I2C_IRQSTATUS_RDR) { |
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| 264 | debug_print("RDR\n"); |
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| 265 | /* last data received */ |
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| 266 | amount = bus->buffer->len - bus->buffer_pos; |
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| 267 | } else if (status & AM335X_I2C_IRQSTATUS_RRDY) { |
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| 268 | debug_print("RRDY\n"); |
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| 269 | /* FIFO threshold reached */ |
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| 270 | amount = min(FIFO_THRESHOLD, bus->buffer->len - bus->buffer_pos); |
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| 271 | } |
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[8f550d2] | 272 | |
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[b89d6cc] | 273 | debug_print("Read %d bytes\n", amount); |
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| 274 | for (i = 0; i < amount; i++) { |
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| 275 | bus->buffer->buf[bus->buffer_pos] = (uint8_t)(regs->BBB_I2C_DATA); |
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| 276 | ++bus->buffer_pos; |
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[8f550d2] | 277 | } |
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| 278 | |
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[b89d6cc] | 279 | if (status & AM335X_I2C_IRQSTATUS_RDR) { |
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| 280 | regs->BBB_I2C_IRQSTATUS =AM335X_I2C_IRQSTATUS_RDR; |
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| 281 | } |
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| 282 | if (status & AM335X_I2C_IRQSTATUS_RRDY) { |
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| 283 | regs->BBB_I2C_IRQSTATUS =AM335X_I2C_IRQSTATUS_RRDY; |
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| 284 | } |
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[8f550d2] | 285 | } else { |
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[b89d6cc] | 286 | if (status & AM335X_I2C_IRQSTATUS_XDR) { |
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| 287 | debug_print("XDR\n"); |
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| 288 | /* Remaining TX data won't reach the FIFO threshold. */ |
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| 289 | amount = bus->buffer->len - bus->buffer_pos; |
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| 290 | } else if (status & AM335X_I2C_IRQSTATUS_XRDY) { |
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| 291 | debug_print("XRDY\n"); |
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| 292 | /* FIFO threshold reached */ |
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| 293 | amount = min(FIFO_THRESHOLD, bus->buffer->len - bus->buffer_pos); |
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| 294 | } |
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| 295 | |
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| 296 | debug_print("Write %d bytes\n", amount); |
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| 297 | for (i = 0; i < amount; i++) { |
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| 298 | regs->BBB_I2C_DATA = bus->buffer->buf[bus->buffer_pos]; |
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| 299 | ++bus->buffer_pos; |
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| 300 | } |
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| 301 | |
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| 302 | if (status & AM335X_I2C_IRQSTATUS_XDR) { |
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| 303 | regs->BBB_I2C_IRQSTATUS = AM335X_I2C_IRQSTATUS_XDR; |
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| 304 | } |
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| 305 | if (status & AM335X_I2C_IRQSTATUS_XRDY) { |
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| 306 | regs->BBB_I2C_IRQSTATUS = AM335X_I2C_IRQSTATUS_XRDY; |
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| 307 | } |
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[8f550d2] | 308 | } |
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[b89d6cc] | 309 | |
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| 310 | return false; |
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[8f550d2] | 311 | } |
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| 312 | |
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| 313 | static void am335x_i2c_interrupt( void *arg ) |
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| 314 | { |
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[b89d6cc] | 315 | bbb_i2c_bus *bus = arg; |
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[8f550d2] | 316 | volatile bbb_i2c_regs *regs = bus->regs; |
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[b89d6cc] | 317 | uint32_t status; |
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[8f550d2] | 318 | |
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[b89d6cc] | 319 | status = regs->BBB_I2C_IRQSTATUS; |
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[8f550d2] | 320 | |
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[b89d6cc] | 321 | debug_print("interrupt: %08x\n", status); |
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[8f550d2] | 322 | |
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[b89d6cc] | 323 | if (status == 0) { |
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| 324 | /* Why can this even happen? */ |
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| 325 | return; |
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[8f550d2] | 326 | } |
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| 327 | |
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[b89d6cc] | 328 | if (bus->buffer == NULL) { |
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| 329 | debug_print("Buffer is NULL\n"); |
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| 330 | bus->error = EINVAL; |
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[8f550d2] | 331 | } |
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| 332 | |
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[b89d6cc] | 333 | if (bus->buffer == NULL || am335x_i2c_transfer_intr(bus, status)) { |
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| 334 | rtems_status_code sc; |
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| 335 | sc = rtems_event_transient_send( bus->task_id ); |
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| 336 | _Assert( sc == RTEMS_SUCCESSFUL ); |
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| 337 | (void) sc; /* suppress warning in case of no assert */ |
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[8f550d2] | 338 | } |
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| 339 | } |
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| 340 | |
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| 341 | static int am335x_i2c_transfer( |
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| 342 | i2c_bus *base, |
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| 343 | i2c_msg *msgs, |
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[b89d6cc] | 344 | uint32_t nmsgs |
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[8f550d2] | 345 | ) |
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| 346 | { |
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[b89d6cc] | 347 | size_t i; |
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| 348 | int err = 0; |
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| 349 | bool repstart = false; |
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| 350 | int timeout = 0; |
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| 351 | bbb_i2c_bus *bus = (bbb_i2c_bus *) base; |
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| 352 | volatile bbb_i2c_regs *regs = bus->regs; |
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| 353 | uint32_t reg; |
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| 354 | rtems_status_code sc; |
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| 355 | |
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| 356 | bus->task_id = rtems_task_self(); |
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[8f550d2] | 357 | |
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[b89d6cc] | 358 | for (i = 0; i < nmsgs; i++) { |
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| 359 | bus->buffer = &msgs[i]; |
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| 360 | bus->buffer_pos = 0; |
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| 361 | bus->error = 0; |
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[8f550d2] | 362 | |
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[b89d6cc] | 363 | debug_print("processing %2d/%d: addr: 0x%04x, flags: 0x%04x, len: %d, buf: %p\n", |
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| 364 | i, nmsgs, msgs[i].addr, msgs[i].flags, msgs[i].len, msgs[i].buf); |
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[8f550d2] | 365 | |
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[b89d6cc] | 366 | if (bus->buffer == NULL || bus->buffer->buf == NULL || |
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| 367 | bus->buffer->len == 0) { |
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| 368 | err = EINVAL; |
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| 369 | break; |
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[8f550d2] | 370 | } |
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| 371 | |
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[b89d6cc] | 372 | /* |
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| 373 | * Send START when bus is busy on repeated starts. |
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| 374 | * Otherwise wait some time. |
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| 375 | */ |
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| 376 | if (!repstart) { |
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| 377 | timeout = 0; |
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| 378 | while ((regs->BBB_I2C_IRQSTATUS_RAW & AM335X_I2C_IRQSTATUS_BB) != 0 |
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| 379 | && timeout <= TRANSFER_TIMEOUT_COUNT) { |
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| 380 | ++timeout; |
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| 381 | rtems_task_wake_after(RTEMS_MICROSECONDS_TO_TICKS(1000)); |
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| 382 | } |
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| 383 | if (timeout > TRANSFER_TIMEOUT_COUNT) { |
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| 384 | err = EBUSY; |
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| 385 | break; |
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| 386 | } |
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| 387 | timeout = 0; |
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| 388 | } else { |
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| 389 | repstart = false; |
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| 390 | } |
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| 391 | |
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| 392 | if ((bus->buffer->flags & I2C_M_STOP) == 0) { |
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| 393 | repstart = true; |
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| 394 | } |
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[8f550d2] | 395 | |
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[b89d6cc] | 396 | regs->BBB_I2C_SA = bus->buffer->addr; |
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| 397 | regs->BBB_I2C_CNT = bus->buffer->len; |
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[8f550d2] | 398 | |
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[b89d6cc] | 399 | regs->BBB_I2C_BUF |= AM335X_I2C_BUF_RXFIFO_CLR | AM335X_I2C_BUF_TXFIFO_CLR; |
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[8f550d2] | 400 | |
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[b89d6cc] | 401 | reg = bus->con_reg | AM335X_I2C_CON_START; |
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| 402 | if (!repstart) { |
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| 403 | reg |= AM335X_I2C_CON_STOP; |
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| 404 | } |
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| 405 | if ((bus->buffer->flags & I2C_M_RD) == 0) { |
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| 406 | reg |= AM335X_I2C_CON_TRX; |
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| 407 | } |
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| 408 | /* Implicit stop on last message. */ |
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| 409 | if (i == nmsgs - 1) { |
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| 410 | reg |= AM335X_I2C_CON_STOP; |
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| 411 | } |
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| 412 | regs->BBB_I2C_CON = reg; |
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| 413 | |
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| 414 | sc = rtems_event_transient_receive( RTEMS_WAIT, bus->base.timeout ); |
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| 415 | if ( sc != RTEMS_SUCCESSFUL ) { |
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| 416 | rtems_event_transient_clear(); |
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| 417 | err = ETIMEDOUT; |
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| 418 | break; |
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| 419 | } |
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| 420 | if (bus->error) { |
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| 421 | err = bus->error; |
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| 422 | break; |
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| 423 | } |
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[8f550d2] | 424 | } |
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| 425 | |
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[b89d6cc] | 426 | if (timeout == 0) { |
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| 427 | while ((regs->BBB_I2C_IRQSTATUS_RAW & AM335X_I2C_IRQSTATUS_BB) != 0 |
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| 428 | && timeout <= TRANSFER_TIMEOUT_COUNT) { |
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| 429 | ++timeout; |
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| 430 | rtems_task_wake_after(RTEMS_MICROSECONDS_TO_TICKS(1000)); |
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| 431 | } |
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| 432 | } |
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[8f550d2] | 433 | |
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[b89d6cc] | 434 | if ((regs->BBB_I2C_CON & AM335X_I2C_CON_MST) == 0) { |
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| 435 | regs->BBB_I2C_CON = bus->con_reg; |
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| 436 | } |
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[8f550d2] | 437 | |
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[b89d6cc] | 438 | bus->buffer = NULL; |
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[8f550d2] | 439 | |
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[b89d6cc] | 440 | return -err; |
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[8f550d2] | 441 | } |
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| 442 | |
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| 443 | static void am335x_i2c_destroy( i2c_bus *base ) |
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| 444 | { |
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| 445 | bbb_i2c_bus *bus = (bbb_i2c_bus *) base; |
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| 446 | rtems_status_code sc; |
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| 447 | |
---|
[b89d6cc] | 448 | bus->regs->BBB_I2C_IRQENABLE_CLR = 0xFFFF; |
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| 449 | bus->regs->BBB_I2C_CON = 0; |
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[8f550d2] | 450 | sc = rtems_interrupt_handler_remove( bus->irq, am335x_i2c_interrupt, bus ); |
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| 451 | _Assert( sc == RTEMS_SUCCESSFUL ); |
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| 452 | (void) sc; |
---|
| 453 | i2c_bus_destroy_and_free( &bus->base ); |
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| 454 | } |
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| 455 | |
---|
| 456 | int am335x_i2c_bus_register( |
---|
| 457 | const char *bus_path, |
---|
| 458 | uintptr_t register_base, |
---|
| 459 | uint32_t input_clock, |
---|
| 460 | rtems_vector_number irq |
---|
| 461 | ) |
---|
| 462 | { |
---|
| 463 | bbb_i2c_bus *bus; |
---|
| 464 | rtems_status_code sc; |
---|
| 465 | int err; |
---|
| 466 | |
---|
[b89d6cc] | 467 | (void) input_clock; /* FIXME: Unused. Left for compatibility. */ |
---|
| 468 | |
---|
[8f550d2] | 469 | bus = (bbb_i2c_bus *) i2c_bus_alloc_and_init( sizeof( *bus ) ); |
---|
| 470 | |
---|
| 471 | if ( bus == NULL ) { |
---|
| 472 | return -1; |
---|
| 473 | } |
---|
| 474 | |
---|
[b89d6cc] | 475 | bus->irq = irq; |
---|
[8f550d2] | 476 | |
---|
[b89d6cc] | 477 | err = am335x_i2c_fill_registers(bus, register_base); |
---|
| 478 | if (err != 0) { |
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[8f550d2] | 479 | ( *bus->base.destroy )( &bus->base ); |
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[b89d6cc] | 480 | rtems_set_errno_and_return_minus_one( err ); |
---|
| 481 | } |
---|
| 482 | am335x_i2c_module_clk_enable(bus); |
---|
| 483 | am335x_i2c_pinmux( bus ); |
---|
| 484 | err = am335x_i2c_reset( bus ); |
---|
| 485 | if (err != 0) { |
---|
| 486 | ( *bus->base.destroy )( &bus->base ); |
---|
| 487 | rtems_set_errno_and_return_minus_one( err ); |
---|
[8f550d2] | 488 | } |
---|
| 489 | |
---|
| 490 | sc = rtems_interrupt_handler_install( |
---|
[b89d6cc] | 491 | bus->irq, |
---|
[8f550d2] | 492 | "BBB_I2C", |
---|
| 493 | RTEMS_INTERRUPT_UNIQUE, |
---|
| 494 | (rtems_interrupt_handler) am335x_i2c_interrupt, |
---|
| 495 | bus |
---|
[b89d6cc] | 496 | ); |
---|
[8f550d2] | 497 | |
---|
| 498 | if ( sc != RTEMS_SUCCESSFUL ) { |
---|
| 499 | ( *bus->base.destroy )( &bus->base ); |
---|
| 500 | rtems_set_errno_and_return_minus_one( EIO ); |
---|
| 501 | } |
---|
| 502 | |
---|
| 503 | bus->base.transfer = am335x_i2c_transfer; |
---|
| 504 | bus->base.set_clock = am335x_i2c_set_clock; |
---|
| 505 | bus->base.destroy = am335x_i2c_destroy; |
---|
| 506 | |
---|
| 507 | return i2c_bus_register( &bus->base, bus_path ); |
---|
[9cb874d] | 508 | } |
---|