[151e53f] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup arm_beagle |
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| 5 | * |
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| 6 | * @brief Support for the BeagleBone Black. |
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| 7 | */ |
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| 8 | |
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| 9 | /** |
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| 10 | * Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com> |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.org/license/LICENSE. |
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| 15 | */ |
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| 16 | |
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| 17 | /* BSP specific function definitions for BeagleBone Black. |
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| 18 | * It is totally beased on Generic GPIO API definition. |
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| 19 | * For more details related to GPIO API please have a |
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| 20 | * look at libbbsp/shared/include/gpio.h |
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| 21 | */ |
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| 22 | |
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| 23 | #include <bsp/beagleboneblack.h> |
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| 24 | #include <bsp/irq-generic.h> |
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| 25 | #include <bsp/gpio.h> |
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| 26 | #include <bsp/bbb-gpio.h> |
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| 27 | #include <libcpu/am335x.h> |
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| 28 | |
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| 29 | #include <assert.h> |
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| 30 | #include <stdlib.h> |
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| 31 | |
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| 32 | /* Currently these definitions are for BeagleBone Black board only |
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| 33 | * Later on Beagle-xM board support can be added in this code. |
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| 34 | * After support gets added if condition should be removed |
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| 35 | */ |
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| 36 | #if IS_AM335X |
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| 37 | |
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| 38 | static const uint32_t gpio_bank_addrs[] = |
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| 39 | { AM335X_GPIO0_BASE, |
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| 40 | AM335X_GPIO1_BASE, |
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| 41 | AM335X_GPIO2_BASE, |
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| 42 | AM335X_GPIO3_BASE }; |
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| 43 | |
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| 44 | static const rtems_vector_number gpio_bank_vector[] = |
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| 45 | { AM335X_INT_GPIOINT0A, |
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| 46 | AM335X_INT_GPIOINT1A, |
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| 47 | AM335X_INT_GPIOINT2A, |
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| 48 | AM335X_INT_GPIOINT3A }; |
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| 49 | |
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| 50 | /* Macro for the gpio pin not having control module offset mapping */ |
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| 51 | #define CONF_NOT_DEFINED 0x00000000 |
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| 52 | |
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| 53 | /* Mapping of gpio pin nuber to the Control module mapped register offset */ |
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| 54 | static const uint32_t gpio_pad_conf[GPIO_BANK_COUNT][BSP_GPIO_PINS_PER_BANK] = |
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| 55 | { |
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| 56 | /* GPIO Module 0 */ |
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| 57 | { CONF_NOT_DEFINED, /* GPIO0[0] */ |
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| 58 | CONF_NOT_DEFINED, /* GPIO0[1] */ |
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| 59 | AM335X_CONF_SPI0_SCLK, /* GPIO0[2] */ |
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| 60 | AM335X_CONF_SPI0_D0, /* GPIO0[3] */ |
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| 61 | AM335X_CONF_SPI0_D1, /* GPIO0[4] */ |
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| 62 | AM335X_CONF_SPI0_CS0, /* GPIO0[5] */ |
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| 63 | CONF_NOT_DEFINED, /* GPIO0[6] */ |
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| 64 | CONF_NOT_DEFINED, /* GPIO0[7] */ |
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| 65 | AM335X_CONF_LCD_DATA12, /* GPIO0[8] */ |
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| 66 | AM335X_CONF_LCD_DATA13, /* GPIO0[9] */ |
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| 67 | AM335X_CONF_LCD_DATA14, /* GPIO0[10] */ |
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| 68 | AM335X_CONF_LCD_DATA15, /* GPIO0[11] */ |
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| 69 | AM335X_CONF_UART1_CTSN, /* GPIO0[12] */ |
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| 70 | AM335X_CONF_UART1_RTSN, /* GPIO0[13] */ |
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| 71 | AM335X_CONF_UART1_RXD, /* GPIO0[14] */ |
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| 72 | AM335X_CONF_UART1_TXD, /* GPIO0[15] */ |
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| 73 | CONF_NOT_DEFINED, /* GPIO0[16] */ |
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| 74 | CONF_NOT_DEFINED, /* GPIO0[17] */ |
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| 75 | CONF_NOT_DEFINED, /* GPIO0[18] */ |
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| 76 | CONF_NOT_DEFINED, /* GPIO0[19] */ |
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| 77 | CONF_NOT_DEFINED, /* GPIO0[20] */ |
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| 78 | CONF_NOT_DEFINED, /* GPIO0[21] */ |
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| 79 | AM335X_CONF_GPMC_AD8, /* GPIO0[22] */ |
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| 80 | AM335X_CONF_GPMC_AD9, /* GPIO0[23] */ |
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| 81 | CONF_NOT_DEFINED, /* GPIO0[24] */ |
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| 82 | CONF_NOT_DEFINED, /* GPIO0[25] */ |
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| 83 | AM335X_CONF_GPMC_AD10, /* GPIO0[26] */ |
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| 84 | AM335X_CONF_GPMC_AD11, /* GPIO0[27] */ |
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| 85 | CONF_NOT_DEFINED, /* GPIO0[28] */ |
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| 86 | CONF_NOT_DEFINED, /* GPIO0[29] */ |
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| 87 | AM335X_CONF_GPMC_WAIT0, /* GPIO0[30] */ |
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| 88 | AM335X_CONF_GPMC_WPN /* GPIO0[31] */ }, |
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| 89 | |
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| 90 | /* GPIO Module 1 */ |
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| 91 | { AM335X_CONF_GPMC_AD0, /* GPIO1[0] */ |
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| 92 | AM335X_CONF_GPMC_AD1, /* GPIO1[1] */ |
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| 93 | AM335X_CONF_GPMC_AD2, /* GPIO1[2] */ |
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| 94 | AM335X_CONF_GPMC_AD3, /* GPIO1[3] */ |
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| 95 | AM335X_CONF_GPMC_AD4, /* GPIO1[4] */ |
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| 96 | AM335X_CONF_GPMC_AD5, /* GPIO1[5] */ |
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| 97 | AM335X_CONF_GPMC_AD6, /* GPIO1[6] */ |
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| 98 | AM335X_CONF_GPMC_AD7, /* GPIO1[7] */ |
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| 99 | CONF_NOT_DEFINED, /* GPIO1[8] */ |
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| 100 | CONF_NOT_DEFINED, /* GPIO1[9] */ |
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| 101 | CONF_NOT_DEFINED, /* GPIO1[10] */ |
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| 102 | CONF_NOT_DEFINED, /* GPIO1[11] */ |
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| 103 | AM335X_CONF_GPMC_AD12, /* GPIO1[12] */ |
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| 104 | AM335X_CONF_GPMC_AD13, /* GPIO1[13] */ |
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| 105 | AM335X_CONF_GPMC_AD14, /* GPIO1[14] */ |
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| 106 | AM335X_CONF_GPMC_AD15, /* GPIO1[15] */ |
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| 107 | AM335X_CONF_GPMC_A0, /* GPIO1[16] */ |
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| 108 | AM335X_CONF_GPMC_A1, /* GPIO1[17] */ |
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| 109 | AM335X_CONF_GPMC_A2, /* GPIO1[18] */ |
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| 110 | AM335X_CONF_GPMC_A3, /* GPIO1[19] */ |
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| 111 | CONF_NOT_DEFINED, /* GPIO1[20] */ |
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| 112 | CONF_NOT_DEFINED, /* GPIO1[21] */ |
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| 113 | CONF_NOT_DEFINED, /* GPIO1[22] */ |
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| 114 | CONF_NOT_DEFINED, /* GPIO1[23] */ |
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| 115 | CONF_NOT_DEFINED, /* GPIO1[24] */ |
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| 116 | CONF_NOT_DEFINED, /* GPIO1[25] */ |
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| 117 | CONF_NOT_DEFINED, /* GPIO1[26] */ |
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| 118 | CONF_NOT_DEFINED, /* GPIO1[27] */ |
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| 119 | AM335X_CONF_GPMC_BEN1, /* GPIO1[28] */ |
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| 120 | AM335X_CONF_GPMC_CSN0, /* GPIO1[29] */ |
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| 121 | AM335X_CONF_GPMC_CSN1, /* GPIO1[30] */ |
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| 122 | AM335X_CONF_GPMC_CSN2 /* GPIO1[31] */ }, |
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| 123 | |
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| 124 | /* GPIO Module 2 */ |
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| 125 | { CONF_NOT_DEFINED, /* GPIO2[0] */ |
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| 126 | AM335X_CONF_GPMC_CLK, /* GPIO2[1] */ |
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| 127 | AM335X_CONF_GPMC_ADVN_ALE, /* GPIO2[2] */ |
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| 128 | AM335X_CONF_GPMC_OEN_REN, /* GPIO2[3] */ |
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| 129 | AM335X_CONF_GPMC_WEN, /* GPIO2[4] */ |
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| 130 | AM335X_CONF_GPMC_BEN0_CLE, /* GPIO2[5] */ |
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| 131 | AM335X_CONF_LCD_DATA0, /* GPIO2[6] */ |
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| 132 | AM335X_CONF_LCD_DATA1, /* GPIO2[7] */ |
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| 133 | AM335X_CONF_LCD_DATA2, /* GPIO2[8] */ |
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| 134 | AM335X_CONF_LCD_DATA3, /* GPIO2[9] */ |
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| 135 | AM335X_CONF_LCD_DATA4, /* GPIO2[10] */ |
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| 136 | AM335X_CONF_LCD_DATA5, /* GPIO2[11] */ |
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| 137 | AM335X_CONF_LCD_DATA6, /* GPIO2[12] */ |
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| 138 | AM335X_CONF_LCD_DATA7, /* GPIO2[13] */ |
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| 139 | AM335X_CONF_LCD_DATA8, /* GPIO2[14] */ |
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| 140 | AM335X_CONF_LCD_DATA9, /* GPIO2[15] */ |
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| 141 | AM335X_CONF_LCD_DATA10, /* GPIO2[16] */ |
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| 142 | AM335X_CONF_LCD_DATA11, /* GPIO2[17] */ |
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| 143 | CONF_NOT_DEFINED, /* GPIO2[18] */ |
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| 144 | CONF_NOT_DEFINED, /* GPIO2[19] */ |
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| 145 | CONF_NOT_DEFINED, /* GPIO2[20] */ |
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| 146 | CONF_NOT_DEFINED, /* GPIO2[21] */ |
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| 147 | AM335X_CONF_LCD_VSYNC, /* GPIO2[22] */ |
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| 148 | AM335X_CONF_LCD_HSYNC, /* GPIO2[23] */ |
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| 149 | AM335X_CONF_LCD_PCLK, /* GPIO2[24] */ |
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| 150 | AM335X_CONF_LCD_AC_BIAS_EN /* GPIO2[25] */ }, |
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| 151 | |
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| 152 | /* GPIO Module 3 */ |
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| 153 | { CONF_NOT_DEFINED, /* GPIO3[0] */ |
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| 154 | CONF_NOT_DEFINED, /* GPIO3[1] */ |
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| 155 | CONF_NOT_DEFINED, /* GPIO3[2] */ |
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| 156 | CONF_NOT_DEFINED, /* GPIO3[3] */ |
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| 157 | CONF_NOT_DEFINED, /* GPIO3[4] */ |
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| 158 | CONF_NOT_DEFINED, /* GPIO3[5] */ |
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| 159 | CONF_NOT_DEFINED, /* GPIO3[6] */ |
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| 160 | CONF_NOT_DEFINED, /* GPIO3[7] */ |
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| 161 | CONF_NOT_DEFINED, /* GPIO3[8] */ |
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| 162 | CONF_NOT_DEFINED, /* GPIO3[9] */ |
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| 163 | CONF_NOT_DEFINED, /* GPIO3[10] */ |
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| 164 | CONF_NOT_DEFINED, /* GPIO3[11] */ |
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| 165 | CONF_NOT_DEFINED, /* GPIO3[12] */ |
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| 166 | CONF_NOT_DEFINED, /* GPIO3[13] */ |
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| 167 | AM335X_CONF_MCASP0_ACLKX, /* GPIO3[14] */ |
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| 168 | AM335X_CONF_MCASP0_FSX, /* GPIO3[15] */ |
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| 169 | AM335X_CONF_MCASP0_AXR0, /* GPIO3[16] */ |
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| 170 | AM335X_CONF_MCASP0_AHCLKR, /* GPIO3[17] */ |
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| 171 | CONF_NOT_DEFINED, /* GPIO3[18] */ |
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| 172 | AM335X_CONF_MCASP0_FSR, /* GPIO3[19] */ |
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| 173 | CONF_NOT_DEFINED, /* GPIO3[20] */ |
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| 174 | AM335X_CONF_MCASP0_AHCLKX /* GPIO3[21] */ } |
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| 175 | }; |
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| 176 | |
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| 177 | /* Get the address of Base Register + Offset for pad config */ |
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| 178 | uint32_t static inline bbb_conf_reg(uint32_t bank, uint32_t pin) |
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| 179 | { |
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| 180 | return (AM335X_PADCONF_BASE + gpio_pad_conf[bank][pin]); |
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| 181 | } |
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| 182 | |
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| 183 | /* Get the value of Base Register + Offset */ |
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| 184 | uint32_t static inline bbb_reg(uint32_t bank, uint32_t reg) |
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| 185 | { |
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| 186 | return (gpio_bank_addrs[bank] + reg); |
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| 187 | } |
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| 188 | |
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| 189 | static rtems_status_code bbb_select_pin_function( |
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| 190 | uint32_t bank, |
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| 191 | uint32_t pin, |
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| 192 | uint32_t type |
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| 193 | ) { |
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| 194 | |
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| 195 | if ( type == BBB_DIGITAL_IN ) { |
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| 196 | mmio_set(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin)); |
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| 197 | } else { |
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| 198 | mmio_clear(bbb_reg(bank, AM335X_GPIO_OE), BIT(pin)); |
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| 199 | } |
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| 200 | |
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| 201 | return RTEMS_SUCCESSFUL; |
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| 202 | } |
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| 203 | |
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| 204 | rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask) |
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| 205 | { |
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| 206 | mmio_set(bbb_reg(bank, AM335X_GPIO_SETDATAOUT), bitmask); |
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| 207 | |
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| 208 | return RTEMS_SUCCESSFUL; |
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| 209 | } |
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| 210 | |
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| 211 | rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask) |
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| 212 | { |
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| 213 | mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), bitmask); |
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| 214 | |
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| 215 | return RTEMS_SUCCESSFUL; |
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| 216 | } |
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| 217 | |
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| 218 | uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask) |
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| 219 | { |
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| 220 | return (bbb_reg(bank, AM335X_GPIO_DATAIN) & bitmask); |
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| 221 | } |
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| 222 | |
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| 223 | rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin) |
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| 224 | { |
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| 225 | mmio_set(bbb_reg(bank, AM335X_GPIO_SETDATAOUT), BIT(pin)); |
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| 226 | |
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| 227 | return RTEMS_SUCCESSFUL; |
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| 228 | } |
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| 229 | |
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| 230 | rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin) |
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| 231 | { |
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| 232 | mmio_set(bbb_reg(bank, AM335X_GPIO_CLEARDATAOUT), BIT(pin)); |
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| 233 | |
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| 234 | return RTEMS_SUCCESSFUL; |
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| 235 | } |
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| 236 | |
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| 237 | uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin) |
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| 238 | { |
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| 239 | return (mmio_read(bbb_reg(bank, AM335X_GPIO_DATAIN)) & BIT(pin)); |
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| 240 | } |
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| 241 | |
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| 242 | rtems_status_code rtems_gpio_bsp_select_input( |
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| 243 | uint32_t bank, |
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| 244 | uint32_t pin, |
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| 245 | void *bsp_specific |
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| 246 | ) { |
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| 247 | return bbb_select_pin_function(bank, pin, BBB_DIGITAL_IN); |
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| 248 | } |
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| 249 | |
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| 250 | rtems_status_code rtems_gpio_bsp_select_output( |
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| 251 | uint32_t bank, |
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| 252 | uint32_t pin, |
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| 253 | void *bsp_specific |
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| 254 | ) { |
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| 255 | return bbb_select_pin_function(bank, pin, BBB_DIGITAL_OUT); |
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| 256 | } |
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| 257 | |
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[2502e26d] | 258 | rtems_status_code rtems_gpio_bsp_select_specific_io( |
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[151e53f] | 259 | uint32_t bank, |
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| 260 | uint32_t pin, |
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| 261 | uint32_t function, |
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| 262 | void *pin_data |
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| 263 | ) { |
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| 264 | return RTEMS_NOT_DEFINED; |
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| 265 | } |
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| 266 | |
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| 267 | rtems_status_code rtems_gpio_bsp_set_resistor_mode( |
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| 268 | uint32_t bank, |
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| 269 | uint32_t pin, |
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| 270 | rtems_gpio_pull_mode mode |
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| 271 | ) { |
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[42989d6] | 272 | /* TODO: Add support for setting up resistor mode */ |
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[151e53f] | 273 | return RTEMS_NOT_DEFINED; |
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| 274 | } |
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| 275 | |
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| 276 | rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank) |
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| 277 | { |
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| 278 | return gpio_bank_vector[bank]; |
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| 279 | } |
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| 280 | |
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| 281 | uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector) |
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| 282 | { |
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| 283 | uint32_t event_status; |
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| 284 | uint8_t bank_nr = 0; |
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| 285 | |
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| 286 | /* Following loop will get the bank number from vector number */ |
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| 287 | while (bank_nr < GPIO_BANK_COUNT && vector != gpio_bank_vector[bank_nr]) |
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| 288 | { |
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| 289 | bank_nr++; |
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| 290 | } |
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| 291 | |
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| 292 | /* Retrieve the interrupt event status. */ |
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| 293 | event_status = mmio_read(bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0)); |
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| 294 | |
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| 295 | /* Clear the interrupt line. */ |
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| 296 | mmio_write( |
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| 297 | (bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0)), event_status); |
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| 298 | |
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| 299 | return event_status; |
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| 300 | } |
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| 301 | |
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[5c337d7e] | 302 | rtems_status_code rtems_gpio_bsp_enable_interrupt( |
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[151e53f] | 303 | uint32_t bank, |
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| 304 | uint32_t pin, |
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| 305 | rtems_gpio_interrupt interrupt |
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| 306 | ) { |
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| 307 | |
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| 308 | /* Enable IRQ generation for the specific pin */ |
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| 309 | mmio_set(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_SET_0), BIT(pin)); |
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| 310 | |
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| 311 | switch ( interrupt ) { |
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| 312 | case FALLING_EDGE: |
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| 313 | /* Enables asynchronous falling edge detection. */ |
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| 314 | mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin)); |
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| 315 | break; |
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| 316 | case RISING_EDGE: |
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| 317 | /* Enables asynchronous rising edge detection. */ |
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| 318 | mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin)); |
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| 319 | break; |
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| 320 | case BOTH_EDGES: |
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| 321 | /* Enables asynchronous falling edge detection. */ |
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| 322 | mmio_set(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin)); |
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| 323 | |
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| 324 | /* Enables asynchronous rising edge detection. */ |
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| 325 | mmio_set(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin)); |
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| 326 | break; |
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| 327 | case LOW_LEVEL: |
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| 328 | /* Enables pin low level detection. */ |
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| 329 | mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin)); |
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| 330 | break; |
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| 331 | case HIGH_LEVEL: |
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| 332 | /* Enables pin high level detection. */ |
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| 333 | mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin)); |
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| 334 | break; |
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| 335 | case BOTH_LEVELS: |
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| 336 | /* Enables pin low level detection. */ |
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| 337 | mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin)); |
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| 338 | |
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| 339 | /* Enables pin high level detection. */ |
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| 340 | mmio_set(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin)); |
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| 341 | break; |
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| 342 | case NONE: |
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| 343 | default: |
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| 344 | return RTEMS_UNSATISFIED; |
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| 345 | } |
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| 346 | |
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| 347 | /* The detection starts after 5 clock cycles as per AM335X TRM |
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| 348 | * This period is required to clean the synchronization edge/ |
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| 349 | * level detection pipeline |
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| 350 | */ |
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| 351 | asm volatile("nop"); asm volatile("nop"); asm volatile("nop"); |
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| 352 | asm volatile("nop"); asm volatile("nop"); |
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| 353 | |
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| 354 | return RTEMS_SUCCESSFUL; |
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| 355 | } |
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| 356 | |
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[5c337d7e] | 357 | rtems_status_code rtems_gpio_bsp_disable_interrupt( |
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[151e53f] | 358 | uint32_t bank, |
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| 359 | uint32_t pin, |
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| 360 | rtems_gpio_interrupt interrupt |
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| 361 | ) { |
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| 362 | /* Clear IRQ generation for the specific pin */ |
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[867b99f] | 363 | mmio_write(bbb_reg(bank, AM335X_GPIO_IRQSTATUS_CLR_0), BIT(pin)); |
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[151e53f] | 364 | |
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| 365 | switch ( interrupt ) { |
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| 366 | case FALLING_EDGE: |
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| 367 | /* Disables asynchronous falling edge detection. */ |
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| 368 | mmio_clear(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin)); |
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| 369 | break; |
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| 370 | case RISING_EDGE: |
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| 371 | /* Disables asynchronous rising edge detection. */ |
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| 372 | mmio_clear(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin)); |
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| 373 | break; |
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| 374 | case BOTH_EDGES: |
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| 375 | /* Disables asynchronous falling edge detection. */ |
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| 376 | mmio_clear(bbb_reg(bank, AM335X_GPIO_FALLINGDETECT), BIT(pin)); |
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| 377 | |
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| 378 | /* Disables asynchronous rising edge detection. */ |
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| 379 | mmio_clear(bbb_reg(bank, AM335X_GPIO_RISINGDETECT), BIT(pin)); |
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| 380 | break; |
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| 381 | case LOW_LEVEL: |
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| 382 | /* Disables pin low level detection. */ |
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| 383 | mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin)); |
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| 384 | break; |
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| 385 | case HIGH_LEVEL: |
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| 386 | /* Disables pin high level detection. */ |
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| 387 | mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin)); |
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| 388 | break; |
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| 389 | case BOTH_LEVELS: |
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| 390 | /* Disables pin low level detection. */ |
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| 391 | mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT0), BIT(pin)); |
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| 392 | |
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| 393 | /* Disables pin high level detection. */ |
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| 394 | mmio_clear(bbb_reg(bank, AM335X_GPIO_LEVELDETECT1), BIT(pin)); |
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| 395 | break; |
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| 396 | case NONE: |
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| 397 | default: |
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| 398 | return RTEMS_UNSATISFIED; |
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| 399 | } |
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| 400 | |
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| 401 | /* The detection starts after 5 clock cycles as per AM335X TRM |
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| 402 | * This period is required to clean the synchronization edge/ |
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| 403 | * level detection pipeline |
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| 404 | */ |
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| 405 | asm volatile("nop"); asm volatile("nop"); asm volatile("nop"); |
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| 406 | asm volatile("nop"); asm volatile("nop"); |
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| 407 | |
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| 408 | return RTEMS_SUCCESSFUL; |
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| 409 | } |
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| 410 | |
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| 411 | rtems_status_code rtems_gpio_bsp_multi_select( |
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| 412 | rtems_gpio_multiple_pin_select *pins, |
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| 413 | uint32_t pin_count, |
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| 414 | uint32_t select_bank |
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| 415 | ) { |
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| 416 | uint32_t register_address; |
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| 417 | uint32_t select_register; |
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| 418 | uint8_t i; |
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| 419 | |
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| 420 | register_address = gpio_bank_addrs[select_bank] + AM335X_GPIO_OE; |
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| 421 | |
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| 422 | select_register = REG(register_address); |
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| 423 | |
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| 424 | for ( i = 0; i < pin_count; ++i ) { |
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| 425 | if ( pins[i].function == DIGITAL_INPUT ) { |
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| 426 | select_register |= BIT(pins[i].pin_number); |
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| 427 | } else if ( pins[i].function == DIGITAL_OUTPUT ) { |
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| 428 | select_register &= ~BIT(pins[i].pin_number); |
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| 429 | } else { /* BSP_SPECIFIC function. */ |
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| 430 | return RTEMS_NOT_DEFINED; |
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| 431 | } |
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| 432 | } |
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| 433 | |
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| 434 | REG(register_address) = select_register; |
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| 435 | |
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| 436 | return RTEMS_SUCCESSFUL; |
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| 437 | } |
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| 438 | |
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| 439 | rtems_status_code rtems_gpio_bsp_specific_group_operation( |
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| 440 | uint32_t bank, |
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| 441 | uint32_t *pins, |
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| 442 | uint32_t pin_count, |
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| 443 | void *arg |
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| 444 | ) { |
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| 445 | return RTEMS_NOT_DEFINED; |
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| 446 | } |
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| 447 | |
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| 448 | #endif /* IS_AM335X */ |
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| 449 | |
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| 450 | /* For support of BeagleboardxM */ |
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| 451 | #if IS_DM3730 |
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| 452 | |
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| 453 | /* Currently this section is just to satisfy |
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| 454 | * GPIO API and to make the build successful. |
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| 455 | * Later on support can be added here. |
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| 456 | */ |
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| 457 | |
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| 458 | rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask) |
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| 459 | { |
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| 460 | return RTEMS_NOT_DEFINED; |
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| 461 | } |
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| 462 | |
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| 463 | rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask) |
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| 464 | { |
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| 465 | return RTEMS_NOT_DEFINED; |
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| 466 | } |
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| 467 | |
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| 468 | uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask) |
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| 469 | { |
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| 470 | return -1; |
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| 471 | } |
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| 472 | |
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| 473 | rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin) |
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| 474 | { |
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| 475 | return RTEMS_NOT_DEFINED; |
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| 476 | } |
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| 477 | |
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| 478 | rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin) |
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| 479 | { |
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| 480 | return RTEMS_NOT_DEFINED; |
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| 481 | } |
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| 482 | |
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| 483 | uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin) |
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| 484 | { |
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| 485 | return -1; |
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| 486 | } |
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| 487 | |
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| 488 | rtems_status_code rtems_gpio_bsp_select_input( |
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| 489 | uint32_t bank, |
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| 490 | uint32_t pin, |
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| 491 | void *bsp_specific |
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| 492 | ) { |
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| 493 | return RTEMS_NOT_DEFINED; |
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| 494 | } |
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| 495 | |
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| 496 | rtems_status_code rtems_gpio_bsp_select_output( |
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| 497 | uint32_t bank, |
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| 498 | uint32_t pin, |
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| 499 | void *bsp_specific |
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| 500 | ) { |
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| 501 | return RTEMS_NOT_DEFINED; |
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| 502 | } |
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| 503 | |
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[2502e26d] | 504 | rtems_status_code rtems_gpio_bsp_select_specific_io( |
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[151e53f] | 505 | uint32_t bank, |
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| 506 | uint32_t pin, |
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| 507 | uint32_t function, |
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| 508 | void *pin_data |
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| 509 | ) { |
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| 510 | return RTEMS_NOT_DEFINED; |
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| 511 | } |
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| 512 | |
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| 513 | rtems_status_code rtems_gpio_bsp_set_resistor_mode( |
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| 514 | uint32_t bank, |
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| 515 | uint32_t pin, |
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| 516 | rtems_gpio_pull_mode mode |
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| 517 | ) { |
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| 518 | return RTEMS_NOT_DEFINED; |
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| 519 | } |
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| 520 | |
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| 521 | rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank) |
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| 522 | { |
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| 523 | return -1; |
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| 524 | } |
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| 525 | |
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| 526 | uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector) |
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| 527 | { |
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| 528 | return -1; |
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| 529 | } |
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| 530 | |
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[5c337d7e] | 531 | rtems_status_code rtems_gpio_bsp_enable_interrupt( |
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[151e53f] | 532 | uint32_t bank, |
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| 533 | uint32_t pin, |
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| 534 | rtems_gpio_interrupt interrupt |
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| 535 | ) { |
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| 536 | return RTEMS_NOT_DEFINED; |
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| 537 | } |
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| 538 | |
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[5c337d7e] | 539 | rtems_status_code rtems_gpio_bsp_disable_interrupt( |
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[151e53f] | 540 | uint32_t bank, |
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| 541 | uint32_t pin, |
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| 542 | rtems_gpio_interrupt interrupt |
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| 543 | ) { |
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| 544 | return RTEMS_NOT_DEFINED; |
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| 545 | } |
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| 546 | |
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| 547 | rtems_status_code rtems_gpio_bsp_multi_select( |
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| 548 | rtems_gpio_multiple_pin_select *pins, |
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| 549 | uint32_t pin_count, |
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| 550 | uint32_t select_bank |
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| 551 | ) { |
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| 552 | return RTEMS_NOT_DEFINED; |
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| 553 | } |
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| 554 | |
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| 555 | rtems_status_code rtems_gpio_bsp_specific_group_operation( |
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| 556 | uint32_t bank, |
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| 557 | uint32_t *pins, |
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| 558 | uint32_t pin_count, |
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| 559 | void *arg |
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| 560 | ) { |
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| 561 | return RTEMS_NOT_DEFINED; |
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| 562 | } |
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| 563 | |
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[2502e26d] | 564 | #endif /* IS_DM3730 */ |
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