1 | /* |
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2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/atsam-clock-config.h> |
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16 | #include <bspopts.h> |
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17 | #include <chip.h> |
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18 | |
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19 | #if ATSAM_MCK == 123000000 |
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20 | /* PLLA/HCLK/MCK clock is set to 492/246/123MHz */ |
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21 | const struct atsam_clock_config atsam_clock_config = { |
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22 | .pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x28U) | |
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23 | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)), |
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24 | .mckr_init = (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | |
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25 | PMC_MCKR_MDIV_PCK_DIV2), |
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26 | .mck_freq = 123*1000*1000 |
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27 | }; |
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28 | #elif ATSAM_MCK == 150000000 |
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29 | /* PLLA/HCLK/MCK clock is set to 300/300/150MHz */ |
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30 | const struct atsam_clock_config atsam_clock_config = { |
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31 | .pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) | |
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32 | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)), |
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33 | .mckr_init = (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK | |
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34 | PMC_MCKR_MDIV_PCK_DIV2), |
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35 | .mck_freq = 150*1000*1000 |
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36 | }; |
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37 | #elif ATSAM_MCK == 60000000 |
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38 | /* PLLA/HCLK/MCK clock is set to 60/60/60MHz */ |
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39 | const struct atsam_clock_config atsam_clock_config = { |
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40 | .pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x4U) | |
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41 | CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)), |
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42 | .mckr_init = (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK | |
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43 | PMC_MCKR_MDIV_EQ_PCK), |
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44 | .mck_freq = 60*1000*1000 |
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45 | }; |
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46 | #error Unknown ATSAM_MCK. |
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47 | #endif |
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