source: rtems/bsps/arm/atsam/start/bspstarthooks.c @ d7d0bba

Last change on this file since d7d0bba was d7d0bba, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 13, 2019 at 6:44:04 AM

bsp/atsam: Do not disable the WDT

The watchdog timer (WDT) can be configure only once. Do not touch it in
the BSP since the application may want to use it.

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Copyright (c) 2016 embedded brains GmbH Huber.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <bsp.h>
16#include <bsp/start.h>
17#include <bsp/pin-config.h>
18#include <bsp/atsam-clock-config.h>
19
20#include <chip.h>
21#include <include/board_lowlevel.h>
22#include <include/board_memories.h>
23
24#define SIZE_0K 0
25#define SIZE_32K (32 * 1024)
26#define SIZE_64K (64 * 1024)
27#define SIZE_128K (128 * 1024)
28
29#define ITCMCR_SZ_0K 0x0
30#define ITCMCR_SZ_32K 0x6
31#define ITCMCR_SZ_64K 0x7
32#define ITCMCR_SZ_128K 0x8
33
34static BSP_START_TEXT_SECTION void efc_send_command(uint32_t eefc)
35{
36  EFC->EEFC_FCR = eefc | EEFC_FCR_FKEY_PASSWD;
37}
38
39static BSP_START_TEXT_SECTION void tcm_enable(void)
40{
41  SCB->ITCMCR |= SCB_ITCMCR_EN_Msk;
42  SCB->DTCMCR |= SCB_DTCMCR_EN_Msk;
43}
44
45static BSP_START_TEXT_SECTION void tcm_disable(void)
46{
47  SCB->ITCMCR &= ~SCB_ITCMCR_EN_Msk;
48  SCB->DTCMCR &= ~SCB_DTCMCR_EN_Msk;
49}
50
51static BSP_START_TEXT_SECTION bool tcm_setup_and_check_if_do_efc_config(
52  uintptr_t tcm_size,
53  uint32_t itcmcr_sz
54)
55{
56  if (tcm_size == SIZE_0K && itcmcr_sz == ITCMCR_SZ_0K) {
57    tcm_disable();
58    return false;
59  } else if (tcm_size == SIZE_32K && itcmcr_sz == ITCMCR_SZ_32K) {
60    tcm_enable();
61    return false;
62  } else if (tcm_size == SIZE_64K && itcmcr_sz == ITCMCR_SZ_64K) {
63    tcm_enable();
64    return false;
65  } else if (tcm_size == SIZE_128K && itcmcr_sz == ITCMCR_SZ_128K) {
66    tcm_enable();
67    return false;
68  } else {
69    return true;
70  }
71}
72
73static bool ATSAM_START_SRAM_SECTION sdram_settings_unchanged(void)
74{
75  return (
76    (SDRAMC->SDRAMC_CR == BOARD_Sdram_Config.sdramc_cr) &&
77    (SDRAMC->SDRAMC_TR == BOARD_Sdram_Config.sdramc_tr) &&
78    (SDRAMC->SDRAMC_MDR == BOARD_Sdram_Config.sdramc_mdr) &&
79    (SDRAMC->SDRAMC_CFR1 == BOARD_Sdram_Config.sdramc_cfr1)
80  );
81}
82
83static void ATSAM_START_SRAM_SECTION setup_CPU_and_SDRAM(void)
84{
85  SystemInit();
86  if (!PMC_IsPeriphEnabled(ID_SDRAMC) || !sdram_settings_unchanged()) {
87    BOARD_ConfigureSdram();
88  }
89}
90
91static void configure_tcm(void)
92{
93  uintptr_t tcm_size;
94  uint32_t itcmcr_sz;
95
96  tcm_size = (uintptr_t) atsam_memory_itcm_size;
97  itcmcr_sz = (SCB->ITCMCR & SCB_ITCMCR_SZ_Msk) >> SCB_ITCMCR_SZ_Pos;
98
99  if (tcm_setup_and_check_if_do_efc_config(tcm_size, itcmcr_sz)) {
100    if (tcm_size == SIZE_128K) {
101      efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
102      efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
103      tcm_enable();
104    } else if (tcm_size == SIZE_64K) {
105      efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
106      efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
107      tcm_enable();
108    } else if (tcm_size == SIZE_32K) {
109      efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
110      efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
111      tcm_enable();
112    } else {
113      efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
114      efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
115      tcm_disable();
116    }
117  }
118}
119
120void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
121{
122  system_init_flash(BOARD_MCK);
123
124  PIO_Configure(&atsam_pin_config[0], atsam_pin_config_count);
125  MATRIX->CCFG_SYSIO = atsam_matrix_ccfg_sysio;
126
127  configure_tcm();
128#if ATSAM_CHANGE_CLOCK_FROM_SRAM != 0
129  /* Early copy of .fast_text section for CPU and SDRAM setup. */
130  bsp_start_memcpy_libc(
131    bsp_section_fast_text_begin,
132    bsp_section_fast_text_load_begin,
133    (size_t) bsp_section_fast_text_size
134  );
135#endif
136  setup_CPU_and_SDRAM();
137
138  if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
139    SCB_EnableICache();
140  }
141
142  if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
143    SCB_EnableDCache();
144  }
145
146  _SetupMemoryRegion();
147}
148
149void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
150{
151  bsp_start_copy_sections_compact();
152  SCB_CleanDCache();
153  SCB_InvalidateICache();
154  bsp_start_clear_bss();
155}
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