1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH Huber. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/start.h> |
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17 | #include <bsp/pin-config.h> |
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18 | #include <bsp/atsam-clock-config.h> |
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19 | |
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20 | #include <chip.h> |
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21 | #include <include/board_lowlevel.h> |
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22 | #include <include/board_memories.h> |
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23 | |
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24 | #define SIZE_0K 0 |
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25 | #define SIZE_32K (32 * 1024) |
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26 | #define SIZE_64K (64 * 1024) |
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27 | #define SIZE_128K (128 * 1024) |
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28 | |
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29 | #define ITCMCR_SZ_0K 0x0 |
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30 | #define ITCMCR_SZ_32K 0x6 |
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31 | #define ITCMCR_SZ_64K 0x7 |
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32 | #define ITCMCR_SZ_128K 0x8 |
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33 | |
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34 | static BSP_START_TEXT_SECTION void efc_send_command(uint32_t eefc) |
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35 | { |
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36 | EFC->EEFC_FCR = eefc | EEFC_FCR_FKEY_PASSWD; |
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37 | } |
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38 | |
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39 | static BSP_START_TEXT_SECTION void tcm_enable(void) |
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40 | { |
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41 | SCB->ITCMCR |= SCB_ITCMCR_EN_Msk; |
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42 | SCB->DTCMCR |= SCB_DTCMCR_EN_Msk; |
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43 | } |
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44 | |
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45 | static BSP_START_TEXT_SECTION void tcm_disable(void) |
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46 | { |
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47 | SCB->ITCMCR &= ~SCB_ITCMCR_EN_Msk; |
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48 | SCB->DTCMCR &= ~SCB_DTCMCR_EN_Msk; |
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49 | } |
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50 | |
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51 | static BSP_START_TEXT_SECTION bool tcm_setup_and_check_if_do_efc_config( |
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52 | uintptr_t tcm_size, |
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53 | uint32_t itcmcr_sz |
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54 | ) |
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55 | { |
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56 | if (tcm_size == SIZE_0K && itcmcr_sz == ITCMCR_SZ_0K) { |
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57 | tcm_disable(); |
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58 | return false; |
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59 | } else if (tcm_size == SIZE_32K && itcmcr_sz == ITCMCR_SZ_32K) { |
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60 | tcm_enable(); |
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61 | return false; |
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62 | } else if (tcm_size == SIZE_64K && itcmcr_sz == ITCMCR_SZ_64K) { |
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63 | tcm_enable(); |
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64 | return false; |
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65 | } else if (tcm_size == SIZE_128K && itcmcr_sz == ITCMCR_SZ_128K) { |
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66 | tcm_enable(); |
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67 | return false; |
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68 | } else { |
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69 | return true; |
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70 | } |
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71 | } |
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72 | |
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73 | static bool ATSAM_START_SRAM_SECTION sdram_settings_unchanged(void) |
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74 | { |
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75 | return ( |
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76 | (SDRAMC->SDRAMC_CR == BOARD_Sdram_Config.sdramc_cr) && |
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77 | (SDRAMC->SDRAMC_TR == BOARD_Sdram_Config.sdramc_tr) && |
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78 | (SDRAMC->SDRAMC_MDR == BOARD_Sdram_Config.sdramc_mdr) && |
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79 | (SDRAMC->SDRAMC_CFR1 == BOARD_Sdram_Config.sdramc_cfr1) |
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80 | ); |
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81 | } |
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82 | |
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83 | static void ATSAM_START_SRAM_SECTION setup_CPU_and_SDRAM(void) |
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84 | { |
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85 | SystemInit(); |
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86 | if (!PMC_IsPeriphEnabled(ID_SDRAMC) || !sdram_settings_unchanged()) { |
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87 | BOARD_ConfigureSdram(); |
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88 | } |
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89 | } |
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90 | |
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91 | static void configure_tcm(void) |
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92 | { |
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93 | uintptr_t tcm_size; |
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94 | uint32_t itcmcr_sz; |
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95 | |
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96 | tcm_size = (uintptr_t) atsam_memory_itcm_size; |
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97 | itcmcr_sz = (SCB->ITCMCR & SCB_ITCMCR_SZ_Msk) >> SCB_ITCMCR_SZ_Pos; |
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98 | |
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99 | if (tcm_setup_and_check_if_do_efc_config(tcm_size, itcmcr_sz)) { |
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100 | if (tcm_size == SIZE_128K) { |
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101 | efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7)); |
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102 | efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8)); |
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103 | tcm_enable(); |
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104 | } else if (tcm_size == SIZE_64K) { |
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105 | efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7)); |
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106 | efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8)); |
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107 | tcm_enable(); |
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108 | } else if (tcm_size == SIZE_32K) { |
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109 | efc_send_command(EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7)); |
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110 | efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8)); |
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111 | tcm_enable(); |
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112 | } else { |
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113 | efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7)); |
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114 | efc_send_command(EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8)); |
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115 | tcm_disable(); |
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116 | } |
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117 | } |
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118 | } |
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119 | |
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120 | void BSP_START_TEXT_SECTION bsp_start_hook_0(void) |
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121 | { |
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122 | system_init_flash(BOARD_MCK); |
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123 | |
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124 | PIO_Configure(&atsam_pin_config[0], atsam_pin_config_count); |
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125 | MATRIX->CCFG_SYSIO = atsam_matrix_ccfg_sysio; |
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126 | |
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127 | configure_tcm(); |
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128 | #if ATSAM_CHANGE_CLOCK_FROM_SRAM != 0 |
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129 | /* Early copy of .fast_text section for CPU and SDRAM setup. */ |
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130 | bsp_start_memcpy_libc( |
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131 | bsp_section_fast_text_begin, |
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132 | bsp_section_fast_text_load_begin, |
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133 | (size_t) bsp_section_fast_text_size |
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134 | ); |
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135 | #endif |
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136 | setup_CPU_and_SDRAM(); |
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137 | |
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138 | if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) { |
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139 | SCB_EnableICache(); |
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140 | } |
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141 | |
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142 | if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) { |
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143 | SCB_EnableDCache(); |
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144 | } |
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145 | |
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146 | _SetupMemoryRegion(); |
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147 | } |
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148 | |
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149 | void BSP_START_TEXT_SECTION bsp_start_hook_1(void) |
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150 | { |
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151 | bsp_start_copy_sections_compact(); |
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152 | SCB_CleanDCache(); |
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153 | SCB_InvalidateICache(); |
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154 | bsp_start_clear_bss(); |
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155 | WDT_Disable(WDT); |
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156 | } |
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