1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* Copyright (c) 2016, embedded brains GmbH */ |
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7 | /* */ |
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8 | /* All rights reserved. */ |
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9 | /* */ |
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10 | /* Redistribution and use in source and binary forms, with or without */ |
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11 | /* modification, are permitted provided that the following condition is met: */ |
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12 | /* */ |
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13 | /* - Redistributions of source code must retain the above copyright notice, */ |
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14 | /* this list of conditions and the disclaimer below. */ |
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15 | /* */ |
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16 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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17 | /* this software without specific prior written permission. */ |
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18 | /* */ |
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19 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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20 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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21 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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22 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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23 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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24 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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25 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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26 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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27 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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28 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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29 | /* ---------------------------------------------------------------------------- */ |
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30 | |
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31 | #include <bsp/atsam-clock-config.h> |
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32 | #include <bsp/atsam-spi.h> |
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33 | #include <bsp/iocopy.h> |
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34 | |
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35 | #include <rtems/thread.h> |
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36 | |
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37 | #include <dev/spi/spi.h> |
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38 | |
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39 | #include <string.h> |
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40 | |
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41 | #define MAX_SPI_FREQUENCY 50000000 |
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42 | |
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43 | #define DMA_NR_DESC_PER_DIR 3 |
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44 | #define DMA_DESC_ALLIGNMENT 4 |
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45 | |
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46 | #define DMA_BUF_RX 0 |
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47 | #define DMA_BUF_TX 1 |
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48 | #define DMA_BUF_DIRS 2 |
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49 | |
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50 | struct atsam_spi_xdma_buf { |
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51 | LinkedListDescriporView0 desc[DMA_NR_DESC_PER_DIR]; |
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52 | uint8_t leadbuf[CPU_CACHE_LINE_BYTES]; |
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53 | uint8_t trailbuf[CPU_CACHE_LINE_BYTES]; |
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54 | }; |
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55 | |
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56 | typedef struct { |
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57 | spi_bus base; |
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58 | rtems_binary_semaphore sem; |
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59 | const spi_ioc_transfer *msg_current; |
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60 | uint32_t msg_todo; |
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61 | int msg_error; |
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62 | Spi *spi_regs; |
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63 | uint32_t dma_tx_channel; |
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64 | uint32_t dma_rx_channel; |
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65 | struct atsam_spi_xdma_buf *dma_bufs; |
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66 | size_t leadbuf_rx_buffered_len; |
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67 | size_t trailbuf_rx_buffered_len; |
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68 | int transfer_in_progress; |
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69 | bool chip_select_decode; |
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70 | uint8_t spi_id; |
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71 | uint32_t peripheral_clk_per_us; |
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72 | uint32_t spi_mr; |
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73 | uint32_t spi_csr[4]; |
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74 | } atsam_spi_bus; |
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75 | |
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76 | static void atsam_spi_wakeup_task(atsam_spi_bus *bus) |
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77 | { |
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78 | rtems_binary_semaphore_post(&bus->sem); |
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79 | } |
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80 | |
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81 | static uint8_t atsam_calculate_dlybcs(const atsam_spi_bus *bus) |
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82 | { |
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83 | uint32_t dlybcs = bus->base.delay_usecs * bus->peripheral_clk_per_us; |
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84 | |
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85 | if (dlybcs > 0xff) { |
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86 | dlybcs = 0xff; |
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87 | } |
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88 | |
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89 | return dlybcs; |
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90 | } |
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91 | |
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92 | static uint32_t atsam_calculate_scbr(uint32_t speed_hz) |
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93 | { |
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94 | uint32_t scbr; |
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95 | |
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96 | scbr = BOARD_MCK / speed_hz; |
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97 | if (scbr > 0x0FF) { |
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98 | /* Best estimation we can offer with the hardware. */ |
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99 | scbr = 0x0FF; |
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100 | } |
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101 | if (scbr == 0) { |
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102 | /* SCBR = 0 isn't allowed. */ |
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103 | scbr = 1; |
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104 | } |
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105 | |
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106 | return scbr; |
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107 | } |
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108 | |
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109 | static void atsam_set_phase_and_polarity(uint32_t mode, uint32_t *csr) |
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110 | { |
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111 | uint32_t mode_mask = mode & SPI_MODE_3; |
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112 | |
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113 | switch(mode_mask) { |
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114 | case SPI_MODE_0: |
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115 | *csr |= SPI_CSR_NCPHA; |
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116 | break; |
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117 | case SPI_MODE_1: |
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118 | break; |
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119 | case SPI_MODE_2: |
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120 | *csr |= SPI_CSR_NCPHA; |
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121 | *csr |= SPI_CSR_CPOL; |
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122 | break; |
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123 | case SPI_MODE_3: |
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124 | *csr |= SPI_CSR_CPOL; |
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125 | break; |
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126 | } |
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127 | *csr |= SPI_CSR_CSAAT; |
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128 | } |
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129 | |
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130 | static void atsam_configure_spi(atsam_spi_bus *bus) |
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131 | { |
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132 | uint32_t scbr; |
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133 | uint32_t csr = 0; |
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134 | uint32_t mr; |
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135 | uint32_t cs = bus->base.cs; |
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136 | |
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137 | scbr = atsam_calculate_scbr(bus->base.speed_hz); |
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138 | |
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139 | mr = bus->spi_mr; |
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140 | |
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141 | if (bus->chip_select_decode) { |
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142 | mr |= SPI_MR_PCS(bus->base.cs); |
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143 | mr |= SPI_MR_PCSDEC; |
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144 | cs /= 4; |
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145 | } else { |
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146 | mr |= SPI_PCS(bus->base.cs); |
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147 | } |
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148 | |
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149 | bus->spi_regs->SPI_MR = mr; |
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150 | |
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151 | csr = bus->spi_csr[cs] |
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152 | | SPI_CSR_SCBR(scbr) |
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153 | | SPI_CSR_BITS(bus->base.bits_per_word - 8); |
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154 | |
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155 | atsam_set_phase_and_polarity(bus->base.mode, &csr); |
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156 | |
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157 | SPI_ConfigureNPCS(bus->spi_regs, cs, csr); |
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158 | } |
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159 | |
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160 | static void atsam_reset_spi(atsam_spi_bus *bus) |
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161 | { |
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162 | bus->spi_regs->SPI_CR = SPI_CR_SPIDIS; |
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163 | bus->spi_regs->SPI_CR = SPI_CR_SWRST; |
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164 | bus->spi_regs->SPI_CR = SPI_CR_SWRST; |
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165 | bus->spi_regs->SPI_CR = SPI_CR_SPIEN; |
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166 | } |
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167 | |
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168 | static void atsam_spi_check_alignment_and_set_up_dma_descriptors( |
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169 | atsam_spi_bus *bus, |
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170 | struct atsam_spi_xdma_buf *buf, |
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171 | const uint8_t *start, |
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172 | size_t len, |
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173 | bool tx |
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174 | ) |
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175 | { |
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176 | LinkedListDescriporView0 *curdesc = buf->desc; |
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177 | size_t misaligned_begin; |
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178 | size_t misaligned_end; |
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179 | size_t len_main; |
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180 | const uint8_t *start_main; |
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181 | const uint8_t *start_trail; |
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182 | |
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183 | /* Check alignments. */ |
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184 | if (len < CPU_CACHE_LINE_BYTES) { |
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185 | misaligned_begin = len; |
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186 | misaligned_end = 0; |
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187 | len_main = 0; |
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188 | } else { |
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189 | misaligned_begin = ((uint32_t) start) % CPU_CACHE_LINE_BYTES; |
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190 | misaligned_end = (((uint32_t) start) + len) % CPU_CACHE_LINE_BYTES; |
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191 | len_main = len - misaligned_begin - misaligned_end; |
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192 | } |
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193 | start_main = start + misaligned_begin; |
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194 | start_trail = start_main + len_main; |
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195 | |
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196 | /* Store length for copying data back. */ |
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197 | if (!tx) { |
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198 | bus->leadbuf_rx_buffered_len = misaligned_begin; |
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199 | bus->trailbuf_rx_buffered_len = misaligned_end; |
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200 | } |
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201 | |
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202 | /* Handle misalignment on begin. */ |
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203 | if (misaligned_begin != 0) { |
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204 | if (tx) { |
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205 | atsam_copy_to_io(buf->leadbuf, start, misaligned_begin); |
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206 | } |
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207 | curdesc->mbr_nda = (uint32_t) (&curdesc[1]); |
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208 | curdesc->mbr_ta = (uint32_t) buf->leadbuf; |
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209 | curdesc->mbr_ubc = misaligned_begin; |
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210 | } |
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211 | |
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212 | /* Main part */ |
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213 | if (len_main > 0) { |
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214 | curdesc->mbr_ubc |= tx ? XDMA_UBC_NSEN_UPDATED : XDMA_UBC_NDEN_UPDATED; |
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215 | curdesc->mbr_ubc |= XDMA_UBC_NVIEW_NDV0; |
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216 | curdesc->mbr_ubc |= XDMA_UBC_NDE_FETCH_EN; |
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217 | ++curdesc; |
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218 | |
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219 | curdesc->mbr_nda = (uint32_t) (&curdesc[1]); |
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220 | curdesc->mbr_ta = (uint32_t) start_main; |
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221 | curdesc->mbr_ubc = len_main; |
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222 | if (tx) { |
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223 | rtems_cache_flush_multiple_data_lines(start_main, len_main); |
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224 | } else { |
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225 | rtems_cache_invalidate_multiple_data_lines(start_main, len_main); |
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226 | } |
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227 | } |
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228 | |
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229 | /* Handle misalignment on end */ |
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230 | if (misaligned_end != 0) { |
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231 | curdesc->mbr_ubc |= tx ? XDMA_UBC_NSEN_UPDATED : XDMA_UBC_NDEN_UPDATED; |
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232 | curdesc->mbr_ubc |= XDMA_UBC_NVIEW_NDV0; |
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233 | curdesc->mbr_ubc |= XDMA_UBC_NDE_FETCH_EN; |
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234 | ++curdesc; |
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235 | |
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236 | if (tx) { |
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237 | atsam_copy_to_io(buf->trailbuf, start_trail, misaligned_end); |
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238 | } |
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239 | curdesc->mbr_nda = 0; |
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240 | curdesc->mbr_ta = (uint32_t) buf->trailbuf; |
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241 | curdesc->mbr_ubc = misaligned_end; |
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242 | curdesc->mbr_ubc |= XDMA_UBC_NDE_FETCH_DIS; |
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243 | } |
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244 | } |
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245 | |
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246 | static void atsam_spi_copy_back_rx_after_dma_transfer( |
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247 | atsam_spi_bus *bus |
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248 | ) |
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249 | { |
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250 | if (bus->leadbuf_rx_buffered_len != 0) { |
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251 | atsam_copy_from_io( |
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252 | bus->msg_current->rx_buf, |
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253 | bus->dma_bufs[DMA_BUF_RX].leadbuf, |
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254 | bus->leadbuf_rx_buffered_len |
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255 | ); |
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256 | } |
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257 | if (bus->trailbuf_rx_buffered_len != 0) { |
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258 | atsam_copy_from_io( |
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259 | bus->msg_current->rx_buf + bus->msg_current->len - |
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260 | bus->trailbuf_rx_buffered_len, |
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261 | bus->dma_bufs[DMA_BUF_RX].trailbuf, |
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262 | bus->trailbuf_rx_buffered_len |
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263 | ); |
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264 | } |
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265 | } |
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266 | |
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267 | static void atsam_spi_start_dma_transfer( |
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268 | atsam_spi_bus *bus, |
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269 | const spi_ioc_transfer *msg |
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270 | ) |
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271 | { |
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272 | Xdmac *pXdmac = XDMAC; |
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273 | |
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274 | atsam_spi_check_alignment_and_set_up_dma_descriptors( |
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275 | bus, |
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276 | &bus->dma_bufs[DMA_BUF_RX], |
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277 | msg->rx_buf, |
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278 | msg->len, |
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279 | false |
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280 | ); |
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281 | atsam_spi_check_alignment_and_set_up_dma_descriptors( |
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282 | bus, |
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283 | &bus->dma_bufs[DMA_BUF_TX], |
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284 | msg->tx_buf, |
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285 | msg->len, |
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286 | true |
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287 | ); |
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288 | |
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289 | XDMAC_SetDescriptorAddr( |
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290 | pXdmac, |
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291 | bus->dma_rx_channel, |
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292 | (uint32_t) bus->dma_bufs[DMA_BUF_RX].desc, |
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293 | 0 |
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294 | ); |
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295 | XDMAC_SetDescriptorControl( |
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296 | pXdmac, |
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297 | bus->dma_rx_channel, |
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298 | XDMAC_CNDC_NDVIEW_NDV0 | |
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299 | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED | |
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300 | XDMAC_CNDC_NDE_DSCR_FETCH_EN |
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301 | ); |
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302 | XDMAC_SetDescriptorAddr( |
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303 | pXdmac, |
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304 | bus->dma_tx_channel, |
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305 | (uint32_t) bus->dma_bufs[DMA_BUF_TX].desc, |
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306 | 0 |
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307 | ); |
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308 | XDMAC_SetDescriptorControl( |
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309 | pXdmac, |
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310 | bus->dma_tx_channel, |
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311 | XDMAC_CNDC_NDVIEW_NDV0 | |
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312 | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | |
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313 | XDMAC_CNDC_NDE_DSCR_FETCH_EN |
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314 | ); |
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315 | |
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316 | XDMAC_StartTransfer(pXdmac, bus->dma_rx_channel); |
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317 | XDMAC_StartTransfer(pXdmac, bus->dma_tx_channel); |
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318 | } |
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319 | |
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320 | static int atsam_check_configure_spi(atsam_spi_bus *bus, const spi_ioc_transfer *msg) |
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321 | { |
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322 | if ( |
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323 | msg->mode != bus->base.mode |
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324 | || msg->speed_hz != bus->base.speed_hz |
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325 | || msg->bits_per_word != bus->base.bits_per_word |
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326 | || msg->cs != bus->base.cs |
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327 | ) { |
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328 | if ( |
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329 | (msg->bits_per_word != 8 && msg->bits_per_word != 16) |
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330 | || msg->mode > 3 |
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331 | || msg->speed_hz > bus->base.max_speed_hz |
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332 | ) { |
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333 | return -EINVAL; |
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334 | } |
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335 | |
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336 | bus->base.mode = msg->mode; |
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337 | bus->base.speed_hz = msg->speed_hz; |
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338 | bus->base.bits_per_word = msg->bits_per_word; |
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339 | bus->base.cs = msg->cs; |
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340 | atsam_configure_spi(bus); |
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341 | } |
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342 | |
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343 | return 0; |
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344 | } |
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345 | |
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346 | static void atsam_spi_setup_transfer(atsam_spi_bus *bus) |
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347 | { |
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348 | uint32_t msg_todo = bus->msg_todo; |
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349 | |
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350 | bus->transfer_in_progress = 2; |
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351 | |
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352 | if (msg_todo > 0) { |
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353 | const spi_ioc_transfer *msg; |
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354 | int error; |
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355 | |
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356 | msg = bus->msg_current; |
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357 | error = atsam_check_configure_spi(bus, msg); |
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358 | if (error == 0) { |
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359 | atsam_spi_start_dma_transfer(bus, msg); |
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360 | } else { |
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361 | bus->msg_error = error; |
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362 | atsam_spi_wakeup_task(bus); |
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363 | } |
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364 | } else { |
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365 | atsam_spi_wakeup_task(bus); |
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366 | } |
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367 | } |
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368 | |
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369 | static void atsam_spi_dma_callback(uint32_t channel, void *arg) |
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370 | { |
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371 | atsam_spi_bus *bus = (atsam_spi_bus *)arg; |
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372 | |
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373 | --bus->transfer_in_progress; |
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374 | |
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375 | if (bus->transfer_in_progress == 0) { |
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376 | const spi_ioc_transfer *msg = bus->msg_current; |
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377 | |
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378 | if (msg->delay_usecs != bus->base.delay_usecs) { |
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379 | uint32_t mr; |
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380 | uint32_t mr_dlybcs; |
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381 | |
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382 | bus->base.delay_usecs = msg->delay_usecs; |
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383 | mr_dlybcs = SPI_MR_DLYBCS(atsam_calculate_dlybcs(bus)); |
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384 | bus->spi_mr = mr_dlybcs | SPI_MR_MSTR | SPI_MR_MODFDIS; |
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385 | |
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386 | mr = bus->spi_regs->SPI_MR; |
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387 | mr &= ~SPI_MR_DLYBCS_Msk; |
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388 | mr |= mr_dlybcs; |
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389 | bus->spi_regs->SPI_MR = mr; |
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390 | } |
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391 | |
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392 | if (msg->cs_change) { |
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393 | bus->spi_regs->SPI_CR = SPI_CR_LASTXFER; |
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394 | } |
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395 | |
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396 | atsam_spi_copy_back_rx_after_dma_transfer(bus); |
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397 | |
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398 | bus->msg_current = msg + 1; |
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399 | --bus->msg_todo; |
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400 | |
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401 | atsam_spi_setup_transfer(bus); |
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402 | } |
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403 | } |
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404 | |
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405 | static int atsam_spi_transfer( |
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406 | spi_bus *base, |
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407 | const spi_ioc_transfer *msgs, |
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408 | uint32_t msg_count |
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409 | ) |
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410 | { |
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411 | atsam_spi_bus *bus = (atsam_spi_bus *)base; |
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412 | |
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413 | bus->msg_current = msgs; |
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414 | bus->msg_todo = msg_count; |
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415 | bus->msg_error = 0; |
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416 | atsam_spi_setup_transfer(bus); |
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417 | rtems_binary_semaphore_wait(&bus->sem); |
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418 | return bus->msg_error; |
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419 | } |
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420 | |
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421 | |
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422 | static void atsam_spi_destroy(spi_bus *base) |
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423 | { |
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424 | atsam_spi_bus *bus = (atsam_spi_bus *)base; |
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425 | eXdmadRC rc; |
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426 | |
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427 | rc = XDMAD_SetCallback( |
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428 | &XDMAD_Instance, |
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429 | bus->dma_rx_channel, |
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430 | XDMAD_DoNothingCallback, |
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431 | NULL |
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432 | ); |
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433 | assert(rc == XDMAD_OK); |
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434 | |
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435 | rc = XDMAD_SetCallback( |
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436 | &XDMAD_Instance, |
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437 | bus->dma_tx_channel, |
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438 | XDMAD_DoNothingCallback, |
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439 | NULL |
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440 | ); |
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441 | assert(rc == XDMAD_OK); |
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442 | |
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443 | XDMAD_FreeChannel(&XDMAD_Instance, bus->dma_rx_channel); |
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444 | XDMAD_FreeChannel(&XDMAD_Instance, bus->dma_tx_channel); |
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445 | |
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446 | SPI_Disable(bus->spi_regs); |
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447 | PMC_DisablePeripheral(bus->spi_id); |
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448 | |
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449 | rtems_cache_coherent_free(bus->dma_bufs); |
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450 | rtems_binary_semaphore_destroy(&bus->sem); |
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451 | spi_bus_destroy_and_free(&bus->base); |
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452 | } |
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453 | |
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454 | static int atsam_spi_setup(spi_bus *base) |
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455 | { |
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456 | atsam_spi_bus *bus = (atsam_spi_bus *)base; |
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457 | |
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458 | if ( |
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459 | bus->base.speed_hz > MAX_SPI_FREQUENCY |
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460 | || (bus->base.bits_per_word != 8 && bus->base.bits_per_word != 16) |
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461 | ) { |
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462 | return -EINVAL; |
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463 | } |
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464 | atsam_configure_spi(bus); |
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465 | return 0; |
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466 | } |
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467 | |
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468 | static void atsam_spi_init_xdma(atsam_spi_bus *bus) |
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469 | { |
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470 | sXdmadCfg cfg; |
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471 | uint32_t xdmaInt; |
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472 | uint8_t channel; |
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473 | eXdmadRC rc; |
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474 | uint32_t xdma_cndc; |
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475 | |
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476 | bus->dma_bufs = rtems_cache_coherent_allocate( |
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477 | DMA_BUF_DIRS * sizeof(*(bus->dma_bufs)), |
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478 | DMA_DESC_ALLIGNMENT, |
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479 | 0 |
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480 | ); |
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481 | assert(bus->dma_bufs != NULL); |
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482 | |
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483 | bus->dma_tx_channel = XDMAD_AllocateChannel( |
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484 | &XDMAD_Instance, |
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485 | XDMAD_TRANSFER_MEMORY, |
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486 | bus->spi_id |
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487 | ); |
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488 | assert(bus->dma_tx_channel != XDMAD_ALLOC_FAILED); |
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489 | |
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490 | bus->dma_rx_channel = XDMAD_AllocateChannel( |
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491 | &XDMAD_Instance, |
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492 | bus->spi_id, |
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493 | XDMAD_TRANSFER_MEMORY |
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494 | ); |
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495 | assert(bus->dma_rx_channel != XDMAD_ALLOC_FAILED); |
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496 | |
---|
497 | rc = XDMAD_SetCallback( |
---|
498 | &XDMAD_Instance, |
---|
499 | bus->dma_rx_channel, |
---|
500 | atsam_spi_dma_callback, |
---|
501 | bus |
---|
502 | ); |
---|
503 | assert(rc == XDMAD_OK); |
---|
504 | |
---|
505 | rc = XDMAD_SetCallback( |
---|
506 | &XDMAD_Instance, |
---|
507 | bus->dma_tx_channel, |
---|
508 | atsam_spi_dma_callback, |
---|
509 | bus |
---|
510 | ); |
---|
511 | assert(rc == XDMAD_OK); |
---|
512 | |
---|
513 | rc = XDMAD_PrepareChannel(&XDMAD_Instance, bus->dma_rx_channel); |
---|
514 | assert(rc == XDMAD_OK); |
---|
515 | |
---|
516 | rc = XDMAD_PrepareChannel(&XDMAD_Instance, bus->dma_tx_channel); |
---|
517 | assert(rc == XDMAD_OK); |
---|
518 | |
---|
519 | /* Put all relevant interrupts on */ |
---|
520 | xdmaInt = ( |
---|
521 | XDMAC_CIE_BIE | |
---|
522 | XDMAC_CIE_DIE | |
---|
523 | XDMAC_CIE_FIE | |
---|
524 | XDMAC_CIE_RBIE | |
---|
525 | XDMAC_CIE_WBIE | |
---|
526 | XDMAC_CIE_ROIE); |
---|
527 | |
---|
528 | /* Setup RX */ |
---|
529 | memset(&cfg, 0, sizeof(cfg)); |
---|
530 | channel = XDMAIF_Get_ChannelNumber(bus->spi_id, XDMAD_TRANSFER_RX); |
---|
531 | cfg.mbr_sa = (uint32_t)&bus->spi_regs->SPI_RDR; |
---|
532 | cfg.mbr_cfg = |
---|
533 | XDMAC_CC_TYPE_PER_TRAN | |
---|
534 | XDMAC_CC_MBSIZE_SINGLE | |
---|
535 | XDMAC_CC_DSYNC_PER2MEM | |
---|
536 | XDMAC_CC_CSIZE_CHK_1 | |
---|
537 | XDMAC_CC_DWIDTH_BYTE | |
---|
538 | XDMAC_CC_SIF_AHB_IF1 | |
---|
539 | XDMAC_CC_DIF_AHB_IF1 | |
---|
540 | XDMAC_CC_SAM_FIXED_AM | |
---|
541 | XDMAC_CC_DAM_INCREMENTED_AM | |
---|
542 | XDMAC_CC_PERID(channel); |
---|
543 | xdma_cndc = XDMAC_CNDC_NDVIEW_NDV0 | |
---|
544 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | |
---|
545 | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED | |
---|
546 | XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED; |
---|
547 | rc = XDMAD_ConfigureTransfer( |
---|
548 | &XDMAD_Instance, |
---|
549 | bus->dma_rx_channel, |
---|
550 | &cfg, |
---|
551 | xdma_cndc, |
---|
552 | (uint32_t) bus->dma_bufs[DMA_BUF_RX].desc, |
---|
553 | xdmaInt |
---|
554 | ); |
---|
555 | assert(rc == XDMAD_OK); |
---|
556 | |
---|
557 | /* Setup TX */ |
---|
558 | memset(&cfg, 0, sizeof(cfg)); |
---|
559 | channel = XDMAIF_Get_ChannelNumber(bus->spi_id, XDMAD_TRANSFER_TX); |
---|
560 | cfg.mbr_da = (uint32_t)&bus->spi_regs->SPI_TDR; |
---|
561 | cfg.mbr_cfg = |
---|
562 | XDMAC_CC_TYPE_PER_TRAN | |
---|
563 | XDMAC_CC_MBSIZE_SINGLE | |
---|
564 | XDMAC_CC_DSYNC_MEM2PER | |
---|
565 | XDMAC_CC_CSIZE_CHK_1 | |
---|
566 | XDMAC_CC_DWIDTH_BYTE | |
---|
567 | XDMAC_CC_SIF_AHB_IF1 | |
---|
568 | XDMAC_CC_DIF_AHB_IF1 | |
---|
569 | XDMAC_CC_SAM_INCREMENTED_AM | |
---|
570 | XDMAC_CC_DAM_FIXED_AM | |
---|
571 | XDMAC_CC_PERID(channel); |
---|
572 | xdma_cndc = XDMAC_CNDC_NDVIEW_NDV0 | |
---|
573 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | |
---|
574 | XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED | |
---|
575 | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED; |
---|
576 | rc = XDMAD_ConfigureTransfer( |
---|
577 | &XDMAD_Instance, |
---|
578 | bus->dma_tx_channel, |
---|
579 | &cfg, |
---|
580 | xdma_cndc, |
---|
581 | (uint32_t) bus->dma_bufs[DMA_BUF_TX].desc, |
---|
582 | xdmaInt |
---|
583 | ); |
---|
584 | assert(rc == XDMAD_OK); |
---|
585 | } |
---|
586 | |
---|
587 | int spi_bus_register_atsam( |
---|
588 | const char *bus_path, |
---|
589 | const atsam_spi_config *config |
---|
590 | ) |
---|
591 | { |
---|
592 | atsam_spi_bus *bus; |
---|
593 | size_t i; |
---|
594 | |
---|
595 | bus = (atsam_spi_bus *) spi_bus_alloc_and_init(sizeof(*bus)); |
---|
596 | if (bus == NULL) { |
---|
597 | return -1; |
---|
598 | } |
---|
599 | |
---|
600 | bus->base.transfer = atsam_spi_transfer; |
---|
601 | bus->base.destroy = atsam_spi_destroy; |
---|
602 | bus->base.setup = atsam_spi_setup; |
---|
603 | bus->base.max_speed_hz = MAX_SPI_FREQUENCY; |
---|
604 | bus->base.bits_per_word = 8; |
---|
605 | bus->base.speed_hz = bus->base.max_speed_hz; |
---|
606 | bus->base.cs = 1; |
---|
607 | bus->spi_id = config->spi_peripheral_id; |
---|
608 | bus->spi_regs = config->spi_regs; |
---|
609 | bus->chip_select_decode = config->chip_select_decode; |
---|
610 | bus->peripheral_clk_per_us = BOARD_MCK / 1000000; |
---|
611 | bus->spi_mr = SPI_MR_MSTR | SPI_MR_MODFDIS; |
---|
612 | |
---|
613 | for (i = 0; i < RTEMS_ARRAY_SIZE(bus->spi_csr); ++i) { |
---|
614 | if (config->dlybs_in_ns[i] != 0) { |
---|
615 | bus->spi_csr[i] |= SPI_DLYBS(config->dlybs_in_ns[i], BOARD_MCK); |
---|
616 | } |
---|
617 | |
---|
618 | if (config->dlybct_in_ns[i] != 0) { |
---|
619 | bus->spi_csr[i] |= SPI_DLYBCT(config->dlybct_in_ns[i], BOARD_MCK); |
---|
620 | } |
---|
621 | } |
---|
622 | |
---|
623 | rtems_binary_semaphore_init(&bus->sem, "ATSAM SPI"); |
---|
624 | PIO_Configure(config->pins, config->pin_count); |
---|
625 | PMC_EnablePeripheral(config->spi_peripheral_id); |
---|
626 | atsam_reset_spi(bus); |
---|
627 | atsam_configure_spi(bus); |
---|
628 | atsam_spi_init_xdma(bus); |
---|
629 | |
---|
630 | return spi_bus_register(&bus->base, bus_path); |
---|
631 | } |
---|