source: rtems/bsps/arm/atsam/include/libchip/include/xdmad.h @ 5f813694

5
Last change on this file since 5f813694 was 5f813694, checked in by Sebastian Huber <sebastian.huber@…>, on 03/19/19 at 09:45:06

bsp/atsam: Simplify XDMAD_Handler()

Remove the channel status evaluation from XDMAD_Handler() and simply
hand over the status to the callbacks.
  • Property mode set to 100644
File size: 9.5 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
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10/* modification, are permitted provided that the following condition is met:    */
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12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
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15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
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22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _XDMAD_H
31#define _XDMAD_H
32
33
34/*----------------------------------------------------------------------------
35 *        Includes
36 *----------------------------------------------------------------------------*/
37
38#include "chip.h"
39#include <assert.h>
40
41
42/** \addtogroup dmad_defines DMA Driver Defines
43        @{*/
44/*----------------------------------------------------------------------------
45 *        Consts
46 *----------------------------------------------------------------------------*/
47#define XDMAD_TRANSFER_MEMORY  0xFF   /**< DMA transfer from or to memory */
48#define XDMAD_ALLOC_FAILED     0xFFFF /**< Channel allocate failed */
49
50#define XDMAD_TRANSFER_TX      0
51#define XDMAD_TRANSFER_RX      1
52
53/* XDMA_MBR_UBC */
54#define XDMA_UBC_NDE (0x1u << 24)
55#define   XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
56#define   XDMA_UBC_NDE_FETCH_EN  (0x1u << 24)
57#define XDMA_UBC_NSEN (0x1u << 25)
58#define   XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
59#define   XDMA_UBC_NSEN_UPDATED (0x1u << 25)
60#define XDMA_UBC_NDEN (0x1u << 26)
61#define   XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
62#define   XDMA_UBC_NDEN_UPDATED (0x1u << 26)
63#define XDMA_UBC_NVIEW_Pos 27
64#define    XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)
65#define    XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)
66#define    XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)
67#define    XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)
68#define    XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)
69
70/*----------------------------------------------------------------------------
71 *        MACRO
72 *----------------------------------------------------------------------------*/
73
74/**     @}*/
75
76/*----------------------------------------------------------------------------
77 *        Types
78 *----------------------------------------------------------------------------*/
79/** \addtogroup dmad_structs DMA Driver Structs
80        @{*/
81
82/** DMA status or return code */
83typedef enum _XdmadStatus {
84        XDMAD_OK = 0,        /**< Operation is successful */
85        XDMAD_PARTIAL_DONE,
86        XDMAD_DONE,
87        XDMAD_BUSY,          /**< Channel occupied or transfer not finished */
88        XDMAD_ERROR,         /**< Operation failed */
89        XDMAD_CANCELED       /**< Operation cancelled */
90} eXdmadStatus, eXdmadRC;
91
92/** DMA state for channel */
93typedef enum _XdmadState {
94        XDMAD_STATE_FREE = 0,      /**< Free channel */
95        XDMAD_STATE_ALLOCATED,     /**< Allocated to some peripheral */
96        XDMAD_STATE_START,         /**< DMA started */
97        XDMAD_STATE_IN_XFR,        /**< DMA in transferring */
98        XDMAD_STATE_DONE,          /**< DMA transfer done */
99        XDMAD_STATE_HALTED,        /**< DMA transfer stopped */
100} eXdmadState;
101
102/** DMA Programming state for channel */
103typedef enum _XdmadProgState {
104        XDMAD_SINGLE = 0,
105        XDMAD_MULTI,
106        XDMAD_LLI,
107} eXdmadProgState;
108
109/** DMA transfer callback */
110typedef void (*XdmadTransferCallback)(uint32_t Channel, void *pArg, uint32_t status);
111
112/** DMA driver channel */
113typedef struct _XdmadChannel {
114        XdmadTransferCallback fCallback; /**< Callback */
115        void *pArg;                     /**< Callback argument */
116        uint8_t bIrqOwner;              /**< Uses DMA handler or external one */
117        uint8_t bSrcPeriphID;           /**< HW ID for source */
118        uint8_t bDstPeriphID;           /**< HW ID for destination */
119        uint8_t bSrcTxIfID;             /**< DMA Tx Interface ID for source */
120        uint8_t bSrcRxIfID;             /**< DMA Rx Interface ID for source */
121        uint8_t bDstTxIfID;             /**< DMA Tx Interface ID for destination */
122        uint8_t bDstRxIfID;             /**< DMA Rx Interface ID for destination */
123        volatile uint8_t state;         /**< DMA channel state */
124} sXdmadChannel;
125
126/** DMA driver instance */
127typedef struct _Xdmad {
128        Xdmac *pXdmacs;
129        sXdmadChannel XdmaChannels[XDMACCHID_NUMBER];
130        uint8_t  numControllers;
131        uint8_t  numChannels;
132        uint8_t  xdmaMutex;
133} sXdmad;
134
135typedef struct _XdmadCfg {
136        /** Microblock Control Member. */
137        uint32_t mbr_ubc;
138        /** Source Address Member. */
139        uint32_t mbr_sa;
140        /** Destination Address Member. */
141        uint32_t mbr_da;
142        /** Configuration Register. */
143        uint32_t mbr_cfg;
144        /** Block Control Member. */
145        uint32_t mbr_bc;
146        /** Data Stride Member. */
147        uint32_t mbr_ds;
148        /** Source Microblock Stride Member. */
149        uint32_t mbr_sus;
150        /** Destination Microblock Stride Member. */
151        uint32_t mbr_dus;
152} sXdmadCfg;
153
154/** \brief Structure for storing parameters for DMA view0 that can be
155 * performed by the DMA Master transfer.*/
156typedef struct _LinkedListDescriporView0 {
157        /** Next Descriptor Address number. */
158        uint32_t mbr_nda;
159        /** Microblock Control Member. */
160        uint32_t mbr_ubc;
161        /** Transfer Address Member. */
162        uint32_t mbr_ta;
163} LinkedListDescriporView0;
164
165/** \brief Structure for storing parameters for DMA view1 that can be
166 * performed by the DMA Master transfer.*/
167typedef struct _LinkedListDescriporView1 {
168        /** Next Descriptor Address number. */
169        uint32_t mbr_nda;
170        /** Microblock Control Member. */
171        uint32_t mbr_ubc;
172        /** Source Address Member. */
173        uint32_t mbr_sa;
174        /** Destination Address Member. */
175        uint32_t mbr_da;
176} LinkedListDescriporView1;
177
178/** \brief Structure for storing parameters for DMA view2 that can be
179 * performed by the DMA Master transfer.*/
180typedef struct _LinkedListDescriporView2 {
181        /** Next Descriptor Address number. */
182        uint32_t mbr_nda;
183        /** Microblock Control Member. */
184        uint32_t mbr_ubc;
185        /** Source Address Member. */
186        uint32_t mbr_sa;
187        /** Destination Address Member. */
188        uint32_t mbr_da;
189        /** Configuration Register. */
190        uint32_t mbr_cfg;
191} LinkedListDescriporView2;
192
193/** \brief Structure for storing parameters for DMA view3 that can be
194 * performed by the DMA Master transfer.*/
195typedef struct _LinkedListDescriporView3 {
196        /** Next Descriptor Address number. */
197        uint32_t mbr_nda;
198        /** Microblock Control Member. */
199        uint32_t mbr_ubc;
200        /** Source Address Member. */
201        uint32_t mbr_sa;
202        /** Destination Address Member. */
203        uint32_t mbr_da;
204        /** Configuration Register. */
205        uint32_t mbr_cfg;
206        /** Block Control Member. */
207        uint32_t mbr_bc;
208        /** Data Stride Member. */
209        uint32_t mbr_ds;
210        /** Source Microblock Stride Member. */
211        uint32_t mbr_sus;
212        /** Destination Microblock Stride Member. */
213        uint32_t mbr_dus;
214} LinkedListDescriporView3;
215
216/**     @}*/
217
218extern sXdmad XDMAD_Instance;
219
220/*----------------------------------------------------------------------------
221 *        Exported functions
222 *----------------------------------------------------------------------------*/
223/** \addtogroup dmad_functions DMA Driver Functions
224        @{*/
225extern uint32_t XDMAD_AllocateChannel(sXdmad *pXdmad,
226                                                                           uint8_t bSrcID, uint8_t bDstID);
227extern eXdmadRC XDMAD_FreeChannel(sXdmad *pXdmad, uint32_t dwChannel);
228
229extern eXdmadRC XDMAD_ConfigureTransfer(sXdmad *pXdmad,
230                uint32_t dwChannel,
231                sXdmadCfg *pXdmaParam,
232                uint32_t dwXdmaDescCfg,
233                uint32_t dwXdmaDescAddr,
234                uint32_t dwXdmaIntEn);
235
236extern eXdmadRC XDMAD_PrepareChannel(sXdmad *pXdmad, uint32_t dwChannel);
237
238extern eXdmadRC XDMAD_IsTransferDone(sXdmad *pXdmad, uint32_t dwChannel);
239
240extern eXdmadRC XDMAD_StartTransfer(sXdmad *pXdmad, uint32_t dwChannel);
241
242extern void XDMAD_DoNothingCallback(uint32_t Channel, void *pArg, uint32_t status);
243
244extern eXdmadRC XDMAD_SetCallback(sXdmad *pXdmad,
245                                                                   uint32_t dwChannel,
246                                                                   XdmadTransferCallback fCallback,
247                                                                   void *pArg);
248
249extern eXdmadRC XDMAD_StopTransfer(sXdmad *pXdmad, uint32_t dwChannel);
250/**     @}*/
251/**@}*/
252#endif //#ifndef _XDMAD_H
253
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