source: rtems/bsps/arm/atsam/include/libchip/include/samv71/samv71n20.h @ 71c5552f

5
Last change on this file since 71c5552f was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 31.9 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
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10/* modification, are permitted provided that the following condition is met:    */
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12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
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15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
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22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71N20_
31#define _SAMV71N20_
32
33/** \addtogroup SAMV71N20_definitions SAMV71N20 definitions
34  This file defines all structures and symbols for SAMV71N20:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAMV71N20 */
52/* ************************************************************************** */
53/** \addtogroup SAMV71N20_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAMV71N20 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAMV71N20 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAMV71N20 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAMV71N20 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAMV71N20 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAMV71N20 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAMV71N20 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAMV71N20 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAMV71N20 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAMV71N20 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAMV71N20 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAMV71N20 Parallel I/O Controller B (PIOB) */
82  USART0_IRQn          = 13, /**< 13 SAMV71N20 USART 0 (USART0) */
83  USART1_IRQn          = 14, /**< 14 SAMV71N20 USART 1 (USART1) */
84  USART2_IRQn          = 15, /**< 15 SAMV71N20 USART 2 (USART2) */
85  PIOD_IRQn            = 16, /**< 16 SAMV71N20 Parallel I/O Controller D (PIOD) */
86  HSMCI_IRQn           = 18, /**< 18 SAMV71N20 Multimedia Card Interface (HSMCI) */
87  TWIHS0_IRQn          = 19, /**< 19 SAMV71N20 Two Wire Interface 0 HS (TWIHS0) */
88  TWIHS1_IRQn          = 20, /**< 20 SAMV71N20 Two Wire Interface 1 HS (TWIHS1) */
89  SPI0_IRQn            = 21, /**< 21 SAMV71N20 Serial Peripheral Interface 0 (SPI0) */
90  SSC_IRQn             = 22, /**< 22 SAMV71N20 Synchronous Serial Controller (SSC) */
91  TC0_IRQn             = 23, /**< 23 SAMV71N20 Timer/Counter 0 (TC0) */
92  TC1_IRQn             = 24, /**< 24 SAMV71N20 Timer/Counter 1 (TC1) */
93  TC2_IRQn             = 25, /**< 25 SAMV71N20 Timer/Counter 2 (TC2) */
94  AFEC0_IRQn           = 29, /**< 29 SAMV71N20 Analog Front End 0 (AFEC0) */
95  DACC_IRQn            = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */
96  PWM0_IRQn            = 31, /**< 31 SAMV71N20 Pulse Width Modulation 0 (PWM0) */
97  ICM_IRQn             = 32, /**< 32 SAMV71N20 Integrity Check Monitor (ICM) */
98  ACC_IRQn             = 33, /**< 33 SAMV71N20 Analog Comparator (ACC) */
99  USBHS_IRQn           = 34, /**< 34 SAMV71N20 USB Host / Device Controller (USBHS) */
100  MCAN0_IRQn           = 35, /**< 35 SAMV71N20 MCAN Controller 0 (MCAN0) */
101  MCAN1_IRQn           = 37, /**< 37 SAMV71N20 MCAN Controller 1 (MCAN1) */
102  GMAC_IRQn            = 39, /**< 39 SAMV71N20 Ethernet MAC (GMAC) */
103  AFEC1_IRQn           = 40, /**< 40 SAMV71N20 Analog Front End 1 (AFEC1) */
104  TWIHS2_IRQn          = 41, /**< 41 SAMV71N20 Two Wire Interface 2 HS (TWIHS2) */
105  SPI1_IRQn            = 42, /**< 42 SAMV71N20 Serial Peripheral Interface 1 (SPI1) */
106  QSPI_IRQn            = 43, /**< 43 SAMV71N20 Quad I/O Serial Peripheral Interface (QSPI) */
107  UART2_IRQn           = 44, /**< 44 SAMV71N20 UART 2 (UART2) */
108  UART3_IRQn           = 45, /**< 45 SAMV71N20 UART 3 (UART3) */
109  UART4_IRQn           = 46, /**< 46 SAMV71N20 UART 4 (UART4) */
110  TC9_IRQn             = 50, /**< 50 SAMV71N20 Timer/Counter 9 (TC9) */
111  TC10_IRQn            = 51, /**< 51 SAMV71N20 Timer/Counter 10 (TC10) */
112  TC11_IRQn            = 52, /**< 52 SAMV71N20 Timer/Counter 11 (TC11) */
113  MLB_IRQn             = 53, /**< 53 SAMV71N20 MediaLB (MLB) */
114  AES_IRQn             = 56, /**< 56 SAMV71N20 AES (AES) */
115  TRNG_IRQn            = 57, /**< 57 SAMV71N20 True Random Generator (TRNG) */
116  XDMAC_IRQn           = 58, /**< 58 SAMV71N20 DMA (XDMAC) */
117  ISI_IRQn             = 59, /**< 59 SAMV71N20 Camera Interface (ISI) */
118  PWM1_IRQn            = 60, /**< 60 SAMV71N20 Pulse Width Modulation 1 (PWM1) */
119  RSWDT_IRQn           = 63, /**< 63 SAMV71N20 Reinforced Secure Watchdog Timer (RSWDT) */
120
121  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
122} IRQn_Type;
123
124typedef struct _DeviceVectors
125{
126  /* Stack pointer */
127  void* pvStack;
128
129  /* Cortex-M handlers */
130  void* pfnReset_Handler;
131  void* pfnNMI_Handler;
132  void* pfnHardFault_Handler;
133  void* pfnMemManage_Handler;
134  void* pfnBusFault_Handler;
135  void* pfnUsageFault_Handler;
136  void* pfnReserved1_Handler;
137  void* pfnReserved2_Handler;
138  void* pfnReserved3_Handler;
139  void* pfnReserved4_Handler;
140  void* pfnSVC_Handler;
141  void* pfnDebugMon_Handler;
142  void* pfnReserved5_Handler;
143  void* pfnPendSV_Handler;
144  void* pfnSysTick_Handler;
145
146  /* Peripheral handlers */
147  void* pfnSUPC_Handler;   /*  0 Supply Controller */
148  void* pfnRSTC_Handler;   /*  1 Reset Controller */
149  void* pfnRTC_Handler;    /*  2 Real Time Clock */
150  void* pfnRTT_Handler;    /*  3 Real Time Timer */
151  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
152  void* pfnPMC_Handler;    /*  5 Power Management Controller */
153  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
154  void* pfnUART0_Handler;  /*  7 UART 0 */
155  void* pfnUART1_Handler;  /*  8 UART 1 */
156  void* pvReserved9;
157  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
158  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
159  void* pvReserved12;
160  void* pfnUSART0_Handler; /* 13 USART 0 */
161  void* pfnUSART1_Handler; /* 14 USART 1 */
162  void* pfnUSART2_Handler; /* 15 USART 2 */
163  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
164  void* pvReserved17;
165  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
166  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
167  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
168  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
169  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
170  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
171  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
172  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
173  void* pvReserved26;
174  void* pvReserved27;
175  void* pvReserved28;
176  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
177  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
178  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
179  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
180  void* pfnACC_Handler;    /* 33 Analog Comparator */
181  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
182  void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
183  void* pvReserved36;
184  void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
185  void* pvReserved38;
186  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
187  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
188  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
189  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
190  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
191  void* pfnUART2_Handler;  /* 44 UART 2 */
192  void* pfnUART3_Handler;  /* 45 UART 3 */
193  void* pfnUART4_Handler;  /* 46 UART 4 */
194  void* pvReserved47;
195  void* pvReserved48;
196  void* pvReserved49;
197  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
198  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
199  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
200  void* pfnMLB_Handler;    /* 53 MediaLB */
201  void* pvReserved54;
202  void* pvReserved55;
203  void* pfnAES_Handler;    /* 56 AES */
204  void* pfnTRNG_Handler;   /* 57 True Random Generator */
205  void* pfnXDMAC_Handler;  /* 58 DMA */
206  void* pfnISI_Handler;    /* 59 Camera Interface */
207  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
208  void* pvReserved61;
209  void* pvReserved62;
210  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
211} DeviceVectors;
212
213/* Cortex-M7 core handlers */
214void Reset_Handler      ( void );
215void NMI_Handler        ( void );
216void HardFault_Handler  ( void );
217void MemManage_Handler  ( void );
218void BusFault_Handler   ( void );
219void UsageFault_Handler ( void );
220void SVC_Handler        ( void );
221void DebugMon_Handler   ( void );
222void PendSV_Handler     ( void );
223void SysTick_Handler    ( void );
224
225/* Peripherals handlers */
226void ACC_Handler        ( void );
227void AES_Handler        ( void );
228void AFEC0_Handler      ( void );
229void AFEC1_Handler      ( void );
230void DACC_Handler       ( void );
231void EFC_Handler        ( void );
232void GMAC_Handler       ( void );
233void HSMCI_Handler      ( void );
234void ICM_Handler        ( void );
235void ISI_Handler        ( void );
236void MCAN0_Handler      ( void );
237void MCAN1_Handler      ( void );
238void MLB_Handler        ( void );
239void PIOA_Handler       ( void );
240void PIOB_Handler       ( void );
241void PIOD_Handler       ( void );
242void PMC_Handler        ( void );
243void PWM0_Handler       ( void );
244void PWM1_Handler       ( void );
245void QSPI_Handler       ( void );
246void RSTC_Handler       ( void );
247void RSWDT_Handler      ( void );
248void RTC_Handler        ( void );
249void RTT_Handler        ( void );
250void SPI0_Handler       ( void );
251void SPI1_Handler       ( void );
252void SSC_Handler        ( void );
253void SUPC_Handler       ( void );
254void TC0_Handler        ( void );
255void TC1_Handler        ( void );
256void TC2_Handler        ( void );
257void TC9_Handler        ( void );
258void TC10_Handler       ( void );
259void TC11_Handler       ( void );
260void TRNG_Handler       ( void );
261void TWIHS0_Handler     ( void );
262void TWIHS1_Handler     ( void );
263void TWIHS2_Handler     ( void );
264void UART0_Handler      ( void );
265void UART1_Handler      ( void );
266void UART2_Handler      ( void );
267void UART3_Handler      ( void );
268void UART4_Handler      ( void );
269void USART0_Handler     ( void );
270void USART1_Handler     ( void );
271void USART2_Handler     ( void );
272void USBHS_Handler      ( void );
273void WDT_Handler        ( void );
274void XDMAC_Handler      ( void );
275
276/**
277 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
278 */
279
280#define __CM7_REV              0x0000 /**< SAMV71N20 core revision number ([15:8] revision number, [7:0] patch number) */
281#define __MPU_PRESENT          1      /**< SAMV71N20 does provide a MPU */
282#define __NVIC_PRIO_BITS       3      /**< SAMV71N20 uses 3 Bits for the Priority Levels */
283#define __FPU_PRESENT          1      /**< SAMV71N20 does provide a FPU                */
284#define __FPU_DP               1      /**< SAMV71N20 Double precision FPU              */
285#define __ICACHE_PRESENT       1      /**< SAMV71N20 does provide an Instruction Cache */
286#define __DCACHE_PRESENT       1      /**< SAMV71N20 does provide a Data Cache         */
287#define __DTCM_PRESENT         1      /**< SAMV71N20 does provide a Data TCM           */
288#define __ITCM_PRESENT         1      /**< SAMV71N20 does provide an Instruction TCM   */
289#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
290
291/*
292 * \brief CMSIS includes
293 */
294
295#include <core_cm7.h>
296#if !defined DONT_USE_CMSIS_INIT
297#include "system_samv71.h"
298#endif /* DONT_USE_CMSIS_INIT */
299
300/*@}*/
301
302/* ************************************************************************** */
303/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N20 */
304/* ************************************************************************** */
305/** \addtogroup SAMV71N20_api Peripheral Software API */
306/*@{*/
307
308#include "component/component_acc.h"
309#include "component/component_aes.h"
310#include "component/component_afec.h"
311#include "component/component_chipid.h"
312#include "component/component_dacc.h"
313#include "component/component_efc.h"
314#include "component/component_gmac.h"
315#include "component/component_gpbr.h"
316#include "component/component_hsmci.h"
317#include "component/component_icm.h"
318#include "component/component_isi.h"
319#include "component/component_matrix.h"
320#include "component/component_mcan.h"
321#include "component/component_mlb.h"
322#include "component/component_pio.h"
323#include "component/component_pmc.h"
324#include "component/component_pwm.h"
325#include "component/component_qspi.h"
326#include "component/component_rstc.h"
327#include "component/component_rswdt.h"
328#include "component/component_rtc.h"
329#include "component/component_rtt.h"
330#include "component/component_spi.h"
331#include "component/component_ssc.h"
332#include "component/component_supc.h"
333#include "component/component_tc.h"
334#include "component/component_trng.h"
335#include "component/component_twihs.h"
336#include "component/component_uart.h"
337#include "component/component_usart.h"
338#include "component/component_usbhs.h"
339#include "component/component_utmi.h"
340#include "component/component_wdt.h"
341#include "component/component_xdmac.h"
342/*@}*/
343
344#ifndef __rtems__
345/* ************************************************************************** */
346/*   REGISTER ACCESS DEFINITIONS FOR SAMV71N20 */
347/* ************************************************************************** */
348/** \addtogroup SAMV71N20_reg Registers Access Definitions */
349/*@{*/
350
351#include "instance/instance_hsmci.h"
352#include "instance/instance_ssc.h"
353#include "instance/instance_spi0.h"
354#include "instance/instance_tc0.h"
355#include "instance/instance_twihs0.h"
356#include "instance/instance_twihs1.h"
357#include "instance/instance_pwm0.h"
358#include "instance/instance_usart0.h"
359#include "instance/instance_usart1.h"
360#include "instance/instance_usart2.h"
361#include "instance/instance_mcan0.h"
362#include "instance/instance_mcan1.h"
363#include "instance/instance_usbhs.h"
364#include "instance/instance_afec0.h"
365#include "instance/instance_dacc.h"
366#include "instance/instance_acc.h"
367#include "instance/instance_icm.h"
368#include "instance/instance_isi.h"
369#include "instance/instance_gmac.h"
370#include "instance/instance_tc3.h"
371#include "instance/instance_spi1.h"
372#include "instance/instance_pwm1.h"
373#include "instance/instance_twihs2.h"
374#include "instance/instance_afec1.h"
375#include "instance/instance_mlb.h"
376#include "instance/instance_aes.h"
377#include "instance/instance_trng.h"
378#include "instance/instance_xdmac.h"
379#include "instance/instance_qspi.h"
380#include "instance/instance_matrix.h"
381#include "instance/instance_utmi.h"
382#include "instance/instance_pmc.h"
383#include "instance/instance_uart0.h"
384#include "instance/instance_chipid.h"
385#include "instance/instance_uart1.h"
386#include "instance/instance_efc.h"
387#include "instance/instance_pioa.h"
388#include "instance/instance_piob.h"
389#include "instance/instance_piod.h"
390#include "instance/instance_rstc.h"
391#include "instance/instance_supc.h"
392#include "instance/instance_rtt.h"
393#include "instance/instance_wdt.h"
394#include "instance/instance_rtc.h"
395#include "instance/instance_gpbr.h"
396#include "instance/instance_rswdt.h"
397#include "instance/instance_uart2.h"
398#include "instance/instance_uart3.h"
399#include "instance/instance_uart4.h"
400/*@}*/
401#endif /* __rtems__ */
402
403/* ************************************************************************** */
404/*   PERIPHERAL ID DEFINITIONS FOR SAMV71N20 */
405/* ************************************************************************** */
406/** \addtogroup SAMV71N20_id Peripheral Ids Definitions */
407/*@{*/
408
409#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
410#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
411#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
412#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
413#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
414#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
415#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
416#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
417#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
418#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
419#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
420#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
421#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
422#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
423#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
424#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
425#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
426#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
427#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
428#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
429#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
430#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
431#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
432#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
433#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
434#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
435#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
436#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
437#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
438#define ID_MCAN0  (35) /**< \brief MCAN Controller 0 (MCAN0) */
439#define ID_MCAN1  (37) /**< \brief MCAN Controller 1 (MCAN1) */
440#define ID_GMAC   (39) /**< \brief Ethernet MAC (GMAC) */
441#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
442#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
443#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
444#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
445#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
446#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
447#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
448#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
449#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
450#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
451#define ID_MLB    (53) /**< \brief MediaLB (MLB) */
452#define ID_AES    (56) /**< \brief AES (AES) */
453#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
454#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
455#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
456#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
457#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
458
459#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
460/*@}*/
461
462/* ************************************************************************** */
463/*   BASE ADDRESS DEFINITIONS FOR SAMV71N20 */
464/* ************************************************************************** */
465/** \addtogroup SAMV71N20_base Peripheral Base Address Definitions */
466/*@{*/
467
468#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
469#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
470#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
471#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
472#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
473#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
474#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
475#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
476#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
477#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
478#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
479#define MCAN0  (0x40030000U) /**< \brief (MCAN0 ) Base Address */
480#define MCAN1  (0x40034000U) /**< \brief (MCAN1 ) Base Address */
481#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
482#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
483#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
484#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
485#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
486#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
487#define GMAC   (0x40050000U) /**< \brief (GMAC  ) Base Address */
488#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
489#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
490#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
491#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
492#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
493#define MLB    (0x40068000U) /**< \brief (MLB   ) Base Address */
494#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
495#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
496#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
497#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
498#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
499#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
500#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
501#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
502#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
503#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
504#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
505#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
506#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
507#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
508#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
509#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
510#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
511#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
512#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
513#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
514#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
515#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
516#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
517#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
518#else
519#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
520#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
521#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
522#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
523#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
524#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
525#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
526#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
527#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
528#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
529#define MCAN0  ((Mcan   *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
530#define MCAN1  ((Mcan   *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
531#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
532#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
533#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
534#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
535#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
536#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
537#define GMAC   ((Gmac   *)0x40050000U) /**< \brief (GMAC  ) Base Address */
538#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
539#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
540#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
541#define TWIHS2 ((Twihs  *)0x40060000U) /**< \brief (TWIHS2) Base Address */
542#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
543#define MLB    ((Mlb    *)0x40068000U) /**< \brief (MLB   ) Base Address */
544#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
545#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
546#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
547#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
548#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
549#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
550#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
551#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
552#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
553#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
554#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
555#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
556#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
557#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
558#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
559#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
560#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
561#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
562#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
563#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
564#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
565#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
566#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
567#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
568#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
569/*@}*/
570
571/* ************************************************************************** */
572/*   PIO DEFINITIONS FOR SAMV71N20 */
573/* ************************************************************************** */
574/** \addtogroup SAMV71N20_pio Peripheral Pio Definitions */
575/*@{*/
576
577#include "pio/pio_samv71n20.h"
578/*@}*/
579
580/* ************************************************************************** */
581/*   MEMORY MAPPING DEFINITIONS FOR SAMV71N20 */
582/* ************************************************************************** */
583
584#define IFLASH_SIZE             (0x100000u)
585#define IFLASH_PAGE_SIZE        (512u)
586#define IFLASH_LOCK_REGION_SIZE (8192u)
587#define IFLASH_NB_OF_PAGES      (2048u)
588#define IFLASH_NB_OF_LOCK_BITS  (64u)
589#define IRAM_SIZE               (0x60000u)
590
591#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
592#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
593#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
594#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
595#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
596#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
597#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
598#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
599#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
600#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
601#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
602#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
603
604/* ************************************************************************** */
605/*   MISCELLANEOUS DEFINITIONS FOR SAMV71N20 */
606/* ************************************************************************** */
607
608#define CHIP_JTAGID (0x05B3D03FUL)
609#define CHIP_CIDR   (0xA1220C00UL)
610#define CHIP_EXID   (0x00000001UL)
611
612/* ************************************************************************** */
613/*   ELECTRICAL DEFINITIONS FOR SAMV71N20 */
614/* ************************************************************************** */
615
616/* %ATMEL_ELECTRICAL% */
617
618/* Device characteristics */
619#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
620#define CHIP_FREQ_SLCK_RC               (32000UL)
621#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
622#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
623#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
624#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
625#define CHIP_FREQ_CPU_MAX               (120000000UL)
626#define CHIP_FREQ_XTAL_32K              (32768UL)
627#define CHIP_FREQ_XTAL_12M              (12000000UL)
628
629/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
630#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
631#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
632#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
633#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
634#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
635#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
636
637#ifdef __cplusplus
638}
639#endif
640
641/*@}*/
642
643#endif /* _SAMV71N20_ */
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