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component_mcan.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 78.2 KB

Line
1	/* ---------------------------------------------------------------------------- */
2	/* Atmel Microcontroller Software Support */
3	/* SAM Software Package License */
4	/* ---------------------------------------------------------------------------- */
5	/* Copyright (c) 2015, Atmel Corporation */
6	/* */
7	/* All rights reserved. */
8	/* */
9	/* Redistribution and use in source and binary forms, with or without */
10	/* modification, are permitted provided that the following condition is met: */
11	/* */
12	/* - Redistributions of source code must retain the above copyright notice, */
13	/* this list of conditions and the disclaimer below. */
14	/* */
15	/* Atmel's name may not be used to endorse or promote products derived from */
16	/* this software without specific prior written permission. */
17	/* */
18	/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19	/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20	/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21	/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22	/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23	/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24	/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25	/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26	/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27	/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28	/* ---------------------------------------------------------------------------- */
29
30	#ifndef _SAMV71_MCAN_COMPONENT_
31	#define _SAMV71_MCAN_COMPONENT_
32
33	/* ============================================================================= */
34	/** SOFTWARE API DEFINITION FOR Controller Area Network */
35	/* ============================================================================= */
36	/** \addtogroup SAMV71_MCAN Controller Area Network */
37	/@{/
38
39	#if !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
40	/** \brief Mcan hardware registers */
41	typedef struct {
42	__I uint32_t MCAN_CREL; /*< \brief (Mcan Offset: 0x00) Core Release Register /
43	__I uint32_t MCAN_ENDN; /*< \brief (Mcan Offset: 0x04) Endian Register /
44	__IO uint32_t MCAN_CUST; /*< \brief (Mcan Offset: 0x08) Customer Register /
45	__IO uint32_t MCAN_FBTP; /*< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register /
46	__IO uint32_t MCAN_TEST; /*< \brief (Mcan Offset: 0x10) Test Register /
47	__IO uint32_t MCAN_RWD; /*< \brief (Mcan Offset: 0x14) RAM Watchdog Register /
48	__IO uint32_t MCAN_CCCR; /*< \brief (Mcan Offset: 0x18) CC Control Register /
49	__IO uint32_t MCAN_BTP; /*< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register /
50	__IO uint32_t MCAN_TSCC; /*< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register /
51	__IO uint32_t MCAN_TSCV; /*< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register /
52	__IO uint32_t MCAN_TOCC; /*< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register /
53	__IO uint32_t MCAN_TOCV; /*< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register /
54	__I uint32_t Reserved1[4];
55	__I uint32_t MCAN_ECR; /*< \brief (Mcan Offset: 0x40) Error Counter Register /
56	__I uint32_t MCAN_PSR; /*< \brief (Mcan Offset: 0x44) Protocol Status Register /
57	__I uint32_t Reserved2[2];
58	__IO uint32_t MCAN_IR; /*< \brief (Mcan Offset: 0x50) Interrupt Register /
59	__IO uint32_t MCAN_IE; /*< \brief (Mcan Offset: 0x54) Interrupt Enable Register /
60	__IO uint32_t MCAN_ILS; /*< \brief (Mcan Offset: 0x58) Interrupt Line Select Register /
61	__IO uint32_t MCAN_ILE; /*< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register /
62	__I uint32_t Reserved3[8];
63	__IO uint32_t MCAN_GFC; /*< \brief (Mcan Offset: 0x80) Global Filter Configuration Register /
64	__IO uint32_t MCAN_SIDFC; /*< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register /
65	__IO uint32_t MCAN_XIDFC; /*< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register /
66	__I uint32_t Reserved4[1];
67	__IO uint32_t MCAN_XIDAM; /*< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register /
68	__I uint32_t MCAN_HPMS; /*< \brief (Mcan Offset: 0x94) High Priority Message Status Register /
69	__IO uint32_t MCAN_NDAT1; /*< \brief (Mcan Offset: 0x98) New Data 1 Register /
70	__IO uint32_t MCAN_NDAT2; /*< \brief (Mcan Offset: 0x9C) New Data 2 Register /
71	__IO uint32_t MCAN_RXF0C; /*< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register /
72	__I uint32_t MCAN_RXF0S; /*< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register /
73	__IO uint32_t MCAN_RXF0A; /*< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register /
74	__IO uint32_t MCAN_RXBC; /*< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register /
75	__IO uint32_t MCAN_RXF1C; /*< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register /
76	__I uint32_t MCAN_RXF1S; /*< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register /
77	__IO uint32_t MCAN_RXF1A; /*< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register /
78	__IO uint32_t MCAN_RXESC; /*< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register /
79	__IO uint32_t MCAN_TXBC; /*< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register /
80	__I uint32_t MCAN_TXFQS; /*< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register /
81	__IO uint32_t MCAN_TXESC; /*< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register /
82	__I uint32_t MCAN_TXBRP; /*< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register /
83	__IO uint32_t MCAN_TXBAR; /*< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register /
84	__IO uint32_t MCAN_TXBCR; /*< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register /
85	__I uint32_t MCAN_TXBTO; /*< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register /
86	__I uint32_t MCAN_TXBCF; /*< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register /
87	__IO uint32_t MCAN_TXBTIE; /*< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register /
88	__IO uint32_t MCAN_TXBCIE; /*< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register /
89	__I uint32_t Reserved5[2];
90	__IO uint32_t MCAN_TXEFC; /*< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register /
91	__I uint32_t MCAN_TXEFS; /*< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register /
92	__IO uint32_t MCAN_TXEFA; /*< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register /
93	} Mcan;
94	#endif /* !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)) */
95	/* -------- MCAN_CREL : (MCAN Offset: 0x00) Core Release Register -------- */
96	#define MCAN_CREL_DAY_Pos 0
97	#define MCAN_CREL_DAY_Msk (0xffu << MCAN_CREL_DAY_Pos) /*< \brief (MCAN_CREL) Timestamp Day /
98	#define MCAN_CREL_MON_Pos 8
99	#define MCAN_CREL_MON_Msk (0xffu << MCAN_CREL_MON_Pos) /*< \brief (MCAN_CREL) Timestamp Month /
100	#define MCAN_CREL_YEAR_Pos 16
101	#define MCAN_CREL_YEAR_Msk (0xfu << MCAN_CREL_YEAR_Pos) /*< \brief (MCAN_CREL) Timestamp Year /
102	#define MCAN_CREL_SUBSTEP_Pos 20
103	#define MCAN_CREL_SUBSTEP_Msk (0xfu << MCAN_CREL_SUBSTEP_Pos) /*< \brief (MCAN_CREL) Sub-step of Core Release /
104	#define MCAN_CREL_STEP_Pos 24
105	#define MCAN_CREL_STEP_Msk (0xfu << MCAN_CREL_STEP_Pos) /*< \brief (MCAN_CREL) Step of Core Release /
106	#define MCAN_CREL_REL_Pos 28
107	#define MCAN_CREL_REL_Msk (0xfu << MCAN_CREL_REL_Pos) /*< \brief (MCAN_CREL) Core Release /
108	/* -------- MCAN_ENDN : (MCAN Offset: 0x04) Endian Register -------- */
109	#define MCAN_ENDN_ETV_Pos 0
110	#define MCAN_ENDN_ETV_Msk (0xffffffffu << MCAN_ENDN_ETV_Pos) /*< \brief (MCAN_ENDN) Endianness Test Value /
111	/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */
112	#define MCAN_CUST_CSV_Pos 0
113	#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /*< \brief (MCAN_CUST) Customer-specific Value /
114	#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)))
115	/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */
116	#define MCAN_FBTP_FSJW_Pos 0
117	#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /*< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width /
118	#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)))
119	#define MCAN_FBTP_FTSEG2_Pos 4
120	#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /*< \brief (MCAN_FBTP) Fast Time Segment After Sample Point /
121	#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)))
122	#define MCAN_FBTP_FTSEG1_Pos 8
123	#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /*< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point /
124	#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)))
125	#define MCAN_FBTP_FBRP_Pos 16
126	#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /*< \brief (MCAN_FBTP) Fast Baud Rate Prescaler /
127	#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos)))
128	#define MCAN_FBTP_TDC (0x1u << 23) /*< \brief (MCAN_FBTP) Transceiver Delay Compensation /
129	#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /*< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. /
130	#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /*< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. /
131	#define MCAN_FBTP_TDCO_Pos 24
132	#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /*< \brief (MCAN_FBTP) Transceiver Delay Compensation Offset /
133	#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos)))
134	/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */
135	#define MCAN_TEST_LBCK (0x1u << 4) /*< \brief (MCAN_TEST) Loop Back Mode (read/write) /
136	#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /*< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. /
137	#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /*< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). /
138	#define MCAN_TEST_TX_Pos 5
139	#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /*< \brief (MCAN_TEST) Control of Transmit Pin (read/write) /
140	#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)))
141	#define MCAN_TEST_TX_RESET (0x0u << 5) /*< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. /
142	#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /*< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. /
143	#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /*< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. /
144	#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /*< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. /
145	#define MCAN_TEST_RX (0x1u << 7) /*< \brief (MCAN_TEST) Receive Pin (read-only) /
146	#define MCAN_TEST_TDCV_Pos 8
147	#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /*< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) /
148	#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos)))
149	/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */
150	#define MCAN_RWD_WDC_Pos 0
151	#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /*< \brief (MCAN_RWD) Watchdog Configuration (read/write) /
152	#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)))
153	#define MCAN_RWD_WDV_Pos 8
154	#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /*< \brief (MCAN_RWD) Watchdog Value (read-only) /
155	#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)))
156	/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */
157	#define MCAN_CCCR_INIT (0x1u << 0) /*< \brief (MCAN_CCCR) Initialization (read/write) /
158	#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /*< \brief (MCAN_CCCR) Normal operation. /
159	#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /*< \brief (MCAN_CCCR) Initialization is started. /
160	#define MCAN_CCCR_CCE (0x1u << 1) /*< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) /
161	#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /*< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. /
162	#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /*< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). /
163	#define MCAN_CCCR_ASM (0x1u << 2) /*< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') /
164	#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /*< \brief (MCAN_CCCR) Normal CAN operation. /
165	#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /*< \brief (MCAN_CCCR) Restricted operation mode active. /
166	#define MCAN_CCCR_CSA (0x1u << 3) /*< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) /
167	#define MCAN_CCCR_CSR (0x1u << 4) /*< \brief (MCAN_CCCR) Clock Stop Request (read/write) /
168	#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /*< \brief (MCAN_CCCR) No clock stop is requested. /
169	#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /*< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. /
170	#define MCAN_CCCR_MON (0x1u << 5) /*< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') /
171	#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /*< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. /
172	#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /*< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. /
173	#define MCAN_CCCR_DAR (0x1u << 6) /*< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) /
174	#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /*< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. /
175	#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /*< \brief (MCAN_CCCR) Automatic retransmission disabled. /
176	#define MCAN_CCCR_TEST (0x1u << 7) /*< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') /
177	#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /*< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. /
178	#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /*< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. /
179	#define MCAN_CCCR_CME_Pos 8
180	#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /*< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) /
181	#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)))
182	#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /*< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled /
183	#define MCAN_CCCR_CME_FD (0x1u << 8) /*< \brief (MCAN_CCCR) CAN FD operation enabled /
184	#define MCAN_CCCR_CMR_Pos 10
185	#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /*< \brief (MCAN_CCCR) CAN Mode Request (read/write) /
186	#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos)))
187	#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /*< \brief (MCAN_CCCR) No mode change /
188	#define MCAN_CCCR_CMR_FD (0x1u << 10) /*< \brief (MCAN_CCCR) Request CAN FD operation /
189	#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /*< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching /
190	#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /*< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 /
191	#define MCAN_CCCR_FDO (0x1u << 12) /*< \brief (MCAN_CCCR) CAN FD Operation (read-only) /
192	#define MCAN_CCCR_FDBS (0x1u << 13) /*< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) /
193	#define MCAN_CCCR_TXP (0x1u << 14) /*< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) /
194	/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */
195	#define MCAN_BTP_SJW_Pos 0
196	#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /*< \brief (MCAN_BTP) (Re) Synchronization Jump Width /
197	#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)))
198	#define MCAN_BTP_TSEG2_Pos 4
199	#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /*< \brief (MCAN_BTP) Time Segment After Sample Point /
200	#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)))
201	#define MCAN_BTP_TSEG1_Pos 8
202	#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /*< \brief (MCAN_BTP) Time Segment Before Sample Point /
203	#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)))
204	#define MCAN_BTP_BRP_Pos 16
205	#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /*< \brief (MCAN_BTP) Baud Rate Prescaler /
206	#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)))
207	/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */
208	#define MCAN_TSCC_TSS_Pos 0
209	#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /*< \brief (MCAN_TSCC) Timestamp Select /
210	#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)))
211	#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /*< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 /
212	#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /*< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP /
213	#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /*< \brief (MCAN_TSCC) External timestamp counter value used /
214	#define MCAN_TSCC_TCP_Pos 16
215	#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /*< \brief (MCAN_TSCC) Timestamp Counter Prescaler /
216	#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)))
217	/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */
218	#define MCAN_TSCV_TSC_Pos 0
219	#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /*< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) /
220	#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)))
221	/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */
222	#define MCAN_TOCC_ETOC (0x1u << 0) /*< \brief (MCAN_TOCC) Enable Timeout Counter /
223	#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /*< \brief (MCAN_TOCC) Timeout Counter disabled. /
224	#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /*< \brief (MCAN_TOCC) Timeout Counter enabled. /
225	#define MCAN_TOCC_TOS_Pos 1
226	#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /*< \brief (MCAN_TOCC) Timeout Select /
227	#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)))
228	#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /*< \brief (MCAN_TOCC) Continuous operation /
229	#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /*< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO /
230	#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /*< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 /
231	#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /*< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 /
232	#define MCAN_TOCC_TOP_Pos 16
233	#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /*< \brief (MCAN_TOCC) Timeout Period /
234	#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)))
235	/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */
236	#define MCAN_TOCV_TOC_Pos 0
237	#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /*< \brief (MCAN_TOCV) Timeout Counter (cleared on write) /
238	#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)))
239	/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */
240	#define MCAN_ECR_TEC_Pos 0
241	#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /*< \brief (MCAN_ECR) Transmit Error Counter /
242	#define MCAN_ECR_REC_Pos 8
243	#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /*< \brief (MCAN_ECR) Receive Error Counter /
244	#define MCAN_ECR_RP (0x1u << 15) /*< \brief (MCAN_ECR) Receive Error Passive /
245	#define MCAN_ECR_CEL_Pos 16
246	#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /*< \brief (MCAN_ECR) CAN Error Logging (cleared on read) /
247	/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */
248	#define MCAN_PSR_LEC_Pos 0
249	#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /*< \brief (MCAN_PSR) Last Error Code (set to 111 on read) /
250	#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /*< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. /
251	#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /*< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. /
252	#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /*< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. /
253	#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /*< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. /
254	#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /*< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. /
255	#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /*< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). /
256	#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /*< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. /
257	#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /*< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. /
258	#define MCAN_PSR_ACT_Pos 3
259	#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /*< \brief (MCAN_PSR) Activity /
260	#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /*< \brief (MCAN_PSR) Node is synchronizing on CAN communication /
261	#define MCAN_PSR_ACT_IDLE (0x1u << 3) /*< \brief (MCAN_PSR) Node is neither receiver nor transmitter /
262	#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /*< \brief (MCAN_PSR) Node is operating as receiver /
263	#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /*< \brief (MCAN_PSR) Node is operating as transmitter /
264	#define MCAN_PSR_EP (0x1u << 5) /*< \brief (MCAN_PSR) Error Passive /
265	#define MCAN_PSR_EW (0x1u << 6) /*< \brief (MCAN_PSR) Warning Status /
266	#define MCAN_PSR_BO (0x1u << 7) /*< \brief (MCAN_PSR) Bus_Off Status /
267	#define MCAN_PSR_FLEC_Pos 8
268	#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /*< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) /
269	#define MCAN_PSR_RESI (0x1u << 11) /*< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) /
270	#define MCAN_PSR_RBRS (0x1u << 12) /*< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) /
271	#define MCAN_PSR_REDL (0x1u << 13) /*< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) /
272	/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */
273	#define MCAN_IR_RF0N (0x1u << 0) /*< \brief (MCAN_IR) Receive FIFO 0 New Message /
274	#define MCAN_IR_RF0W (0x1u << 1) /*< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached /
275	#define MCAN_IR_RF0F (0x1u << 2) /*< \brief (MCAN_IR) Receive FIFO 0 Full /
276	#define MCAN_IR_RF0L (0x1u << 3) /*< \brief (MCAN_IR) Receive FIFO 0 Message Lost /
277	#define MCAN_IR_RF1N (0x1u << 4) /*< \brief (MCAN_IR) Receive FIFO 1 New Message /
278	#define MCAN_IR_RF1W (0x1u << 5) /*< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached /
279	#define MCAN_IR_RF1F (0x1u << 6) /*< \brief (MCAN_IR) Receive FIFO 1 Full /
280	#define MCAN_IR_RF1L (0x1u << 7) /*< \brief (MCAN_IR) Receive FIFO 1 Message Lost /
281	#define MCAN_IR_HPM (0x1u << 8) /*< \brief (MCAN_IR) High Priority Message /
282	#define MCAN_IR_TC (0x1u << 9) /*< \brief (MCAN_IR) Transmission Completed /
283	#define MCAN_IR_TCF (0x1u << 10) /*< \brief (MCAN_IR) Transmission Cancellation Finished /
284	#define MCAN_IR_TFE (0x1u << 11) /*< \brief (MCAN_IR) Tx FIFO Empty /
285	#define MCAN_IR_TEFN (0x1u << 12) /*< \brief (MCAN_IR) Tx Event FIFO New Entry /
286	#define MCAN_IR_TEFW (0x1u << 13) /*< \brief (MCAN_IR) Tx Event FIFO Watermark Reached /
287	#define MCAN_IR_TEFF (0x1u << 14) /*< \brief (MCAN_IR) Tx Event FIFO Full /
288	#define MCAN_IR_TEFL (0x1u << 15) /*< \brief (MCAN_IR) Tx Event FIFO Element Lost /
289	#define MCAN_IR_TSW (0x1u << 16) /*< \brief (MCAN_IR) Timestamp Wraparound /
290	#define MCAN_IR_MRAF (0x1u << 17) /*< \brief (MCAN_IR) Message RAM Access Failure /
291	#define MCAN_IR_TOO (0x1u << 18) /*< \brief (MCAN_IR) Timeout Occurred /
292	#define MCAN_IR_DRX (0x1u << 19) /*< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer /
293	#define MCAN_IR_BEC (0x1u << 20) /*< \brief (MCAN_IR) Bit Error Corrected /
294	#define MCAN_IR_BEU (0x1u << 21) /*< \brief (MCAN_IR) Bit Error Uncorrected /
295	#define MCAN_IR_ELO (0x1u << 22) /*< \brief (MCAN_IR) Error Logging Overflow /
296	#define MCAN_IR_EP (0x1u << 23) /*< \brief (MCAN_IR) Error Passive /
297	#define MCAN_IR_EW (0x1u << 24) /*< \brief (MCAN_IR) Warning Status /
298	#define MCAN_IR_BO (0x1u << 25) /*< \brief (MCAN_IR) Bus_Off Status /
299	#define MCAN_IR_WDI (0x1u << 26) /*< \brief (MCAN_IR) Watchdog Interrupt /
300	#define MCAN_IR_CRCE (0x1u << 27) /*< \brief (MCAN_IR) CRC Error /
301	#define MCAN_IR_BE (0x1u << 28) /*< \brief (MCAN_IR) Bit Error /
302	#define MCAN_IR_ACKE (0x1u << 29) /*< \brief (MCAN_IR) Acknowledge Error /
303	#define MCAN_IR_FOE (0x1u << 30) /*< \brief (MCAN_IR) Format Error /
304	#define MCAN_IR_STE (0x1u << 31) /*< \brief (MCAN_IR) Stuff Error /
305	/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */
306	#define MCAN_IE_RF0NE (0x1u << 0) /*< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable /
307	#define MCAN_IE_RF0WE (0x1u << 1) /*< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable /
308	#define MCAN_IE_RF0FE (0x1u << 2) /*< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable /
309	#define MCAN_IE_RF0LE (0x1u << 3) /*< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable /
310	#define MCAN_IE_RF1NE (0x1u << 4) /*< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable /
311	#define MCAN_IE_RF1WE (0x1u << 5) /*< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable /
312	#define MCAN_IE_RF1FE (0x1u << 6) /*< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable /
313	#define MCAN_IE_RF1LE (0x1u << 7) /*< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable /
314	#define MCAN_IE_HPME (0x1u << 8) /*< \brief (MCAN_IE) High Priority Message Interrupt Enable /
315	#define MCAN_IE_TCE (0x1u << 9) /*< \brief (MCAN_IE) Transmission Completed Interrupt Enable /
316	#define MCAN_IE_TCFE (0x1u << 10) /*< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable /
317	#define MCAN_IE_TFEE (0x1u << 11) /*< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable /
318	#define MCAN_IE_TEFNE (0x1u << 12) /*< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable /
319	#define MCAN_IE_TEFWE (0x1u << 13) /*< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable /
320	#define MCAN_IE_TEFFE (0x1u << 14) /*< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable /
321	#define MCAN_IE_TEFLE (0x1u << 15) /*< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable /
322	#define MCAN_IE_TSWE (0x1u << 16) /*< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable /
323	#define MCAN_IE_MRAFE (0x1u << 17) /*< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable /
324	#define MCAN_IE_TOOE (0x1u << 18) /*< \brief (MCAN_IE) Timeout Occurred Interrupt Enable /
325	#define MCAN_IE_DRXE (0x1u << 19) /*< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable /
326	#define MCAN_IE_BECE (0x1u << 20) /*< \brief (MCAN_IE) Bit Error Corrected Interrupt Enable /
327	#define MCAN_IE_BEUE (0x1u << 21) /*< \brief (MCAN_IE) Bit Error Uncorrected Interrupt Enable /
328	#define MCAN_IE_ELOE (0x1u << 22) /*< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable /
329	#define MCAN_IE_EPE (0x1u << 23) /*< \brief (MCAN_IE) Error Passive Interrupt Enable /
330	#define MCAN_IE_EWE (0x1u << 24) /*< \brief (MCAN_IE) Warning Status Interrupt Enable /
331	#define MCAN_IE_BOE (0x1u << 25) /*< \brief (MCAN_IE) Bus_Off Status Interrupt Enable /
332	#define MCAN_IE_WDIE (0x1u << 26) /*< \brief (MCAN_IE) Watchdog Interrupt Enable /
333	#define MCAN_IE_CRCEE (0x1u << 27) /*< \brief (MCAN_IE) CRC Error Interrupt Enable /
334	#define MCAN_IE_BEE (0x1u << 28) /*< \brief (MCAN_IE) Bit Error Interrupt Enable /
335	#define MCAN_IE_ACKEE (0x1u << 29) /*< \brief (MCAN_IE) Acknowledge Error Interrupt Enable /
336	#define MCAN_IE_FOEE (0x1u << 30) /*< \brief (MCAN_IE) Format Error Interrupt Enable /
337	#define MCAN_IE_STEE (0x1u << 31) /*< \brief (MCAN_IE) Stuff Error Interrupt Enable /
338	/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */
339	#define MCAN_ILS_RF0NL (0x1u << 0) /*< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line /
340	#define MCAN_ILS_RF0WL (0x1u << 1) /*< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line /
341	#define MCAN_ILS_RF0FL (0x1u << 2) /*< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line /
342	#define MCAN_ILS_RF0LL (0x1u << 3) /*< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line /
343	#define MCAN_ILS_RF1NL (0x1u << 4) /*< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line /
344	#define MCAN_ILS_RF1WL (0x1u << 5) /*< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line /
345	#define MCAN_ILS_RF1FL (0x1u << 6) /*< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line /
346	#define MCAN_ILS_RF1LL (0x1u << 7) /*< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line /
347	#define MCAN_ILS_HPML (0x1u << 8) /*< \brief (MCAN_ILS) High Priority Message Interrupt Line /
348	#define MCAN_ILS_TCL (0x1u << 9) /*< \brief (MCAN_ILS) Transmission Completed Interrupt Line /
349	#define MCAN_ILS_TCFL (0x1u << 10) /*< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line /
350	#define MCAN_ILS_TFEL (0x1u << 11) /*< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line /
351	#define MCAN_ILS_TEFNL (0x1u << 12) /*< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line /
352	#define MCAN_ILS_TEFWL (0x1u << 13) /*< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line /
353	#define MCAN_ILS_TEFFL (0x1u << 14) /*< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line /
354	#define MCAN_ILS_TEFLL (0x1u << 15) /*< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line /
355	#define MCAN_ILS_TSWL (0x1u << 16) /*< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line /
356	#define MCAN_ILS_MRAFL (0x1u << 17) /*< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line /
357	#define MCAN_ILS_TOOL (0x1u << 18) /*< \brief (MCAN_ILS) Timeout Occurred Interrupt Line /
358	#define MCAN_ILS_DRXL (0x1u << 19) /*< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line /
359	#define MCAN_ILS_BECL (0x1u << 20) /*< \brief (MCAN_ILS) Bit Error Corrected Interrupt Line /
360	#define MCAN_ILS_BEUL (0x1u << 21) /*< \brief (MCAN_ILS) Bit Error Uncorrected Interrupt Line /
361	#define MCAN_ILS_ELOL (0x1u << 22) /*< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line /
362	#define MCAN_ILS_EPL (0x1u << 23) /*< \brief (MCAN_ILS) Error Passive Interrupt Line /
363	#define MCAN_ILS_EWL (0x1u << 24) /*< \brief (MCAN_ILS) Warning Status Interrupt Line /
364	#define MCAN_ILS_BOL (0x1u << 25) /*< \brief (MCAN_ILS) Bus_Off Status Interrupt Line /
365	#define MCAN_ILS_WDIL (0x1u << 26) /*< \brief (MCAN_ILS) Watchdog Interrupt Line /
366	#define MCAN_ILS_CRCEL (0x1u << 27) /*< \brief (MCAN_ILS) CRC Error Interrupt Line /
367	#define MCAN_ILS_BEL (0x1u << 28) /*< \brief (MCAN_ILS) Bit Error Interrupt Line /
368	#define MCAN_ILS_ACKEL (0x1u << 29) /*< \brief (MCAN_ILS) Acknowledge Error Interrupt Line /
369	#define MCAN_ILS_FOEL (0x1u << 30) /*< \brief (MCAN_ILS) Format Error Interrupt Line /
370	#define MCAN_ILS_STEL (0x1u << 31) /*< \brief (MCAN_ILS) Stuff Error Interrupt Line /
371	/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */
372	#define MCAN_ILE_EINT0 (0x1u << 0) /*< \brief (MCAN_ILE) Enable Interrupt Line 0 /
373	#define MCAN_ILE_EINT1 (0x1u << 1) /*< \brief (MCAN_ILE) Enable Interrupt Line 1 /
374	/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */
375	#define MCAN_GFC_RRFE (0x1u << 0) /*< \brief (MCAN_GFC) Reject Remote Frames Extended /
376	#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /*< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. /
377	#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /*< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. /
378	#define MCAN_GFC_RRFS (0x1u << 1) /*< \brief (MCAN_GFC) Reject Remote Frames Standard /
379	#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /*< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. /
380	#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /*< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. /
381	#define MCAN_GFC_ANFE_Pos 2
382	#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /*< \brief (MCAN_GFC) Accept Non-matching Frames Extended /
383	#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)))
384	#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /*< \brief (MCAN_GFC) Message stored in Receive FIFO 0 /
385	#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /*< \brief (MCAN_GFC) Message stored in Receive FIFO 1 /
386	#define MCAN_GFC_ANFS_Pos 4
387	#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /*< \brief (MCAN_GFC) Accept Non-matching Frames Standard /
388	#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)))
389	#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /*< \brief (MCAN_GFC) Message stored in Receive FIFO 0 /
390	#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /*< \brief (MCAN_GFC) Message stored in Receive FIFO 1 /
391	/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */
392	#define MCAN_SIDFC_FLSSA_Pos 2
393	#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /*< \brief (MCAN_SIDFC) Filter List Standard Start Address /
394	#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)))
395	#define MCAN_SIDFC_LSS_Pos 16
396	#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /*< \brief (MCAN_SIDFC) List Size Standard /
397	#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)))
398	/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */
399	#define MCAN_XIDFC_FLESA_Pos 2
400	#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /*< \brief (MCAN_XIDFC) Filter List Extended Start Address /
401	#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)))
402	#define MCAN_XIDFC_LSE_Pos 16
403	#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /*< \brief (MCAN_XIDFC) List Size Extended /
404	#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)))
405	/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */
406	#define MCAN_XIDAM_EIDM_Pos 0
407	#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /*< \brief (MCAN_XIDAM) Extended ID Mask /
408	#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)))
409	/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */
410	#define MCAN_HPMS_BIDX_Pos 0
411	#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /*< \brief (MCAN_HPMS) Buffer Index /
412	#define MCAN_HPMS_MSI_Pos 6
413	#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /*< \brief (MCAN_HPMS) Message Storage Indicator /
414	#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /*< \brief (MCAN_HPMS) No FIFO selected. /
415	#define MCAN_HPMS_MSI_LOST (0x1u << 6) /*< \brief (MCAN_HPMS) FIFO message. /
416	#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /*< \brief (MCAN_HPMS) Message stored in FIFO 0. /
417	#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /*< \brief (MCAN_HPMS) Message stored in FIFO 1. /
418	#define MCAN_HPMS_FIDX_Pos 8
419	#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /*< \brief (MCAN_HPMS) Filter Index /
420	#define MCAN_HPMS_FLST (0x1u << 15) /*< \brief (MCAN_HPMS) Filter List /
421	/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */
422	#define MCAN_NDAT1_ND0 (0x1u << 0) /*< \brief (MCAN_NDAT1) New Data /
423	#define MCAN_NDAT1_ND1 (0x1u << 1) /*< \brief (MCAN_NDAT1) New Data /
424	#define MCAN_NDAT1_ND2 (0x1u << 2) /*< \brief (MCAN_NDAT1) New Data /
425	#define MCAN_NDAT1_ND3 (0x1u << 3) /*< \brief (MCAN_NDAT1) New Data /
426	#define MCAN_NDAT1_ND4 (0x1u << 4) /*< \brief (MCAN_NDAT1) New Data /
427	#define MCAN_NDAT1_ND5 (0x1u << 5) /*< \brief (MCAN_NDAT1) New Data /
428	#define MCAN_NDAT1_ND6 (0x1u << 6) /*< \brief (MCAN_NDAT1) New Data /
429	#define MCAN_NDAT1_ND7 (0x1u << 7) /*< \brief (MCAN_NDAT1) New Data /
430	#define MCAN_NDAT1_ND8 (0x1u << 8) /*< \brief (MCAN_NDAT1) New Data /
431	#define MCAN_NDAT1_ND9 (0x1u << 9) /*< \brief (MCAN_NDAT1) New Data /
432	#define MCAN_NDAT1_ND10 (0x1u << 10) /*< \brief (MCAN_NDAT1) New Data /
433	#define MCAN_NDAT1_ND11 (0x1u << 11) /*< \brief (MCAN_NDAT1) New Data /
434	#define MCAN_NDAT1_ND12 (0x1u << 12) /*< \brief (MCAN_NDAT1) New Data /
435	#define MCAN_NDAT1_ND13 (0x1u << 13) /*< \brief (MCAN_NDAT1) New Data /
436	#define MCAN_NDAT1_ND14 (0x1u << 14) /*< \brief (MCAN_NDAT1) New Data /
437	#define MCAN_NDAT1_ND15 (0x1u << 15) /*< \brief (MCAN_NDAT1) New Data /
438	#define MCAN_NDAT1_ND16 (0x1u << 16) /*< \brief (MCAN_NDAT1) New Data /
439	#define MCAN_NDAT1_ND17 (0x1u << 17) /*< \brief (MCAN_NDAT1) New Data /
440	#define MCAN_NDAT1_ND18 (0x1u << 18) /*< \brief (MCAN_NDAT1) New Data /
441	#define MCAN_NDAT1_ND19 (0x1u << 19) /*< \brief (MCAN_NDAT1) New Data /
442	#define MCAN_NDAT1_ND20 (0x1u << 20) /*< \brief (MCAN_NDAT1) New Data /
443	#define MCAN_NDAT1_ND21 (0x1u << 21) /*< \brief (MCAN_NDAT1) New Data /
444	#define MCAN_NDAT1_ND22 (0x1u << 22) /*< \brief (MCAN_NDAT1) New Data /
445	#define MCAN_NDAT1_ND23 (0x1u << 23) /*< \brief (MCAN_NDAT1) New Data /
446	#define MCAN_NDAT1_ND24 (0x1u << 24) /*< \brief (MCAN_NDAT1) New Data /
447	#define MCAN_NDAT1_ND25 (0x1u << 25) /*< \brief (MCAN_NDAT1) New Data /
448	#define MCAN_NDAT1_ND26 (0x1u << 26) /*< \brief (MCAN_NDAT1) New Data /
449	#define MCAN_NDAT1_ND27 (0x1u << 27) /*< \brief (MCAN_NDAT1) New Data /
450	#define MCAN_NDAT1_ND28 (0x1u << 28) /*< \brief (MCAN_NDAT1) New Data /
451	#define MCAN_NDAT1_ND29 (0x1u << 29) /*< \brief (MCAN_NDAT1) New Data /
452	#define MCAN_NDAT1_ND30 (0x1u << 30) /*< \brief (MCAN_NDAT1) New Data /
453	#define MCAN_NDAT1_ND31 (0x1u << 31) /*< \brief (MCAN_NDAT1) New Data /
454	/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */
455	#define MCAN_NDAT2_ND32 (0x1u << 0) /*< \brief (MCAN_NDAT2) New Data /
456	#define MCAN_NDAT2_ND33 (0x1u << 1) /*< \brief (MCAN_NDAT2) New Data /
457	#define MCAN_NDAT2_ND34 (0x1u << 2) /*< \brief (MCAN_NDAT2) New Data /
458	#define MCAN_NDAT2_ND35 (0x1u << 3) /*< \brief (MCAN_NDAT2) New Data /
459	#define MCAN_NDAT2_ND36 (0x1u << 4) /*< \brief (MCAN_NDAT2) New Data /
460	#define MCAN_NDAT2_ND37 (0x1u << 5) /*< \brief (MCAN_NDAT2) New Data /
461	#define MCAN_NDAT2_ND38 (0x1u << 6) /*< \brief (MCAN_NDAT2) New Data /
462	#define MCAN_NDAT2_ND39 (0x1u << 7) /*< \brief (MCAN_NDAT2) New Data /
463	#define MCAN_NDAT2_ND40 (0x1u << 8) /*< \brief (MCAN_NDAT2) New Data /
464	#define MCAN_NDAT2_ND41 (0x1u << 9) /*< \brief (MCAN_NDAT2) New Data /
465	#define MCAN_NDAT2_ND42 (0x1u << 10) /*< \brief (MCAN_NDAT2) New Data /
466	#define MCAN_NDAT2_ND43 (0x1u << 11) /*< \brief (MCAN_NDAT2) New Data /
467	#define MCAN_NDAT2_ND44 (0x1u << 12) /*< \brief (MCAN_NDAT2) New Data /
468	#define MCAN_NDAT2_ND45 (0x1u << 13) /*< \brief (MCAN_NDAT2) New Data /
469	#define MCAN_NDAT2_ND46 (0x1u << 14) /*< \brief (MCAN_NDAT2) New Data /
470	#define MCAN_NDAT2_ND47 (0x1u << 15) /*< \brief (MCAN_NDAT2) New Data /
471	#define MCAN_NDAT2_ND48 (0x1u << 16) /*< \brief (MCAN_NDAT2) New Data /
472	#define MCAN_NDAT2_ND49 (0x1u << 17) /*< \brief (MCAN_NDAT2) New Data /
473	#define MCAN_NDAT2_ND50 (0x1u << 18) /*< \brief (MCAN_NDAT2) New Data /
474	#define MCAN_NDAT2_ND51 (0x1u << 19) /*< \brief (MCAN_NDAT2) New Data /
475	#define MCAN_NDAT2_ND52 (0x1u << 20) /*< \brief (MCAN_NDAT2) New Data /
476	#define MCAN_NDAT2_ND53 (0x1u << 21) /*< \brief (MCAN_NDAT2) New Data /
477	#define MCAN_NDAT2_ND54 (0x1u << 22) /*< \brief (MCAN_NDAT2) New Data /
478	#define MCAN_NDAT2_ND55 (0x1u << 23) /*< \brief (MCAN_NDAT2) New Data /
479	#define MCAN_NDAT2_ND56 (0x1u << 24) /*< \brief (MCAN_NDAT2) New Data /
480	#define MCAN_NDAT2_ND57 (0x1u << 25) /*< \brief (MCAN_NDAT2) New Data /
481	#define MCAN_NDAT2_ND58 (0x1u << 26) /*< \brief (MCAN_NDAT2) New Data /
482	#define MCAN_NDAT2_ND59 (0x1u << 27) /*< \brief (MCAN_NDAT2) New Data /
483	#define MCAN_NDAT2_ND60 (0x1u << 28) /*< \brief (MCAN_NDAT2) New Data /
484	#define MCAN_NDAT2_ND61 (0x1u << 29) /*< \brief (MCAN_NDAT2) New Data /
485	#define MCAN_NDAT2_ND62 (0x1u << 30) /*< \brief (MCAN_NDAT2) New Data /
486	#define MCAN_NDAT2_ND63 (0x1u << 31) /*< \brief (MCAN_NDAT2) New Data /
487	/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */
488	#define MCAN_RXF0C_F0SA_Pos 2
489	#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /*< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address /
490	#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)))
491	#define MCAN_RXF0C_F0S_Pos 16
492	#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /*< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address /
493	#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)))
494	#define MCAN_RXF0C_F0WM_Pos 24
495	#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /*< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark /
496	#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)))
497	#define MCAN_RXF0C_F0OM (0x1u << 31) /*< \brief (MCAN_RXF0C) FIFO 0 Operation Mode /
498	/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */
499	#define MCAN_RXF0S_F0FL_Pos 0
500	#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /*< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level /
501	#define MCAN_RXF0S_F0GI_Pos 8
502	#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /*< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index /
503	#define MCAN_RXF0S_F0PI_Pos 16
504	#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /*< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index /
505	#define MCAN_RXF0S_F0F (0x1u << 24) /*< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level /
506	#define MCAN_RXF0S_RF0L (0x1u << 25) /*< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost /
507	/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */
508	#define MCAN_RXF0A_F0AI_Pos 0
509	#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /*< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index /
510	#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)))
511	/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */
512	#define MCAN_RXBC_RBSA_Pos 2
513	#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /*< \brief (MCAN_RXBC) Receive Buffer Start Address /
514	#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)))
515	/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */
516	#define MCAN_RXF1C_F1SA_Pos 2
517	#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /*< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address /
518	#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)))
519	#define MCAN_RXF1C_F1S_Pos 16
520	#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /*< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address /
521	#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)))
522	#define MCAN_RXF1C_F1WM_Pos 24
523	#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /*< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark /
524	#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)))
525	#define MCAN_RXF1C_F1OM (0x1u << 31) /*< \brief (MCAN_RXF1C) FIFO 1 Operation Mode /
526	/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */
527	#define MCAN_RXF1S_F1FL_Pos 0
528	#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /*< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level /
529	#define MCAN_RXF1S_F1GI_Pos 8
530	#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /*< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index /
531	#define MCAN_RXF1S_F1PI_Pos 16
532	#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /*< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index /
533	#define MCAN_RXF1S_F1F (0x1u << 24) /*< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level /
534	#define MCAN_RXF1S_RF1L (0x1u << 25) /*< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost /
535	#define MCAN_RXF1S_DMS_Pos 30
536	#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /*< \brief (MCAN_RXF1S) Debug Message Status /
537	#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /*< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. /
538	#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /*< \brief (MCAN_RXF1S) Debug message A received. /
539	#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /*< \brief (MCAN_RXF1S) Debug messages A, B received. /
540	#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /*< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. /
541	/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */
542	#define MCAN_RXF1A_F1AI_Pos 0
543	#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /*< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index /
544	#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)))
545	/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */
546	#define MCAN_RXESC_F0DS_Pos 0
547	#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /*< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size /
548	#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)))
549	#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /*< \brief (MCAN_RXESC) 8-byte data field /
550	#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /*< \brief (MCAN_RXESC) 12-byte data field /
551	#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /*< \brief (MCAN_RXESC) 16-byte data field /
552	#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /*< \brief (MCAN_RXESC) 20-byte data field /
553	#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /*< \brief (MCAN_RXESC) 24-byte data field /
554	#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /*< \brief (MCAN_RXESC) 32-byte data field /
555	#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /*< \brief (MCAN_RXESC) 48-byte data field /
556	#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /*< \brief (MCAN_RXESC) 64-byte data field /
557	#define MCAN_RXESC_F1DS_Pos 4
558	#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /*< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size /
559	#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)))
560	#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /*< \brief (MCAN_RXESC) 8-byte data field /
561	#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /*< \brief (MCAN_RXESC) 12-byte data field /
562	#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /*< \brief (MCAN_RXESC) 16-byte data field /
563	#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /*< \brief (MCAN_RXESC) 20-byte data field /
564	#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /*< \brief (MCAN_RXESC) 24-byte data field /
565	#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /*< \brief (MCAN_RXESC) 32-byte data field /
566	#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /*< \brief (MCAN_RXESC) 48-byte data field /
567	#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /*< \brief (MCAN_RXESC) 64-byte data field /
568	#define MCAN_RXESC_RBDS_Pos 8
569	#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /*< \brief (MCAN_RXESC) Receive Buffer Data Field Size /
570	#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)))
571	#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /*< \brief (MCAN_RXESC) 8-byte data field /
572	#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /*< \brief (MCAN_RXESC) 12-byte data field /
573	#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /*< \brief (MCAN_RXESC) 16-byte data field /
574	#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /*< \brief (MCAN_RXESC) 20-byte data field /
575	#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /*< \brief (MCAN_RXESC) 24-byte data field /
576	#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /*< \brief (MCAN_RXESC) 32-byte data field /
577	#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /*< \brief (MCAN_RXESC) 48-byte data field /
578	#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /*< \brief (MCAN_RXESC) 64-byte data field /
579	/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */
580	#define MCAN_TXBC_TBSA_Pos 2
581	#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /*< \brief (MCAN_TXBC) Tx Buffers Start Address /
582	#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)))
583	#define MCAN_TXBC_NDTB_Pos 16
584	#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /*< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers /
585	#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)))
586	#define MCAN_TXBC_TFQS_Pos 24
587	#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /*< \brief (MCAN_TXBC) Transmit FIFO/Queue Size /
588	#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)))
589	#define MCAN_TXBC_TFQM (0x1u << 30) /*< \brief (MCAN_TXBC) Tx FIFO/Queue Mode /
590	/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */
591	#define MCAN_TXFQS_TFFL_Pos 0
592	#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /*< \brief (MCAN_TXFQS) Tx FIFO Free Level /
593	#define MCAN_TXFQS_TFGI_Pos 8
594	#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /*< \brief (MCAN_TXFQS) Tx FIFO Get Index /
595	#define MCAN_TXFQS_TFQPI_Pos 16
596	#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /*< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index /
597	#define MCAN_TXFQS_TFQF (0x1u << 21) /*< \brief (MCAN_TXFQS) Tx FIFO/Queue Full /
598	/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */
599	#define MCAN_TXESC_TBDS_Pos 0
600	#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /*< \brief (MCAN_TXESC) Tx Buffer Data Field Size /
601	#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)))
602	#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /*< \brief (MCAN_TXESC) 8-byte data field /
603	#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /*< \brief (MCAN_TXESC) 12-byte data field /
604	#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /*< \brief (MCAN_TXESC) 16-byte data field /
605	#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /*< \brief (MCAN_TXESC) 20-byte data field /
606	#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /*< \brief (MCAN_TXESC) 24-byte data field /
607	#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /*< \brief (MCAN_TXESC) 32-byte data field /
608	#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /*< \brief (MCAN_TXESC) 4- byte data field /
609	#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /*< \brief (MCAN_TXESC) 64-byte data field /
610	/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */
611	#define MCAN_TXBRP_TRP0 (0x1u << 0) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 /
612	#define MCAN_TXBRP_TRP1 (0x1u << 1) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 /
613	#define MCAN_TXBRP_TRP2 (0x1u << 2) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 /
614	#define MCAN_TXBRP_TRP3 (0x1u << 3) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 /
615	#define MCAN_TXBRP_TRP4 (0x1u << 4) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 /
616	#define MCAN_TXBRP_TRP5 (0x1u << 5) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 /
617	#define MCAN_TXBRP_TRP6 (0x1u << 6) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 /
618	#define MCAN_TXBRP_TRP7 (0x1u << 7) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 /
619	#define MCAN_TXBRP_TRP8 (0x1u << 8) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 /
620	#define MCAN_TXBRP_TRP9 (0x1u << 9) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 /
621	#define MCAN_TXBRP_TRP10 (0x1u << 10) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 /
622	#define MCAN_TXBRP_TRP11 (0x1u << 11) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 /
623	#define MCAN_TXBRP_TRP12 (0x1u << 12) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 /
624	#define MCAN_TXBRP_TRP13 (0x1u << 13) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 /
625	#define MCAN_TXBRP_TRP14 (0x1u << 14) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 /
626	#define MCAN_TXBRP_TRP15 (0x1u << 15) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 /
627	#define MCAN_TXBRP_TRP16 (0x1u << 16) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 /
628	#define MCAN_TXBRP_TRP17 (0x1u << 17) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 /
629	#define MCAN_TXBRP_TRP18 (0x1u << 18) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 /
630	#define MCAN_TXBRP_TRP19 (0x1u << 19) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 /
631	#define MCAN_TXBRP_TRP20 (0x1u << 20) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 /
632	#define MCAN_TXBRP_TRP21 (0x1u << 21) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 /
633	#define MCAN_TXBRP_TRP22 (0x1u << 22) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 /
634	#define MCAN_TXBRP_TRP23 (0x1u << 23) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 /
635	#define MCAN_TXBRP_TRP24 (0x1u << 24) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 /
636	#define MCAN_TXBRP_TRP25 (0x1u << 25) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 /
637	#define MCAN_TXBRP_TRP26 (0x1u << 26) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 /
638	#define MCAN_TXBRP_TRP27 (0x1u << 27) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 /
639	#define MCAN_TXBRP_TRP28 (0x1u << 28) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 /
640	#define MCAN_TXBRP_TRP29 (0x1u << 29) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 /
641	#define MCAN_TXBRP_TRP30 (0x1u << 30) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 /
642	#define MCAN_TXBRP_TRP31 (0x1u << 31) /*< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 /
643	/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */
644	#define MCAN_TXBAR_AR0 (0x1u << 0) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 /
645	#define MCAN_TXBAR_AR1 (0x1u << 1) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 /
646	#define MCAN_TXBAR_AR2 (0x1u << 2) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 /
647	#define MCAN_TXBAR_AR3 (0x1u << 3) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 /
648	#define MCAN_TXBAR_AR4 (0x1u << 4) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 /
649	#define MCAN_TXBAR_AR5 (0x1u << 5) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 /
650	#define MCAN_TXBAR_AR6 (0x1u << 6) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 /
651	#define MCAN_TXBAR_AR7 (0x1u << 7) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 /
652	#define MCAN_TXBAR_AR8 (0x1u << 8) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 /
653	#define MCAN_TXBAR_AR9 (0x1u << 9) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 /
654	#define MCAN_TXBAR_AR10 (0x1u << 10) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 /
655	#define MCAN_TXBAR_AR11 (0x1u << 11) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 /
656	#define MCAN_TXBAR_AR12 (0x1u << 12) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 /
657	#define MCAN_TXBAR_AR13 (0x1u << 13) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 /
658	#define MCAN_TXBAR_AR14 (0x1u << 14) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 /
659	#define MCAN_TXBAR_AR15 (0x1u << 15) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 /
660	#define MCAN_TXBAR_AR16 (0x1u << 16) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 /
661	#define MCAN_TXBAR_AR17 (0x1u << 17) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 /
662	#define MCAN_TXBAR_AR18 (0x1u << 18) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 /
663	#define MCAN_TXBAR_AR19 (0x1u << 19) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 /
664	#define MCAN_TXBAR_AR20 (0x1u << 20) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 /
665	#define MCAN_TXBAR_AR21 (0x1u << 21) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 /
666	#define MCAN_TXBAR_AR22 (0x1u << 22) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 /
667	#define MCAN_TXBAR_AR23 (0x1u << 23) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 /
668	#define MCAN_TXBAR_AR24 (0x1u << 24) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 /
669	#define MCAN_TXBAR_AR25 (0x1u << 25) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 /
670	#define MCAN_TXBAR_AR26 (0x1u << 26) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 /
671	#define MCAN_TXBAR_AR27 (0x1u << 27) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 /
672	#define MCAN_TXBAR_AR28 (0x1u << 28) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 /
673	#define MCAN_TXBAR_AR29 (0x1u << 29) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 /
674	#define MCAN_TXBAR_AR30 (0x1u << 30) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 /
675	#define MCAN_TXBAR_AR31 (0x1u << 31) /*< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 /
676	/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */
677	#define MCAN_TXBCR_CR0 (0x1u << 0) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 /
678	#define MCAN_TXBCR_CR1 (0x1u << 1) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 /
679	#define MCAN_TXBCR_CR2 (0x1u << 2) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 /
680	#define MCAN_TXBCR_CR3 (0x1u << 3) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 /
681	#define MCAN_TXBCR_CR4 (0x1u << 4) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 /
682	#define MCAN_TXBCR_CR5 (0x1u << 5) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 /
683	#define MCAN_TXBCR_CR6 (0x1u << 6) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 /
684	#define MCAN_TXBCR_CR7 (0x1u << 7) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 /
685	#define MCAN_TXBCR_CR8 (0x1u << 8) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 /
686	#define MCAN_TXBCR_CR9 (0x1u << 9) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 /
687	#define MCAN_TXBCR_CR10 (0x1u << 10) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 /
688	#define MCAN_TXBCR_CR11 (0x1u << 11) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 /
689	#define MCAN_TXBCR_CR12 (0x1u << 12) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 /
690	#define MCAN_TXBCR_CR13 (0x1u << 13) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 /
691	#define MCAN_TXBCR_CR14 (0x1u << 14) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 /
692	#define MCAN_TXBCR_CR15 (0x1u << 15) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 /
693	#define MCAN_TXBCR_CR16 (0x1u << 16) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 /
694	#define MCAN_TXBCR_CR17 (0x1u << 17) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 /
695	#define MCAN_TXBCR_CR18 (0x1u << 18) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 /
696	#define MCAN_TXBCR_CR19 (0x1u << 19) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 /
697	#define MCAN_TXBCR_CR20 (0x1u << 20) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 /
698	#define MCAN_TXBCR_CR21 (0x1u << 21) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 /
699	#define MCAN_TXBCR_CR22 (0x1u << 22) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 /
700	#define MCAN_TXBCR_CR23 (0x1u << 23) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 /
701	#define MCAN_TXBCR_CR24 (0x1u << 24) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 /
702	#define MCAN_TXBCR_CR25 (0x1u << 25) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 /
703	#define MCAN_TXBCR_CR26 (0x1u << 26) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 /
704	#define MCAN_TXBCR_CR27 (0x1u << 27) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 /
705	#define MCAN_TXBCR_CR28 (0x1u << 28) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 /
706	#define MCAN_TXBCR_CR29 (0x1u << 29) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 /
707	#define MCAN_TXBCR_CR30 (0x1u << 30) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 /
708	#define MCAN_TXBCR_CR31 (0x1u << 31) /*< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 /
709	/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */
710	#define MCAN_TXBTO_TO0 (0x1u << 0) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 /
711	#define MCAN_TXBTO_TO1 (0x1u << 1) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 /
712	#define MCAN_TXBTO_TO2 (0x1u << 2) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 /
713	#define MCAN_TXBTO_TO3 (0x1u << 3) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 /
714	#define MCAN_TXBTO_TO4 (0x1u << 4) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 /
715	#define MCAN_TXBTO_TO5 (0x1u << 5) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 /
716	#define MCAN_TXBTO_TO6 (0x1u << 6) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 /
717	#define MCAN_TXBTO_TO7 (0x1u << 7) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 /
718	#define MCAN_TXBTO_TO8 (0x1u << 8) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 /
719	#define MCAN_TXBTO_TO9 (0x1u << 9) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 /
720	#define MCAN_TXBTO_TO10 (0x1u << 10) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 /
721	#define MCAN_TXBTO_TO11 (0x1u << 11) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 /
722	#define MCAN_TXBTO_TO12 (0x1u << 12) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 /
723	#define MCAN_TXBTO_TO13 (0x1u << 13) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 /
724	#define MCAN_TXBTO_TO14 (0x1u << 14) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 /
725	#define MCAN_TXBTO_TO15 (0x1u << 15) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 /
726	#define MCAN_TXBTO_TO16 (0x1u << 16) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 /
727	#define MCAN_TXBTO_TO17 (0x1u << 17) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 /
728	#define MCAN_TXBTO_TO18 (0x1u << 18) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 /
729	#define MCAN_TXBTO_TO19 (0x1u << 19) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 /
730	#define MCAN_TXBTO_TO20 (0x1u << 20) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 /
731	#define MCAN_TXBTO_TO21 (0x1u << 21) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 /
732	#define MCAN_TXBTO_TO22 (0x1u << 22) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 /
733	#define MCAN_TXBTO_TO23 (0x1u << 23) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 /
734	#define MCAN_TXBTO_TO24 (0x1u << 24) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 /
735	#define MCAN_TXBTO_TO25 (0x1u << 25) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 /
736	#define MCAN_TXBTO_TO26 (0x1u << 26) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 /
737	#define MCAN_TXBTO_TO27 (0x1u << 27) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 /
738	#define MCAN_TXBTO_TO28 (0x1u << 28) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 /
739	#define MCAN_TXBTO_TO29 (0x1u << 29) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 /
740	#define MCAN_TXBTO_TO30 (0x1u << 30) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 /
741	#define MCAN_TXBTO_TO31 (0x1u << 31) /*< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 /
742	/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */
743	#define MCAN_TXBCF_CF0 (0x1u << 0) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 /
744	#define MCAN_TXBCF_CF1 (0x1u << 1) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 /
745	#define MCAN_TXBCF_CF2 (0x1u << 2) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 /
746	#define MCAN_TXBCF_CF3 (0x1u << 3) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 /
747	#define MCAN_TXBCF_CF4 (0x1u << 4) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 /
748	#define MCAN_TXBCF_CF5 (0x1u << 5) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 /
749	#define MCAN_TXBCF_CF6 (0x1u << 6) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 /
750	#define MCAN_TXBCF_CF7 (0x1u << 7) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 /
751	#define MCAN_TXBCF_CF8 (0x1u << 8) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 /
752	#define MCAN_TXBCF_CF9 (0x1u << 9) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 /
753	#define MCAN_TXBCF_CF10 (0x1u << 10) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 /
754	#define MCAN_TXBCF_CF11 (0x1u << 11) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 /
755	#define MCAN_TXBCF_CF12 (0x1u << 12) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 /
756	#define MCAN_TXBCF_CF13 (0x1u << 13) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 /
757	#define MCAN_TXBCF_CF14 (0x1u << 14) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 /
758	#define MCAN_TXBCF_CF15 (0x1u << 15) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 /
759	#define MCAN_TXBCF_CF16 (0x1u << 16) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 /
760	#define MCAN_TXBCF_CF17 (0x1u << 17) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 /
761	#define MCAN_TXBCF_CF18 (0x1u << 18) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 /
762	#define MCAN_TXBCF_CF19 (0x1u << 19) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 /
763	#define MCAN_TXBCF_CF20 (0x1u << 20) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 /
764	#define MCAN_TXBCF_CF21 (0x1u << 21) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 /
765	#define MCAN_TXBCF_CF22 (0x1u << 22) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 /
766	#define MCAN_TXBCF_CF23 (0x1u << 23) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 /
767	#define MCAN_TXBCF_CF24 (0x1u << 24) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 /
768	#define MCAN_TXBCF_CF25 (0x1u << 25) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 /
769	#define MCAN_TXBCF_CF26 (0x1u << 26) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 /
770	#define MCAN_TXBCF_CF27 (0x1u << 27) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 /
771	#define MCAN_TXBCF_CF28 (0x1u << 28) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 /
772	#define MCAN_TXBCF_CF29 (0x1u << 29) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 /
773	#define MCAN_TXBCF_CF30 (0x1u << 30) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 /
774	#define MCAN_TXBCF_CF31 (0x1u << 31) /*< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 /
775	/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */
776	#define MCAN_TXBTIE_TIE0 (0x1u << 0) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 /
777	#define MCAN_TXBTIE_TIE1 (0x1u << 1) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 /
778	#define MCAN_TXBTIE_TIE2 (0x1u << 2) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 /
779	#define MCAN_TXBTIE_TIE3 (0x1u << 3) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 /
780	#define MCAN_TXBTIE_TIE4 (0x1u << 4) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 /
781	#define MCAN_TXBTIE_TIE5 (0x1u << 5) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 /
782	#define MCAN_TXBTIE_TIE6 (0x1u << 6) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 /
783	#define MCAN_TXBTIE_TIE7 (0x1u << 7) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 /
784	#define MCAN_TXBTIE_TIE8 (0x1u << 8) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 /
785	#define MCAN_TXBTIE_TIE9 (0x1u << 9) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 /
786	#define MCAN_TXBTIE_TIE10 (0x1u << 10) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 /
787	#define MCAN_TXBTIE_TIE11 (0x1u << 11) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 /
788	#define MCAN_TXBTIE_TIE12 (0x1u << 12) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 /
789	#define MCAN_TXBTIE_TIE13 (0x1u << 13) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 /
790	#define MCAN_TXBTIE_TIE14 (0x1u << 14) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 /
791	#define MCAN_TXBTIE_TIE15 (0x1u << 15) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 /
792	#define MCAN_TXBTIE_TIE16 (0x1u << 16) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 /
793	#define MCAN_TXBTIE_TIE17 (0x1u << 17) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 /
794	#define MCAN_TXBTIE_TIE18 (0x1u << 18) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 /
795	#define MCAN_TXBTIE_TIE19 (0x1u << 19) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 /
796	#define MCAN_TXBTIE_TIE20 (0x1u << 20) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 /
797	#define MCAN_TXBTIE_TIE21 (0x1u << 21) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 /
798	#define MCAN_TXBTIE_TIE22 (0x1u << 22) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 /
799	#define MCAN_TXBTIE_TIE23 (0x1u << 23) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 /
800	#define MCAN_TXBTIE_TIE24 (0x1u << 24) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 /
801	#define MCAN_TXBTIE_TIE25 (0x1u << 25) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 /
802	#define MCAN_TXBTIE_TIE26 (0x1u << 26) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 /
803	#define MCAN_TXBTIE_TIE27 (0x1u << 27) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 /
804	#define MCAN_TXBTIE_TIE28 (0x1u << 28) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 /
805	#define MCAN_TXBTIE_TIE29 (0x1u << 29) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 /
806	#define MCAN_TXBTIE_TIE30 (0x1u << 30) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 /
807	#define MCAN_TXBTIE_TIE31 (0x1u << 31) /*< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 /
808	/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */
809	#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 /
810	#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 /
811	#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 /
812	#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 /
813	#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 /
814	#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 /
815	#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 /
816	#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 /
817	#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 /
818	#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 /
819	#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 /
820	#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 /
821	#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 /
822	#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 /
823	#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 /
824	#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 /
825	#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 /
826	#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 /
827	#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 /
828	#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 /
829	#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 /
830	#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 /
831	#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 /
832	#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 /
833	#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 /
834	#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 /
835	#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 /
836	#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 /
837	#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 /
838	#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 /
839	#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 /
840	#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /*< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 /
841	/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */
842	#define MCAN_TXEFC_EFSA_Pos 2
843	#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /*< \brief (MCAN_TXEFC) Event FIFO Start Address /
844	#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)))
845	#define MCAN_TXEFC_EFS_Pos 16
846	#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /*< \brief (MCAN_TXEFC) Event FIFO Size /
847	#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)))
848	#define MCAN_TXEFC_EFWM_Pos 24
849	#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /*< \brief (MCAN_TXEFC) Event FIFO Watermark /
850	#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)))
851	/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */
852	#define MCAN_TXEFS_EFFL_Pos 0
853	#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /*< \brief (MCAN_TXEFS) Event FIFO Fill Level /
854	#define MCAN_TXEFS_EFGI_Pos 8
855	#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /*< \brief (MCAN_TXEFS) Event FIFO Get Index /
856	#define MCAN_TXEFS_EFPI_Pos 16
857	#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /*< \brief (MCAN_TXEFS) Event FIFO Put Index /
858	#define MCAN_TXEFS_EFF (0x1u << 24) /*< \brief (MCAN_TXEFS) Event FIFO Full /
859	#define MCAN_TXEFS_TEFL (0x1u << 25) /*< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost /
860	/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */
861	#define MCAN_TXEFA_EFAI_Pos 0
862	#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /*< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index /
863	#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)))
864
865	/@}/
866
867
868	#endif /* _SAMV71_MCAN_COMPONENT_ */

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source: rtems/bsps/arm/atsam/include/libchip/include/samv71/component/component_mcan.h @ 2afb22b

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