source: rtems/bsps/arm/atsam/include/libchip/include/sams70/sams70q21.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 33.3 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
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9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70Q21_
31#define _SAMS70Q21_
32
33/** \addtogroup SAMS70Q21_definitions SAMS70Q21 definitions
34  This file defines all structures and symbols for SAMS70Q21:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAMS70Q21 */
52/* ************************************************************************** */
53/** \addtogroup SAMS70Q21_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAMS70Q21 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAMS70Q21 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAMS70Q21 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAMS70Q21 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAMS70Q21 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAMS70Q21 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAMS70Q21 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAMS70Q21 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAMS70Q21 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAMS70Q21 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAMS70Q21 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAMS70Q21 Parallel I/O Controller B (PIOB) */
82  PIOC_IRQn            = 12, /**< 12 SAMS70Q21 Parallel I/O Controller C (PIOC) */
83  USART0_IRQn          = 13, /**< 13 SAMS70Q21 USART 0 (USART0) */
84  USART1_IRQn          = 14, /**< 14 SAMS70Q21 USART 1 (USART1) */
85  USART2_IRQn          = 15, /**< 15 SAMS70Q21 USART 2 (USART2) */
86  PIOD_IRQn            = 16, /**< 16 SAMS70Q21 Parallel I/O Controller D (PIOD) */
87  PIOE_IRQn            = 17, /**< 17 SAMS70Q21 Parallel I/O Controller E (PIOE) */
88  HSMCI_IRQn           = 18, /**< 18 SAMS70Q21 Multimedia Card Interface (HSMCI) */
89  TWIHS0_IRQn          = 19, /**< 19 SAMS70Q21 Two Wire Interface 0 HS (TWIHS0) */
90  TWIHS1_IRQn          = 20, /**< 20 SAMS70Q21 Two Wire Interface 1 HS (TWIHS1) */
91  SPI0_IRQn            = 21, /**< 21 SAMS70Q21 Serial Peripheral Interface 0 (SPI0) */
92  SSC_IRQn             = 22, /**< 22 SAMS70Q21 Synchronous Serial Controller (SSC) */
93  TC0_IRQn             = 23, /**< 23 SAMS70Q21 Timer/Counter 0 (TC0) */
94  TC1_IRQn             = 24, /**< 24 SAMS70Q21 Timer/Counter 1 (TC1) */
95  TC2_IRQn             = 25, /**< 25 SAMS70Q21 Timer/Counter 2 (TC2) */
96  TC3_IRQn             = 26, /**< 26 SAMS70Q21 Timer/Counter 3 (TC3) */
97  TC4_IRQn             = 27, /**< 27 SAMS70Q21 Timer/Counter 4 (TC4) */
98  TC5_IRQn             = 28, /**< 28 SAMS70Q21 Timer/Counter 5 (TC5) */
99  AFEC0_IRQn           = 29, /**< 29 SAMS70Q21 Analog Front End 0 (AFEC0) */
100  DACC_IRQn            = 30, /**< 30 SAMS70Q21 Digital To Analog Converter (DACC) */
101  PWM0_IRQn            = 31, /**< 31 SAMS70Q21 Pulse Width Modulation 0 (PWM0) */
102  ICM_IRQn             = 32, /**< 32 SAMS70Q21 Integrity Check Monitor (ICM) */
103  ACC_IRQn             = 33, /**< 33 SAMS70Q21 Analog Comparator (ACC) */
104  USBHS_IRQn           = 34, /**< 34 SAMS70Q21 USB Host / Device Controller (USBHS) */
105  AFEC1_IRQn           = 40, /**< 40 SAMS70Q21 Analog Front End 1 (AFEC1) */
106  TWIHS2_IRQn          = 41, /**< 41 SAMS70Q21 Two Wire Interface 2 HS (TWIHS2) */
107  SPI1_IRQn            = 42, /**< 42 SAMS70Q21 Serial Peripheral Interface 1 (SPI1) */
108  QSPI_IRQn            = 43, /**< 43 SAMS70Q21 Quad I/O Serial Peripheral Interface (QSPI) */
109  UART2_IRQn           = 44, /**< 44 SAMS70Q21 UART 2 (UART2) */
110  UART3_IRQn           = 45, /**< 45 SAMS70Q21 UART 3 (UART3) */
111  UART4_IRQn           = 46, /**< 46 SAMS70Q21 UART 4 (UART4) */
112  TC6_IRQn             = 47, /**< 47 SAMS70Q21 Timer/Counter 6 (TC6) */
113  TC7_IRQn             = 48, /**< 48 SAMS70Q21 Timer/Counter 7 (TC7) */
114  TC8_IRQn             = 49, /**< 49 SAMS70Q21 Timer/Counter 8 (TC8) */
115  TC9_IRQn             = 50, /**< 50 SAMS70Q21 Timer/Counter 9 (TC9) */
116  TC10_IRQn            = 51, /**< 51 SAMS70Q21 Timer/Counter 10 (TC10) */
117  TC11_IRQn            = 52, /**< 52 SAMS70Q21 Timer/Counter 11 (TC11) */
118  AES_IRQn             = 56, /**< 56 SAMS70Q21 AES (AES) */
119  TRNG_IRQn            = 57, /**< 57 SAMS70Q21 True Random Generator (TRNG) */
120  XDMAC_IRQn           = 58, /**< 58 SAMS70Q21 DMA (XDMAC) */
121  ISI_IRQn             = 59, /**< 59 SAMS70Q21 Camera Interface (ISI) */
122  PWM1_IRQn            = 60, /**< 60 SAMS70Q21 Pulse Width Modulation 1 (PWM1) */
123  SDRAMC_IRQn          = 62, /**< 62 SAMS70Q21 SDRAM Controller (SDRAMC) */
124  RSWDT_IRQn           = 63, /**< 63 SAMS70Q21 Reinforced Secure Watchdog Timer (RSWDT) */
125
126  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
127} IRQn_Type;
128
129typedef struct _DeviceVectors
130{
131  /* Stack pointer */
132  void* pvStack;
133
134  /* Cortex-M handlers */
135  void* pfnReset_Handler;
136  void* pfnNMI_Handler;
137  void* pfnHardFault_Handler;
138  void* pfnMemManage_Handler;
139  void* pfnBusFault_Handler;
140  void* pfnUsageFault_Handler;
141  void* pfnReserved1_Handler;
142  void* pfnReserved2_Handler;
143  void* pfnReserved3_Handler;
144  void* pfnReserved4_Handler;
145  void* pfnSVC_Handler;
146  void* pfnDebugMon_Handler;
147  void* pfnReserved5_Handler;
148  void* pfnPendSV_Handler;
149  void* pfnSysTick_Handler;
150
151  /* Peripheral handlers */
152  void* pfnSUPC_Handler;   /*  0 Supply Controller */
153  void* pfnRSTC_Handler;   /*  1 Reset Controller */
154  void* pfnRTC_Handler;    /*  2 Real Time Clock */
155  void* pfnRTT_Handler;    /*  3 Real Time Timer */
156  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
157  void* pfnPMC_Handler;    /*  5 Power Management Controller */
158  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
159  void* pfnUART0_Handler;  /*  7 UART 0 */
160  void* pfnUART1_Handler;  /*  8 UART 1 */
161  void* pvReserved9;
162  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
163  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
164  void* pfnPIOC_Handler;   /* 12 Parallel I/O Controller C */
165  void* pfnUSART0_Handler; /* 13 USART 0 */
166  void* pfnUSART1_Handler; /* 14 USART 1 */
167  void* pfnUSART2_Handler; /* 15 USART 2 */
168  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
169  void* pfnPIOE_Handler;   /* 17 Parallel I/O Controller E */
170  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
171  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
172  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
173  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
174  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
175  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
176  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
177  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
178  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
179  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
180  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
181  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
182  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
183  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
184  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
185  void* pfnACC_Handler;    /* 33 Analog Comparator */
186  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
187  void* pvReserved35;
188  void* pvReserved36;
189  void* pvReserved37;
190  void* pvReserved38;
191  void* pvReserved39;
192  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
193  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
194  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
195  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
196  void* pfnUART2_Handler;  /* 44 UART 2 */
197  void* pfnUART3_Handler;  /* 45 UART 3 */
198  void* pfnUART4_Handler;  /* 46 UART 4 */
199  void* pfnTC6_Handler;    /* 47 Timer/Counter 6 */
200  void* pfnTC7_Handler;    /* 48 Timer/Counter 7 */
201  void* pfnTC8_Handler;    /* 49 Timer/Counter 8 */
202  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
203  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
204  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
205  void* pvReserved53;
206  void* pvReserved54;
207  void* pvReserved55;
208  void* pfnAES_Handler;    /* 56 AES */
209  void* pfnTRNG_Handler;   /* 57 True Random Generator */
210  void* pfnXDMAC_Handler;  /* 58 DMA */
211  void* pfnISI_Handler;    /* 59 Camera Interface */
212  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
213  void* pvReserved61;
214  void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
215  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
216} DeviceVectors;
217
218/* Cortex-M7 core handlers */
219void Reset_Handler      ( void );
220void NMI_Handler        ( void );
221void HardFault_Handler  ( void );
222void MemManage_Handler  ( void );
223void BusFault_Handler   ( void );
224void UsageFault_Handler ( void );
225void SVC_Handler        ( void );
226void DebugMon_Handler   ( void );
227void PendSV_Handler     ( void );
228void SysTick_Handler    ( void );
229
230/* Peripherals handlers */
231void ACC_Handler        ( void );
232void AES_Handler        ( void );
233void AFEC0_Handler      ( void );
234void AFEC1_Handler      ( void );
235void DACC_Handler       ( void );
236void EFC_Handler        ( void );
237void HSMCI_Handler      ( void );
238void ICM_Handler        ( void );
239void ISI_Handler        ( void );
240void PIOA_Handler       ( void );
241void PIOB_Handler       ( void );
242void PIOC_Handler       ( void );
243void PIOD_Handler       ( void );
244void PIOE_Handler       ( void );
245void PMC_Handler        ( void );
246void PWM0_Handler       ( void );
247void PWM1_Handler       ( void );
248void QSPI_Handler       ( void );
249void RSTC_Handler       ( void );
250void RSWDT_Handler      ( void );
251void RTC_Handler        ( void );
252void RTT_Handler        ( void );
253void SDRAMC_Handler     ( void );
254void SPI0_Handler       ( void );
255void SPI1_Handler       ( void );
256void SSC_Handler        ( void );
257void SUPC_Handler       ( void );
258void TC0_Handler        ( void );
259void TC1_Handler        ( void );
260void TC2_Handler        ( void );
261void TC3_Handler        ( void );
262void TC4_Handler        ( void );
263void TC5_Handler        ( void );
264void TC6_Handler        ( void );
265void TC7_Handler        ( void );
266void TC8_Handler        ( void );
267void TC9_Handler        ( void );
268void TC10_Handler       ( void );
269void TC11_Handler       ( void );
270void TRNG_Handler       ( void );
271void TWIHS0_Handler     ( void );
272void TWIHS1_Handler     ( void );
273void TWIHS2_Handler     ( void );
274void UART0_Handler      ( void );
275void UART1_Handler      ( void );
276void UART2_Handler      ( void );
277void UART3_Handler      ( void );
278void UART4_Handler      ( void );
279void USART0_Handler     ( void );
280void USART1_Handler     ( void );
281void USART2_Handler     ( void );
282void USBHS_Handler      ( void );
283void WDT_Handler        ( void );
284void XDMAC_Handler      ( void );
285
286/**
287 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
288 */
289
290#define __CM7_REV              0x0000 /**< SAMS70Q21 core revision number ([15:8] revision number, [7:0] patch number) */
291#define __MPU_PRESENT          1      /**< SAMS70Q21 does provide a MPU */
292#define __NVIC_PRIO_BITS       3      /**< SAMS70Q21 uses 3 Bits for the Priority Levels */
293#define __FPU_PRESENT          1      /**< SAMS70Q21 does provide a FPU                */
294#define __FPU_DP               1      /**< SAMS70Q21 Double precision FPU              */
295#define __ICACHE_PRESENT       1      /**< SAMS70Q21 does provide an Instruction Cache */
296#define __DCACHE_PRESENT       1      /**< SAMS70Q21 does provide a Data Cache         */
297#define __DTCM_PRESENT         1      /**< SAMS70Q21 does provide a Data TCM           */
298#define __ITCM_PRESENT         1      /**< SAMS70Q21 does provide an Instruction TCM   */
299#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
300
301/*
302 * \brief CMSIS includes
303 */
304
305#include <core_cm7.h>
306#if !defined DONT_USE_CMSIS_INIT
307#include "system_sams70.h"
308#endif /* DONT_USE_CMSIS_INIT */
309
310/*@}*/
311
312/* ************************************************************************** */
313/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q21 */
314/* ************************************************************************** */
315/** \addtogroup SAMS70Q21_api Peripheral Software API */
316/*@{*/
317
318#include "component/component_acc.h"
319#include "component/component_aes.h"
320#include "component/component_afec.h"
321#include "component/component_chipid.h"
322#include "component/component_dacc.h"
323#include "component/component_efc.h"
324#include "component/component_gpbr.h"
325#include "component/component_hsmci.h"
326#include "component/component_icm.h"
327#include "component/component_isi.h"
328#include "component/component_matrix.h"
329#include "component/component_pio.h"
330#include "component/component_pmc.h"
331#include "component/component_pwm.h"
332#include "component/component_qspi.h"
333#include "component/component_rstc.h"
334#include "component/component_rswdt.h"
335#include "component/component_rtc.h"
336#include "component/component_rtt.h"
337#include "component/component_sdramc.h"
338#include "component/component_smc.h"
339#include "component/component_spi.h"
340#include "component/component_ssc.h"
341#include "component/component_supc.h"
342#include "component/component_tc.h"
343#include "component/component_trng.h"
344#include "component/component_twihs.h"
345#include "component/component_uart.h"
346#include "component/component_usart.h"
347#include "component/component_usbhs.h"
348#include "component/component_utmi.h"
349#include "component/component_wdt.h"
350#include "component/component_xdmac.h"
351/*@}*/
352
353#ifndef __rtems__
354/* ************************************************************************** */
355/*   REGISTER ACCESS DEFINITIONS FOR SAMS70Q21 */
356/* ************************************************************************** */
357/** \addtogroup SAMS70Q21_reg Registers Access Definitions */
358/*@{*/
359
360#include "instance/instance_hsmci.h"
361#include "instance/instance_ssc.h"
362#include "instance/instance_spi0.h"
363#include "instance/instance_tc0.h"
364#include "instance/instance_tc1.h"
365#include "instance/instance_tc2.h"
366#include "instance/instance_twihs0.h"
367#include "instance/instance_twihs1.h"
368#include "instance/instance_pwm0.h"
369#include "instance/instance_usart0.h"
370#include "instance/instance_usart1.h"
371#include "instance/instance_usart2.h"
372#include "instance/instance_usbhs.h"
373#include "instance/instance_afec0.h"
374#include "instance/instance_dacc.h"
375#include "instance/instance_acc.h"
376#include "instance/instance_icm.h"
377#include "instance/instance_isi.h"
378#include "instance/instance_tc3.h"
379#include "instance/instance_spi1.h"
380#include "instance/instance_pwm1.h"
381#include "instance/instance_twihs2.h"
382#include "instance/instance_afec1.h"
383#include "instance/instance_aes.h"
384#include "instance/instance_trng.h"
385#include "instance/instance_xdmac.h"
386#include "instance/instance_qspi.h"
387#include "instance/instance_smc.h"
388#include "instance/instance_sdramc.h"
389#include "instance/instance_matrix.h"
390#include "instance/instance_utmi.h"
391#include "instance/instance_pmc.h"
392#include "instance/instance_uart0.h"
393#include "instance/instance_chipid.h"
394#include "instance/instance_uart1.h"
395#include "instance/instance_efc.h"
396#include "instance/instance_pioa.h"
397#include "instance/instance_piob.h"
398#include "instance/instance_pioc.h"
399#include "instance/instance_piod.h"
400#include "instance/instance_pioe.h"
401#include "instance/instance_rstc.h"
402#include "instance/instance_supc.h"
403#include "instance/instance_rtt.h"
404#include "instance/instance_wdt.h"
405#include "instance/instance_rtc.h"
406#include "instance/instance_gpbr.h"
407#include "instance/instance_rswdt.h"
408#include "instance/instance_uart2.h"
409#include "instance/instance_uart3.h"
410#include "instance/instance_uart4.h"
411/*@}*/
412#endif /* __rtems__ */
413
414/* ************************************************************************** */
415/*   PERIPHERAL ID DEFINITIONS FOR SAMS70Q21 */
416/* ************************************************************************** */
417/** \addtogroup SAMS70Q21_id Peripheral Ids Definitions */
418/*@{*/
419
420#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
421#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
422#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
423#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
424#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
425#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
426#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
427#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
428#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
429#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
430#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
431#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
432#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
433#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
434#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
435#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
436#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
437#define ID_PIOE   (17) /**< \brief Parallel I/O Controller E (PIOE) */
438#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
439#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
440#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
441#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
442#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
443#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
444#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
445#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
446#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
447#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
448#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
449#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
450#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
451#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
452#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
453#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
454#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
455#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
456#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
457#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
458#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
459#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
460#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
461#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
462#define ID_TC6    (47) /**< \brief Timer/Counter 6 (TC6) */
463#define ID_TC7    (48) /**< \brief Timer/Counter 7 (TC7) */
464#define ID_TC8    (49) /**< \brief Timer/Counter 8 (TC8) */
465#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
466#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
467#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
468#define ID_AES    (56) /**< \brief AES (AES) */
469#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
470#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
471#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
472#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
473#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
474#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
475
476#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
477/*@}*/
478
479/* ************************************************************************** */
480/*   BASE ADDRESS DEFINITIONS FOR SAMS70Q21 */
481/* ************************************************************************** */
482/** \addtogroup SAMS70Q21_base Peripheral Base Address Definitions */
483/*@{*/
484
485#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
486#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
487#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
488#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
489#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
490#define TC1    (0x40010000U) /**< \brief (TC1   ) Base Address */
491#define TC2    (0x40014000U) /**< \brief (TC2   ) Base Address */
492#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
493#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
494#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
495#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
496#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
497#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
498#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
499#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
500#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
501#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
502#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
503#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
504#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
505#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
506#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
507#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
508#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
509#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
510#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
511#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
512#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
513#define SMC    (0x40080000U) /**< \brief (SMC   ) Base Address */
514#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
515#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
516#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
517#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
518#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
519#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
520#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
521#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
522#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
523#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
524#define PIOC   (0x400E1200U) /**< \brief (PIOC  ) Base Address */
525#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
526#define PIOE   (0x400E1600U) /**< \brief (PIOE  ) Base Address */
527#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
528#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
529#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
530#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
531#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
532#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
533#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
534#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
535#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
536#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
537#else
538#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
539#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
540#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
541#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
542#define TC1    ((Tc     *)0x40010000U) /**< \brief (TC1   ) Base Address */
543#define TC2    ((Tc     *)0x40014000U) /**< \brief (TC2   ) Base Address */
544#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
545#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
546#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
547#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
548#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
549#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
550#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
551#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
552#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
553#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
554#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
555#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
556#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
557#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
558#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
559#define TWIHS2 ((Twihs  *)0x40060000U) /**< \brief (TWIHS2) Base Address */
560#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
561#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
562#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
563#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
564#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
565#define SMC    ((Smc    *)0x40080000U) /**< \brief (SMC   ) Base Address */
566#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
567#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
568#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
569#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
570#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
571#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
572#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
573#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
574#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
575#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
576#define PIOC   ((Pio    *)0x400E1200U) /**< \brief (PIOC  ) Base Address */
577#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
578#define PIOE   ((Pio    *)0x400E1600U) /**< \brief (PIOE  ) Base Address */
579#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
580#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
581#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
582#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
583#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
584#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
585#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
586#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
587#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
588#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
589#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
590/*@}*/
591
592/* ************************************************************************** */
593/*   PIO DEFINITIONS FOR SAMS70Q21 */
594/* ************************************************************************** */
595/** \addtogroup SAMS70Q21_pio Peripheral Pio Definitions */
596/*@{*/
597
598#include "pio/pio_sams70q21.h"
599/*@}*/
600
601/* ************************************************************************** */
602/*   MEMORY MAPPING DEFINITIONS FOR SAMS70Q21 */
603/* ************************************************************************** */
604
605#define IFLASH_SIZE             (0x200000u)
606#define IFLASH_PAGE_SIZE        (512u)
607#define IFLASH_LOCK_REGION_SIZE (8192u)
608#define IFLASH_NB_OF_PAGES      (4096u)
609#define IFLASH_NB_OF_LOCK_BITS  (128u)
610#define IRAM_SIZE               (0x60000u)
611
612#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
613#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
614#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
615#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
616#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
617#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
618#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
619#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
620#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
621#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
622#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
623#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
624
625/* ************************************************************************** */
626/*   MISCELLANEOUS DEFINITIONS FOR SAMS70Q21 */
627/* ************************************************************************** */
628
629#define CHIP_JTAGID (0x05B3D03FUL)
630#define CHIP_CIDR   (0xA1120E00UL)
631#define CHIP_EXID   (0x00000002UL)
632
633/* ************************************************************************** */
634/*   ELECTRICAL DEFINITIONS FOR SAMS70Q21 */
635/* ************************************************************************** */
636
637/* %ATMEL_ELECTRICAL% */
638
639/* Device characteristics */
640#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
641#define CHIP_FREQ_SLCK_RC               (32000UL)
642#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
643#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
644#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
645#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
646#define CHIP_FREQ_CPU_MAX               (120000000UL)
647#define CHIP_FREQ_XTAL_32K              (32768UL)
648#define CHIP_FREQ_XTAL_12M              (12000000UL)
649
650/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
651#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
652#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
653#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
654#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
655#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
656#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
657
658#ifdef __cplusplus
659}
660#endif
661
662/*@}*/
663
664#endif /* _SAMS70Q21_ */
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