source: rtems/bsps/arm/atsam/include/libchip/include/sams70/sams70n19.h @ 71c5552f

5
Last change on this file since 71c5552f was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 30.3 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70N19_
31#define _SAMS70N19_
32
33/** \addtogroup SAMS70N19_definitions SAMS70N19 definitions
34  This file defines all structures and symbols for SAMS70N19:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAMS70N19 */
52/* ************************************************************************** */
53/** \addtogroup SAMS70N19_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAMS70N19 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAMS70N19 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAMS70N19 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAMS70N19 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAMS70N19 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAMS70N19 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAMS70N19 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAMS70N19 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAMS70N19 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAMS70N19 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAMS70N19 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAMS70N19 Parallel I/O Controller B (PIOB) */
82  USART0_IRQn          = 13, /**< 13 SAMS70N19 USART 0 (USART0) */
83  USART1_IRQn          = 14, /**< 14 SAMS70N19 USART 1 (USART1) */
84  USART2_IRQn          = 15, /**< 15 SAMS70N19 USART 2 (USART2) */
85  PIOD_IRQn            = 16, /**< 16 SAMS70N19 Parallel I/O Controller D (PIOD) */
86  HSMCI_IRQn           = 18, /**< 18 SAMS70N19 Multimedia Card Interface (HSMCI) */
87  TWIHS0_IRQn          = 19, /**< 19 SAMS70N19 Two Wire Interface 0 HS (TWIHS0) */
88  TWIHS1_IRQn          = 20, /**< 20 SAMS70N19 Two Wire Interface 1 HS (TWIHS1) */
89  SPI0_IRQn            = 21, /**< 21 SAMS70N19 Serial Peripheral Interface 0 (SPI0) */
90  SSC_IRQn             = 22, /**< 22 SAMS70N19 Synchronous Serial Controller (SSC) */
91  TC0_IRQn             = 23, /**< 23 SAMS70N19 Timer/Counter 0 (TC0) */
92  TC1_IRQn             = 24, /**< 24 SAMS70N19 Timer/Counter 1 (TC1) */
93  TC2_IRQn             = 25, /**< 25 SAMS70N19 Timer/Counter 2 (TC2) */
94  AFEC0_IRQn           = 29, /**< 29 SAMS70N19 Analog Front End 0 (AFEC0) */
95  DACC_IRQn            = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */
96  PWM0_IRQn            = 31, /**< 31 SAMS70N19 Pulse Width Modulation 0 (PWM0) */
97  ICM_IRQn             = 32, /**< 32 SAMS70N19 Integrity Check Monitor (ICM) */
98  ACC_IRQn             = 33, /**< 33 SAMS70N19 Analog Comparator (ACC) */
99  USBHS_IRQn           = 34, /**< 34 SAMS70N19 USB Host / Device Controller (USBHS) */
100  AFEC1_IRQn           = 40, /**< 40 SAMS70N19 Analog Front End 1 (AFEC1) */
101  TWIHS2_IRQn          = 41, /**< 41 SAMS70N19 Two Wire Interface 2 HS (TWIHS2) */
102  SPI1_IRQn            = 42, /**< 42 SAMS70N19 Serial Peripheral Interface 1 (SPI1) */
103  QSPI_IRQn            = 43, /**< 43 SAMS70N19 Quad I/O Serial Peripheral Interface (QSPI) */
104  UART2_IRQn           = 44, /**< 44 SAMS70N19 UART 2 (UART2) */
105  UART3_IRQn           = 45, /**< 45 SAMS70N19 UART 3 (UART3) */
106  UART4_IRQn           = 46, /**< 46 SAMS70N19 UART 4 (UART4) */
107  TC9_IRQn             = 50, /**< 50 SAMS70N19 Timer/Counter 9 (TC9) */
108  TC10_IRQn            = 51, /**< 51 SAMS70N19 Timer/Counter 10 (TC10) */
109  TC11_IRQn            = 52, /**< 52 SAMS70N19 Timer/Counter 11 (TC11) */
110  AES_IRQn             = 56, /**< 56 SAMS70N19 AES (AES) */
111  TRNG_IRQn            = 57, /**< 57 SAMS70N19 True Random Generator (TRNG) */
112  XDMAC_IRQn           = 58, /**< 58 SAMS70N19 DMA (XDMAC) */
113  ISI_IRQn             = 59, /**< 59 SAMS70N19 Camera Interface (ISI) */
114  PWM1_IRQn            = 60, /**< 60 SAMS70N19 Pulse Width Modulation 1 (PWM1) */
115  RSWDT_IRQn           = 63, /**< 63 SAMS70N19 Reinforced Secure Watchdog Timer (RSWDT) */
116
117  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
118} IRQn_Type;
119
120typedef struct _DeviceVectors
121{
122  /* Stack pointer */
123  void* pvStack;
124
125  /* Cortex-M handlers */
126  void* pfnReset_Handler;
127  void* pfnNMI_Handler;
128  void* pfnHardFault_Handler;
129  void* pfnMemManage_Handler;
130  void* pfnBusFault_Handler;
131  void* pfnUsageFault_Handler;
132  void* pfnReserved1_Handler;
133  void* pfnReserved2_Handler;
134  void* pfnReserved3_Handler;
135  void* pfnReserved4_Handler;
136  void* pfnSVC_Handler;
137  void* pfnDebugMon_Handler;
138  void* pfnReserved5_Handler;
139  void* pfnPendSV_Handler;
140  void* pfnSysTick_Handler;
141
142  /* Peripheral handlers */
143  void* pfnSUPC_Handler;   /*  0 Supply Controller */
144  void* pfnRSTC_Handler;   /*  1 Reset Controller */
145  void* pfnRTC_Handler;    /*  2 Real Time Clock */
146  void* pfnRTT_Handler;    /*  3 Real Time Timer */
147  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
148  void* pfnPMC_Handler;    /*  5 Power Management Controller */
149  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
150  void* pfnUART0_Handler;  /*  7 UART 0 */
151  void* pfnUART1_Handler;  /*  8 UART 1 */
152  void* pvReserved9;
153  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
154  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
155  void* pvReserved12;
156  void* pfnUSART0_Handler; /* 13 USART 0 */
157  void* pfnUSART1_Handler; /* 14 USART 1 */
158  void* pfnUSART2_Handler; /* 15 USART 2 */
159  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
160  void* pvReserved17;
161  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
162  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
163  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
164  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
165  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
166  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
167  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
168  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
169  void* pvReserved26;
170  void* pvReserved27;
171  void* pvReserved28;
172  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
173  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
174  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
175  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
176  void* pfnACC_Handler;    /* 33 Analog Comparator */
177  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
178  void* pvReserved35;
179  void* pvReserved36;
180  void* pvReserved37;
181  void* pvReserved38;
182  void* pvReserved39;
183  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
184  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
185  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
186  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
187  void* pfnUART2_Handler;  /* 44 UART 2 */
188  void* pfnUART3_Handler;  /* 45 UART 3 */
189  void* pfnUART4_Handler;  /* 46 UART 4 */
190  void* pvReserved47;
191  void* pvReserved48;
192  void* pvReserved49;
193  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
194  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
195  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
196  void* pvReserved53;
197  void* pvReserved54;
198  void* pvReserved55;
199  void* pfnAES_Handler;    /* 56 AES */
200  void* pfnTRNG_Handler;   /* 57 True Random Generator */
201  void* pfnXDMAC_Handler;  /* 58 DMA */
202  void* pfnISI_Handler;    /* 59 Camera Interface */
203  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
204  void* pvReserved61;
205  void* pvReserved62;
206  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
207} DeviceVectors;
208
209/* Cortex-M7 core handlers */
210void Reset_Handler      ( void );
211void NMI_Handler        ( void );
212void HardFault_Handler  ( void );
213void MemManage_Handler  ( void );
214void BusFault_Handler   ( void );
215void UsageFault_Handler ( void );
216void SVC_Handler        ( void );
217void DebugMon_Handler   ( void );
218void PendSV_Handler     ( void );
219void SysTick_Handler    ( void );
220
221/* Peripherals handlers */
222void ACC_Handler        ( void );
223void AES_Handler        ( void );
224void AFEC0_Handler      ( void );
225void AFEC1_Handler      ( void );
226void DACC_Handler       ( void );
227void EFC_Handler        ( void );
228void HSMCI_Handler      ( void );
229void ICM_Handler        ( void );
230void ISI_Handler        ( void );
231void PIOA_Handler       ( void );
232void PIOB_Handler       ( void );
233void PIOD_Handler       ( void );
234void PMC_Handler        ( void );
235void PWM0_Handler       ( void );
236void PWM1_Handler       ( void );
237void QSPI_Handler       ( void );
238void RSTC_Handler       ( void );
239void RSWDT_Handler      ( void );
240void RTC_Handler        ( void );
241void RTT_Handler        ( void );
242void SPI0_Handler       ( void );
243void SPI1_Handler       ( void );
244void SSC_Handler        ( void );
245void SUPC_Handler       ( void );
246void TC0_Handler        ( void );
247void TC1_Handler        ( void );
248void TC2_Handler        ( void );
249void TC9_Handler        ( void );
250void TC10_Handler       ( void );
251void TC11_Handler       ( void );
252void TRNG_Handler       ( void );
253void TWIHS0_Handler     ( void );
254void TWIHS1_Handler     ( void );
255void TWIHS2_Handler     ( void );
256void UART0_Handler      ( void );
257void UART1_Handler      ( void );
258void UART2_Handler      ( void );
259void UART3_Handler      ( void );
260void UART4_Handler      ( void );
261void USART0_Handler     ( void );
262void USART1_Handler     ( void );
263void USART2_Handler     ( void );
264void USBHS_Handler      ( void );
265void WDT_Handler        ( void );
266void XDMAC_Handler      ( void );
267
268/**
269 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
270 */
271
272#define __CM7_REV              0x0000 /**< SAMS70N19 core revision number ([15:8] revision number, [7:0] patch number) */
273#define __MPU_PRESENT          1      /**< SAMS70N19 does provide a MPU */
274#define __NVIC_PRIO_BITS       3      /**< SAMS70N19 uses 3 Bits for the Priority Levels */
275#define __FPU_PRESENT          1      /**< SAMS70N19 does provide a FPU                */
276#define __FPU_DP               1      /**< SAMS70N19 Double precision FPU              */
277#define __ICACHE_PRESENT       1      /**< SAMS70N19 does provide an Instruction Cache */
278#define __DCACHE_PRESENT       1      /**< SAMS70N19 does provide a Data Cache         */
279#define __DTCM_PRESENT         1      /**< SAMS70N19 does provide a Data TCM           */
280#define __ITCM_PRESENT         1      /**< SAMS70N19 does provide an Instruction TCM   */
281#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
282
283/*
284 * \brief CMSIS includes
285 */
286
287#include <core_cm7.h>
288#if !defined DONT_USE_CMSIS_INIT
289#include "system_sams70.h"
290#endif /* DONT_USE_CMSIS_INIT */
291
292/*@}*/
293
294/* ************************************************************************** */
295/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N19 */
296/* ************************************************************************** */
297/** \addtogroup SAMS70N19_api Peripheral Software API */
298/*@{*/
299
300#include "component/component_acc.h"
301#include "component/component_aes.h"
302#include "component/component_afec.h"
303#include "component/component_chipid.h"
304#include "component/component_dacc.h"
305#include "component/component_efc.h"
306#include "component/component_gpbr.h"
307#include "component/component_hsmci.h"
308#include "component/component_icm.h"
309#include "component/component_isi.h"
310#include "component/component_matrix.h"
311#include "component/component_pio.h"
312#include "component/component_pmc.h"
313#include "component/component_pwm.h"
314#include "component/component_qspi.h"
315#include "component/component_rstc.h"
316#include "component/component_rswdt.h"
317#include "component/component_rtc.h"
318#include "component/component_rtt.h"
319#include "component/component_spi.h"
320#include "component/component_ssc.h"
321#include "component/component_supc.h"
322#include "component/component_tc.h"
323#include "component/component_trng.h"
324#include "component/component_twihs.h"
325#include "component/component_uart.h"
326#include "component/component_usart.h"
327#include "component/component_usbhs.h"
328#include "component/component_utmi.h"
329#include "component/component_wdt.h"
330#include "component/component_xdmac.h"
331/*@}*/
332
333#ifndef __rtems__
334/* ************************************************************************** */
335/*   REGISTER ACCESS DEFINITIONS FOR SAMS70N19 */
336/* ************************************************************************** */
337/** \addtogroup SAMS70N19_reg Registers Access Definitions */
338/*@{*/
339
340#include "instance/instance_hsmci.h"
341#include "instance/instance_ssc.h"
342#include "instance/instance_spi0.h"
343#include "instance/instance_tc0.h"
344#include "instance/instance_twihs0.h"
345#include "instance/instance_twihs1.h"
346#include "instance/instance_pwm0.h"
347#include "instance/instance_usart0.h"
348#include "instance/instance_usart1.h"
349#include "instance/instance_usart2.h"
350#include "instance/instance_usbhs.h"
351#include "instance/instance_afec0.h"
352#include "instance/instance_dacc.h"
353#include "instance/instance_acc.h"
354#include "instance/instance_icm.h"
355#include "instance/instance_isi.h"
356#include "instance/instance_tc3.h"
357#include "instance/instance_spi1.h"
358#include "instance/instance_pwm1.h"
359#include "instance/instance_twihs2.h"
360#include "instance/instance_afec1.h"
361#include "instance/instance_aes.h"
362#include "instance/instance_trng.h"
363#include "instance/instance_xdmac.h"
364#include "instance/instance_qspi.h"
365#include "instance/instance_matrix.h"
366#include "instance/instance_utmi.h"
367#include "instance/instance_pmc.h"
368#include "instance/instance_uart0.h"
369#include "instance/instance_chipid.h"
370#include "instance/instance_uart1.h"
371#include "instance/instance_efc.h"
372#include "instance/instance_pioa.h"
373#include "instance/instance_piob.h"
374#include "instance/instance_piod.h"
375#include "instance/instance_rstc.h"
376#include "instance/instance_supc.h"
377#include "instance/instance_rtt.h"
378#include "instance/instance_wdt.h"
379#include "instance/instance_rtc.h"
380#include "instance/instance_gpbr.h"
381#include "instance/instance_rswdt.h"
382#include "instance/instance_uart2.h"
383#include "instance/instance_uart3.h"
384#include "instance/instance_uart4.h"
385/*@}*/
386#endif /* __rtems__ */
387
388/* ************************************************************************** */
389/*   PERIPHERAL ID DEFINITIONS FOR SAMS70N19 */
390/* ************************************************************************** */
391/** \addtogroup SAMS70N19_id Peripheral Ids Definitions */
392/*@{*/
393
394#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
395#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
396#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
397#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
398#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
399#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
400#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
401#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
402#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
403#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
404#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
405#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
406#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
407#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
408#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
409#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
410#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
411#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
412#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
413#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
414#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
415#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
416#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
417#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
418#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
419#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
420#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
421#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
422#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
423#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
424#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
425#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
426#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
427#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
428#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
429#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
430#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
431#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
432#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
433#define ID_AES    (56) /**< \brief AES (AES) */
434#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
435#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
436#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
437#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
438#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
439
440#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
441/*@}*/
442
443/* ************************************************************************** */
444/*   BASE ADDRESS DEFINITIONS FOR SAMS70N19 */
445/* ************************************************************************** */
446/** \addtogroup SAMS70N19_base Peripheral Base Address Definitions */
447/*@{*/
448
449#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
450#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
451#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
452#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
453#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
454#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
455#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
456#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
457#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
458#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
459#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
460#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
461#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
462#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
463#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
464#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
465#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
466#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
467#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
468#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
469#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
470#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
471#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
472#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
473#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
474#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
475#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
476#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
477#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
478#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
479#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
480#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
481#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
482#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
483#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
484#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
485#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
486#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
487#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
488#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
489#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
490#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
491#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
492#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
493#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
494#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
495#else
496#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
497#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
498#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
499#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
500#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
501#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
502#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
503#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
504#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
505#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
506#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
507#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
508#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
509#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
510#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
511#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
512#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
513#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
514#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
515#define TWIHS2 ((Twihs  *)0x40060000U) /**< \brief (TWIHS2) Base Address */
516#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
517#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
518#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
519#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
520#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
521#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
522#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
523#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
524#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
525#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
526#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
527#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
528#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
529#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
530#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
531#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
532#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
533#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
534#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
535#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
536#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
537#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
538#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
539#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
540#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
541#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
542/*@}*/
543
544/* ************************************************************************** */
545/*   PIO DEFINITIONS FOR SAMS70N19 */
546/* ************************************************************************** */
547/** \addtogroup SAMS70N19_pio Peripheral Pio Definitions */
548/*@{*/
549
550#include "pio/pio_sams70n19.h"
551/*@}*/
552
553/* ************************************************************************** */
554/*   MEMORY MAPPING DEFINITIONS FOR SAMS70N19 */
555/* ************************************************************************** */
556
557#define IFLASH_SIZE             (0x80000u)
558#define IFLASH_PAGE_SIZE        (512u)
559#define IFLASH_LOCK_REGION_SIZE (8192u)
560#define IFLASH_NB_OF_PAGES      (1024u)
561#define IFLASH_NB_OF_LOCK_BITS  (32u)
562#define IRAM_SIZE               (0x40000u)
563
564#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
565#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
566#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
567#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
568#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
569#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
570#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
571#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
572#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
573#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
574#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
575#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
576
577/* ************************************************************************** */
578/*   MISCELLANEOUS DEFINITIONS FOR SAMS70N19 */
579/* ************************************************************************** */
580
581#define CHIP_JTAGID (0x05B3D03FUL)
582#define CHIP_CIDR   (0xA11D0A00UL)
583#define CHIP_EXID   (0x00000001UL)
584
585/* ************************************************************************** */
586/*   ELECTRICAL DEFINITIONS FOR SAMS70N19 */
587/* ************************************************************************** */
588
589/* %ATMEL_ELECTRICAL% */
590
591/* Device characteristics */
592#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
593#define CHIP_FREQ_SLCK_RC               (32000UL)
594#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
595#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
596#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
597#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
598#define CHIP_FREQ_CPU_MAX               (120000000UL)
599#define CHIP_FREQ_XTAL_32K              (32768UL)
600#define CHIP_FREQ_XTAL_12M              (12000000UL)
601
602/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
603#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
604#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
605#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
606#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
607#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
608#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
609
610#ifdef __cplusplus
611}
612#endif
613
614/*@}*/
615
616#endif /* _SAMS70N19_ */
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