source: rtems/bsps/arm/atsam/include/libchip/include/sams70/sams70j19.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 29.9 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70J19_
31#define _SAMS70J19_
32
33/** \addtogroup SAMS70J19_definitions SAMS70J19 definitions
34  This file defines all structures and symbols for SAMS70J19:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAMS70J19 */
52/* ************************************************************************** */
53/** \addtogroup SAMS70J19_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAMS70J19 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAMS70J19 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAMS70J19 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAMS70J19 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAMS70J19 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAMS70J19 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAMS70J19 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAMS70J19 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAMS70J19 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAMS70J19 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAMS70J19 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAMS70J19 Parallel I/O Controller B (PIOB) */
82  USART0_IRQn          = 13, /**< 13 SAMS70J19 USART 0 (USART0) */
83  USART1_IRQn          = 14, /**< 14 SAMS70J19 USART 1 (USART1) */
84  USART2_IRQn          = 15, /**< 15 SAMS70J19 USART 2 (USART2) */
85  PIOD_IRQn            = 16, /**< 16 SAMS70J19 Parallel I/O Controller D (PIOD) */
86  HSMCI_IRQn           = 18, /**< 18 SAMS70J19 Multimedia Card Interface (HSMCI) */
87  TWIHS0_IRQn          = 19, /**< 19 SAMS70J19 Two Wire Interface 0 HS (TWIHS0) */
88  TWIHS1_IRQn          = 20, /**< 20 SAMS70J19 Two Wire Interface 1 HS (TWIHS1) */
89  SPI0_IRQn            = 21, /**< 21 SAMS70J19 Serial Peripheral Interface 0 (SPI0) */
90  SSC_IRQn             = 22, /**< 22 SAMS70J19 Synchronous Serial Controller (SSC) */
91  TC0_IRQn             = 23, /**< 23 SAMS70J19 Timer/Counter 0 (TC0) */
92  TC1_IRQn             = 24, /**< 24 SAMS70J19 Timer/Counter 1 (TC1) */
93  TC2_IRQn             = 25, /**< 25 SAMS70J19 Timer/Counter 2 (TC2) */
94  AFEC0_IRQn           = 29, /**< 29 SAMS70J19 Analog Front End 0 (AFEC0) */
95  DACC_IRQn            = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */
96  PWM0_IRQn            = 31, /**< 31 SAMS70J19 Pulse Width Modulation 0 (PWM0) */
97  ICM_IRQn             = 32, /**< 32 SAMS70J19 Integrity Check Monitor (ICM) */
98  ACC_IRQn             = 33, /**< 33 SAMS70J19 Analog Comparator (ACC) */
99  USBHS_IRQn           = 34, /**< 34 SAMS70J19 USB Host / Device Controller (USBHS) */
100  AFEC1_IRQn           = 40, /**< 40 SAMS70J19 Analog Front End 1 (AFEC1) */
101  SPI1_IRQn            = 42, /**< 42 SAMS70J19 Serial Peripheral Interface 1 (SPI1) */
102  QSPI_IRQn            = 43, /**< 43 SAMS70J19 Quad I/O Serial Peripheral Interface (QSPI) */
103  UART2_IRQn           = 44, /**< 44 SAMS70J19 UART 2 (UART2) */
104  UART3_IRQn           = 45, /**< 45 SAMS70J19 UART 3 (UART3) */
105  UART4_IRQn           = 46, /**< 46 SAMS70J19 UART 4 (UART4) */
106  TC9_IRQn             = 50, /**< 50 SAMS70J19 Timer/Counter 9 (TC9) */
107  TC10_IRQn            = 51, /**< 51 SAMS70J19 Timer/Counter 10 (TC10) */
108  TC11_IRQn            = 52, /**< 52 SAMS70J19 Timer/Counter 11 (TC11) */
109  AES_IRQn             = 56, /**< 56 SAMS70J19 AES (AES) */
110  TRNG_IRQn            = 57, /**< 57 SAMS70J19 True Random Generator (TRNG) */
111  XDMAC_IRQn           = 58, /**< 58 SAMS70J19 DMA (XDMAC) */
112  ISI_IRQn             = 59, /**< 59 SAMS70J19 Camera Interface (ISI) */
113  PWM1_IRQn            = 60, /**< 60 SAMS70J19 Pulse Width Modulation 1 (PWM1) */
114  RSWDT_IRQn           = 63, /**< 63 SAMS70J19 Reinforced Secure Watchdog Timer (RSWDT) */
115
116  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
117} IRQn_Type;
118
119typedef struct _DeviceVectors
120{
121  /* Stack pointer */
122  void* pvStack;
123
124  /* Cortex-M handlers */
125  void* pfnReset_Handler;
126  void* pfnNMI_Handler;
127  void* pfnHardFault_Handler;
128  void* pfnMemManage_Handler;
129  void* pfnBusFault_Handler;
130  void* pfnUsageFault_Handler;
131  void* pfnReserved1_Handler;
132  void* pfnReserved2_Handler;
133  void* pfnReserved3_Handler;
134  void* pfnReserved4_Handler;
135  void* pfnSVC_Handler;
136  void* pfnDebugMon_Handler;
137  void* pfnReserved5_Handler;
138  void* pfnPendSV_Handler;
139  void* pfnSysTick_Handler;
140
141  /* Peripheral handlers */
142  void* pfnSUPC_Handler;   /*  0 Supply Controller */
143  void* pfnRSTC_Handler;   /*  1 Reset Controller */
144  void* pfnRTC_Handler;    /*  2 Real Time Clock */
145  void* pfnRTT_Handler;    /*  3 Real Time Timer */
146  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
147  void* pfnPMC_Handler;    /*  5 Power Management Controller */
148  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
149  void* pfnUART0_Handler;  /*  7 UART 0 */
150  void* pfnUART1_Handler;  /*  8 UART 1 */
151  void* pvReserved9;
152  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
153  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
154  void* pvReserved12;
155  void* pfnUSART0_Handler; /* 13 USART 0 */
156  void* pfnUSART1_Handler; /* 14 USART 1 */
157  void* pfnUSART2_Handler; /* 15 USART 2 */
158  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
159  void* pvReserved17;
160  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
161  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
162  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
163  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
164  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
165  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
166  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
167  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
168  void* pvReserved26;
169  void* pvReserved27;
170  void* pvReserved28;
171  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
172  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
173  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
174  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
175  void* pfnACC_Handler;    /* 33 Analog Comparator */
176  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
177  void* pvReserved35;
178  void* pvReserved36;
179  void* pvReserved37;
180  void* pvReserved38;
181  void* pvReserved39;
182  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
183  void* pvReserved41;
184  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
185  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
186  void* pfnUART2_Handler;  /* 44 UART 2 */
187  void* pfnUART3_Handler;  /* 45 UART 3 */
188  void* pfnUART4_Handler;  /* 46 UART 4 */
189  void* pvReserved47;
190  void* pvReserved48;
191  void* pvReserved49;
192  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
193  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
194  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
195  void* pvReserved53;
196  void* pvReserved54;
197  void* pvReserved55;
198  void* pfnAES_Handler;    /* 56 AES */
199  void* pfnTRNG_Handler;   /* 57 True Random Generator */
200  void* pfnXDMAC_Handler;  /* 58 DMA */
201  void* pfnISI_Handler;    /* 59 Camera Interface */
202  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
203  void* pvReserved61;
204  void* pvReserved62;
205  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
206} DeviceVectors;
207
208/* Cortex-M7 core handlers */
209void Reset_Handler      ( void );
210void NMI_Handler        ( void );
211void HardFault_Handler  ( void );
212void MemManage_Handler  ( void );
213void BusFault_Handler   ( void );
214void UsageFault_Handler ( void );
215void SVC_Handler        ( void );
216void DebugMon_Handler   ( void );
217void PendSV_Handler     ( void );
218void SysTick_Handler    ( void );
219
220/* Peripherals handlers */
221void ACC_Handler        ( void );
222void AES_Handler        ( void );
223void AFEC0_Handler      ( void );
224void AFEC1_Handler      ( void );
225void DACC_Handler       ( void );
226void EFC_Handler        ( void );
227void HSMCI_Handler      ( void );
228void ICM_Handler        ( void );
229void ISI_Handler        ( void );
230void PIOA_Handler       ( void );
231void PIOB_Handler       ( void );
232void PIOD_Handler       ( void );
233void PMC_Handler        ( void );
234void PWM0_Handler       ( void );
235void PWM1_Handler       ( void );
236void QSPI_Handler       ( void );
237void RSTC_Handler       ( void );
238void RSWDT_Handler      ( void );
239void RTC_Handler        ( void );
240void RTT_Handler        ( void );
241void SPI0_Handler       ( void );
242void SPI1_Handler       ( void );
243void SSC_Handler        ( void );
244void SUPC_Handler       ( void );
245void TC0_Handler        ( void );
246void TC1_Handler        ( void );
247void TC2_Handler        ( void );
248void TC9_Handler        ( void );
249void TC10_Handler       ( void );
250void TC11_Handler       ( void );
251void TRNG_Handler       ( void );
252void TWIHS0_Handler     ( void );
253void TWIHS1_Handler     ( void );
254void UART0_Handler      ( void );
255void UART1_Handler      ( void );
256void UART2_Handler      ( void );
257void UART3_Handler      ( void );
258void UART4_Handler      ( void );
259void USART0_Handler     ( void );
260void USART1_Handler     ( void );
261void USART2_Handler     ( void );
262void USBHS_Handler      ( void );
263void WDT_Handler        ( void );
264void XDMAC_Handler      ( void );
265
266/**
267 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
268 */
269
270#define __CM7_REV              0x0000 /**< SAMS70J19 core revision number ([15:8] revision number, [7:0] patch number) */
271#define __MPU_PRESENT          1      /**< SAMS70J19 does provide a MPU */
272#define __NVIC_PRIO_BITS       3      /**< SAMS70J19 uses 3 Bits for the Priority Levels */
273#define __FPU_PRESENT          1      /**< SAMS70J19 does provide a FPU                */
274#define __FPU_DP               1      /**< SAMS70J19 Double precision FPU              */
275#define __ICACHE_PRESENT       1      /**< SAMS70J19 does provide an Instruction Cache */
276#define __DCACHE_PRESENT       1      /**< SAMS70J19 does provide a Data Cache         */
277#define __DTCM_PRESENT         1      /**< SAMS70J19 does provide a Data TCM           */
278#define __ITCM_PRESENT         1      /**< SAMS70J19 does provide an Instruction TCM   */
279#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
280
281/*
282 * \brief CMSIS includes
283 */
284
285#include <core_cm7.h>
286#if !defined DONT_USE_CMSIS_INIT
287#include "system_sams70.h"
288#endif /* DONT_USE_CMSIS_INIT */
289
290/*@}*/
291
292/* ************************************************************************** */
293/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J19 */
294/* ************************************************************************** */
295/** \addtogroup SAMS70J19_api Peripheral Software API */
296/*@{*/
297
298#include "component/component_acc.h"
299#include "component/component_aes.h"
300#include "component/component_afec.h"
301#include "component/component_chipid.h"
302#include "component/component_dacc.h"
303#include "component/component_efc.h"
304#include "component/component_gpbr.h"
305#include "component/component_hsmci.h"
306#include "component/component_icm.h"
307#include "component/component_isi.h"
308#include "component/component_matrix.h"
309#include "component/component_pio.h"
310#include "component/component_pmc.h"
311#include "component/component_pwm.h"
312#include "component/component_qspi.h"
313#include "component/component_rstc.h"
314#include "component/component_rswdt.h"
315#include "component/component_rtc.h"
316#include "component/component_rtt.h"
317#include "component/component_spi.h"
318#include "component/component_ssc.h"
319#include "component/component_supc.h"
320#include "component/component_tc.h"
321#include "component/component_trng.h"
322#include "component/component_twihs.h"
323#include "component/component_uart.h"
324#include "component/component_usart.h"
325#include "component/component_usbhs.h"
326#include "component/component_utmi.h"
327#include "component/component_wdt.h"
328#include "component/component_xdmac.h"
329/*@}*/
330
331#ifndef __rtems__
332/* ************************************************************************** */
333/*   REGISTER ACCESS DEFINITIONS FOR SAMS70J19 */
334/* ************************************************************************** */
335/** \addtogroup SAMS70J19_reg Registers Access Definitions */
336/*@{*/
337
338#include "instance/instance_hsmci.h"
339#include "instance/instance_ssc.h"
340#include "instance/instance_spi0.h"
341#include "instance/instance_tc0.h"
342#include "instance/instance_twihs0.h"
343#include "instance/instance_twihs1.h"
344#include "instance/instance_pwm0.h"
345#include "instance/instance_usart0.h"
346#include "instance/instance_usart1.h"
347#include "instance/instance_usart2.h"
348#include "instance/instance_usbhs.h"
349#include "instance/instance_afec0.h"
350#include "instance/instance_dacc.h"
351#include "instance/instance_acc.h"
352#include "instance/instance_icm.h"
353#include "instance/instance_isi.h"
354#include "instance/instance_tc3.h"
355#include "instance/instance_spi1.h"
356#include "instance/instance_pwm1.h"
357#include "instance/instance_afec1.h"
358#include "instance/instance_aes.h"
359#include "instance/instance_trng.h"
360#include "instance/instance_xdmac.h"
361#include "instance/instance_qspi.h"
362#include "instance/instance_matrix.h"
363#include "instance/instance_utmi.h"
364#include "instance/instance_pmc.h"
365#include "instance/instance_uart0.h"
366#include "instance/instance_chipid.h"
367#include "instance/instance_uart1.h"
368#include "instance/instance_efc.h"
369#include "instance/instance_pioa.h"
370#include "instance/instance_piob.h"
371#include "instance/instance_piod.h"
372#include "instance/instance_rstc.h"
373#include "instance/instance_supc.h"
374#include "instance/instance_rtt.h"
375#include "instance/instance_wdt.h"
376#include "instance/instance_rtc.h"
377#include "instance/instance_gpbr.h"
378#include "instance/instance_rswdt.h"
379#include "instance/instance_uart2.h"
380#include "instance/instance_uart3.h"
381#include "instance/instance_uart4.h"
382/*@}*/
383#endif /* __rtems__ */
384
385/* ************************************************************************** */
386/*   PERIPHERAL ID DEFINITIONS FOR SAMS70J19 */
387/* ************************************************************************** */
388/** \addtogroup SAMS70J19_id Peripheral Ids Definitions */
389/*@{*/
390
391#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
392#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
393#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
394#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
395#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
396#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
397#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
398#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
399#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
400#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
401#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
402#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
403#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
404#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
405#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
406#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
407#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
408#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
409#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
410#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
411#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
412#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
413#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
414#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
415#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
416#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
417#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
418#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
419#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
420#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
421#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
422#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
423#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
424#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
425#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
426#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
427#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
428#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
429#define ID_AES    (56) /**< \brief AES (AES) */
430#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
431#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
432#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
433#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
434#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
435
436#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
437/*@}*/
438
439/* ************************************************************************** */
440/*   BASE ADDRESS DEFINITIONS FOR SAMS70J19 */
441/* ************************************************************************** */
442/** \addtogroup SAMS70J19_base Peripheral Base Address Definitions */
443/*@{*/
444
445#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
446#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
447#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
448#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
449#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
450#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
451#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
452#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
453#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
454#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
455#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
456#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
457#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
458#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
459#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
460#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
461#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
462#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
463#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
464#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
465#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
466#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
467#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
468#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
469#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
470#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
471#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
472#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
473#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
474#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
475#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
476#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
477#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
478#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
479#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
480#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
481#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
482#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
483#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
484#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
485#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
486#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
487#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
488#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
489#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
490#else
491#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
492#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
493#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
494#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
495#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
496#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
497#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
498#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
499#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
500#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
501#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
502#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
503#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
504#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
505#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
506#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
507#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
508#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
509#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
510#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
511#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
512#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
513#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
514#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
515#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
516#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
517#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
518#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
519#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
520#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
521#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
522#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
523#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
524#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
525#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
526#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
527#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
528#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
529#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
530#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
531#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
532#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
533#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
534#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
535#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
536/*@}*/
537
538/* ************************************************************************** */
539/*   PIO DEFINITIONS FOR SAMS70J19 */
540/* ************************************************************************** */
541/** \addtogroup SAMS70J19_pio Peripheral Pio Definitions */
542/*@{*/
543
544#include "pio/pio_sams70j19.h"
545/*@}*/
546
547/* ************************************************************************** */
548/*   MEMORY MAPPING DEFINITIONS FOR SAMS70J19 */
549/* ************************************************************************** */
550
551#define IFLASH_SIZE             (0x80000u)
552#define IFLASH_PAGE_SIZE        (512u)
553#define IFLASH_LOCK_REGION_SIZE (8192u)
554#define IFLASH_NB_OF_PAGES      (1024u)
555#define IFLASH_NB_OF_LOCK_BITS  (32u)
556#define IRAM_SIZE               (0x40000u)
557
558#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
559#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
560#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
561#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
562#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
563#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
564#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
565#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
566#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
567#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
568#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
569#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
570
571/* ************************************************************************** */
572/*   MISCELLANEOUS DEFINITIONS FOR SAMS70J19 */
573/* ************************************************************************** */
574
575#define CHIP_JTAGID (0x05B3D03FUL)
576#define CHIP_CIDR   (0xA11D0A00UL)
577#define CHIP_EXID   (0x00000000UL)
578
579/* ************************************************************************** */
580/*   ELECTRICAL DEFINITIONS FOR SAMS70J19 */
581/* ************************************************************************** */
582
583/* %ATMEL_ELECTRICAL% */
584
585/* Device characteristics */
586#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
587#define CHIP_FREQ_SLCK_RC               (32000UL)
588#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
589#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
590#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
591#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
592#define CHIP_FREQ_CPU_MAX               (120000000UL)
593#define CHIP_FREQ_XTAL_32K              (32768UL)
594#define CHIP_FREQ_XTAL_12M              (12000000UL)
595
596/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
597#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
598#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
599#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
600#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
601#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
602#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
603
604#ifdef __cplusplus
605}
606#endif
607
608/*@}*/
609
610#endif /* _SAMS70J19_ */
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