source: rtems/bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 20.2 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70_TWIHS_COMPONENT_
31#define _SAMS70_TWIHS_COMPONENT_
32
33/* ============================================================================= */
34/**  SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */
35/* ============================================================================= */
36/** \addtogroup SAMS70_TWIHS Two-wire Interface High Speed */
37/*@{*/
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40/** \brief Twihs hardware registers */
41typedef struct {
42  __O  uint32_t TWIHS_CR;      /**< \brief (Twihs Offset: 0x00) Control Register */
43  __IO uint32_t TWIHS_MMR;     /**< \brief (Twihs Offset: 0x04) Master Mode Register */
44  __IO uint32_t TWIHS_SMR;     /**< \brief (Twihs Offset: 0x08) Slave Mode Register */
45  __IO uint32_t TWIHS_IADR;    /**< \brief (Twihs Offset: 0x0C) Internal Address Register */
46  __IO uint32_t TWIHS_CWGR;    /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */
47  __I  uint32_t Reserved1[3];
48  __I  uint32_t TWIHS_SR;      /**< \brief (Twihs Offset: 0x20) Status Register */
49  __O  uint32_t TWIHS_IER;     /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */
50  __O  uint32_t TWIHS_IDR;     /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */
51  __I  uint32_t TWIHS_IMR;     /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */
52  __I  uint32_t TWIHS_RHR;     /**< \brief (Twihs Offset: 0x30) Receive Holding Register */
53  __O  uint32_t TWIHS_THR;     /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */
54  __IO uint32_t TWIHS_SMBTR;   /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */
55  __I  uint32_t Reserved2[2];
56  __IO uint32_t TWIHS_FILTR;   /**< \brief (Twihs Offset: 0x44) Filter Register */
57  __I  uint32_t Reserved3[1];
58  __IO uint32_t TWIHS_SWMR;    /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */
59  __I  uint32_t Reserved4[37];
60  __IO uint32_t TWIHS_WPMR;    /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */
61  __I  uint32_t TWIHS_WPSR;    /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */
62} Twihs;
63#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
64/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */
65#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */
66#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */
67#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */
68#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */
69#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */
70#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */
71#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */
72#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */
73#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */
74#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */
75#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */
76#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */
77#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */
78#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */
79#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */
80#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */
81/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */
82#define TWIHS_MMR_IADRSZ_Pos 8
83#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */
84#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))
85#define   TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */
86#define   TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */
87#define   TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */
88#define   TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */
89#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */
90#define TWIHS_MMR_DADR_Pos 16
91#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */
92#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))
93/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */
94#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */
95#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */
96#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */
97#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */
98#define TWIHS_SMR_MASK_Pos 8
99#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */
100#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))
101#define TWIHS_SMR_SADR_Pos 16
102#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */
103#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))
104#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */
105#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */
106#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */
107#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */
108/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */
109#define TWIHS_IADR_IADR_Pos 0
110#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */
111#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))
112/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */
113#define TWIHS_CWGR_CLDIV_Pos 0
114#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */
115#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))
116#define TWIHS_CWGR_CHDIV_Pos 8
117#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */
118#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))
119#define TWIHS_CWGR_CKDIV_Pos 16
120#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */
121#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))
122#define TWIHS_CWGR_HOLD_Pos 24
123#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */
124#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))
125/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */
126#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */
127#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */
128#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */
129#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */
130#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */
131#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */
132#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */
133#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */
134#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */
135#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */
136#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */
137#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */
138#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */
139#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */
140#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */
141#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */
142#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */
143#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */
144#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */
145/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */
146#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */
147#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */
148#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */
149#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */
150#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */
151#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */
152#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */
153#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */
154#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */
155#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */
156#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */
157#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */
158#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */
159#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */
160#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */
161#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */
162/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */
163#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */
164#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */
165#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */
166#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */
167#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */
168#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */
169#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */
170#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */
171#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */
172#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */
173#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */
174#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */
175#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */
176#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */
177#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */
178#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */
179/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */
180#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */
181#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */
182#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */
183#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */
184#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */
185#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */
186#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */
187#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */
188#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */
189#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */
190#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */
191#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */
192#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */
193#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */
194#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */
195#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */
196/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */
197#define TWIHS_RHR_RXDATA_Pos 0
198#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */
199/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */
200#define TWIHS_THR_TXDATA_Pos 0
201#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */
202#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))
203/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */
204#define TWIHS_SMBTR_PRESC_Pos 0
205#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */
206#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))
207#define TWIHS_SMBTR_TLOWS_Pos 8
208#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */
209#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))
210#define TWIHS_SMBTR_TLOWM_Pos 16
211#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */
212#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))
213#define TWIHS_SMBTR_THMAX_Pos 24
214#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */
215#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))
216/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */
217#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */
218#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */
219#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */
220#define TWIHS_FILTR_THRES_Pos 8
221#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */
222#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))
223/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */
224#define TWIHS_SWMR_SADR1_Pos 0
225#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */
226#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))
227#define TWIHS_SWMR_SADR2_Pos 8
228#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */
229#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))
230#define TWIHS_SWMR_SADR3_Pos 16
231#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */
232#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))
233#define TWIHS_SWMR_DATAM_Pos 24
234#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */
235#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))
236/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */
237#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */
238#define TWIHS_WPMR_WPKEY_Pos 8
239#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */
240#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))
241#define   TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
242/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */
243#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */
244#define TWIHS_WPSR_WPVSRC_Pos 8
245#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */
246
247/*@}*/
248
249
250#endif /* _SAMS70_TWIHS_COMPONENT_ */
Note: See TracBrowser for help on using the repository browser.