1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | #ifndef _SAMS70_TWIHS_COMPONENT_ |
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31 | #define _SAMS70_TWIHS_COMPONENT_ |
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32 | |
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33 | /* ============================================================================= */ |
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34 | /** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ |
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35 | /* ============================================================================= */ |
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36 | /** \addtogroup SAMS70_TWIHS Two-wire Interface High Speed */ |
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37 | /*@{*/ |
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38 | |
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39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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40 | /** \brief Twihs hardware registers */ |
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41 | typedef struct { |
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42 | __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ |
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43 | __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ |
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44 | __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ |
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45 | __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ |
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46 | __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ |
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47 | __I uint32_t Reserved1[3]; |
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48 | __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ |
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49 | __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ |
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50 | __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ |
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51 | __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ |
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52 | __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ |
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53 | __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ |
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54 | __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ |
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55 | __I uint32_t Reserved2[2]; |
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56 | __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ |
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57 | __I uint32_t Reserved3[1]; |
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58 | __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ |
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59 | __I uint32_t Reserved4[37]; |
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60 | __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ |
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61 | __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ |
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62 | } Twihs; |
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63 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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64 | /* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ |
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65 | #define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ |
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66 | #define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ |
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67 | #define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ |
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68 | #define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ |
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69 | #define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ |
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70 | #define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ |
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71 | #define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ |
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72 | #define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ |
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73 | #define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ |
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74 | #define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ |
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75 | #define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ |
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76 | #define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ |
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77 | #define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ |
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78 | #define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ |
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79 | #define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ |
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80 | #define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ |
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81 | /* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ |
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82 | #define TWIHS_MMR_IADRSZ_Pos 8 |
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83 | #define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ |
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84 | #define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) |
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85 | #define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ |
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86 | #define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ |
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87 | #define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ |
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88 | #define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ |
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89 | #define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ |
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90 | #define TWIHS_MMR_DADR_Pos 16 |
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91 | #define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ |
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92 | #define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) |
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93 | /* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ |
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94 | #define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ |
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95 | #define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ |
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96 | #define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ |
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97 | #define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ |
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98 | #define TWIHS_SMR_MASK_Pos 8 |
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99 | #define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ |
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100 | #define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) |
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101 | #define TWIHS_SMR_SADR_Pos 16 |
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102 | #define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ |
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103 | #define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) |
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104 | #define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ |
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105 | #define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ |
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106 | #define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ |
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107 | #define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ |
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108 | /* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ |
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109 | #define TWIHS_IADR_IADR_Pos 0 |
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110 | #define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ |
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111 | #define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) |
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112 | /* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ |
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113 | #define TWIHS_CWGR_CLDIV_Pos 0 |
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114 | #define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ |
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115 | #define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) |
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116 | #define TWIHS_CWGR_CHDIV_Pos 8 |
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117 | #define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ |
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118 | #define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) |
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119 | #define TWIHS_CWGR_CKDIV_Pos 16 |
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120 | #define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ |
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121 | #define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) |
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122 | #define TWIHS_CWGR_HOLD_Pos 24 |
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123 | #define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ |
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124 | #define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) |
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125 | /* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ |
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126 | #define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ |
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127 | #define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ |
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128 | #define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ |
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129 | #define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ |
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130 | #define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ |
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131 | #define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ |
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132 | #define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ |
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133 | #define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ |
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134 | #define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ |
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135 | #define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ |
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136 | #define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ |
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137 | #define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ |
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138 | #define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ |
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139 | #define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ |
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140 | #define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ |
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141 | #define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ |
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142 | #define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ |
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143 | #define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL Line Value */ |
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144 | #define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA Line Value */ |
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145 | /* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ |
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146 | #define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ |
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147 | #define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ |
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148 | #define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ |
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149 | #define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ |
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150 | #define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ |
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151 | #define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ |
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152 | #define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ |
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153 | #define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ |
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154 | #define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ |
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155 | #define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ |
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156 | #define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ |
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157 | #define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ |
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158 | #define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ |
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159 | #define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ |
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160 | #define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ |
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161 | #define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ |
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162 | /* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ |
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163 | #define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ |
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164 | #define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ |
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165 | #define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ |
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166 | #define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ |
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167 | #define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ |
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168 | #define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ |
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169 | #define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ |
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170 | #define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ |
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171 | #define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ |
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172 | #define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ |
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173 | #define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ |
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174 | #define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ |
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175 | #define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ |
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176 | #define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ |
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177 | #define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ |
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178 | #define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ |
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179 | /* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ |
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180 | #define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ |
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181 | #define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ |
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182 | #define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ |
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183 | #define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ |
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184 | #define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ |
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185 | #define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ |
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186 | #define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ |
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187 | #define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ |
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188 | #define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ |
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189 | #define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ |
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190 | #define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ |
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191 | #define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ |
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192 | #define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ |
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193 | #define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ |
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194 | #define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ |
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195 | #define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ |
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196 | /* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ |
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197 | #define TWIHS_RHR_RXDATA_Pos 0 |
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198 | #define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ |
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199 | /* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ |
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200 | #define TWIHS_THR_TXDATA_Pos 0 |
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201 | #define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ |
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202 | #define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) |
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203 | /* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ |
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204 | #define TWIHS_SMBTR_PRESC_Pos 0 |
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205 | #define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ |
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206 | #define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) |
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207 | #define TWIHS_SMBTR_TLOWS_Pos 8 |
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208 | #define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ |
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209 | #define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) |
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210 | #define TWIHS_SMBTR_TLOWM_Pos 16 |
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211 | #define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ |
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212 | #define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) |
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213 | #define TWIHS_SMBTR_THMAX_Pos 24 |
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214 | #define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ |
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215 | #define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) |
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216 | /* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ |
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217 | #define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ |
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218 | #define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ |
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219 | #define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ |
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220 | #define TWIHS_FILTR_THRES_Pos 8 |
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221 | #define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ |
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222 | #define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) |
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223 | /* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ |
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224 | #define TWIHS_SWMR_SADR1_Pos 0 |
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225 | #define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ |
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226 | #define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) |
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227 | #define TWIHS_SWMR_SADR2_Pos 8 |
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228 | #define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ |
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229 | #define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) |
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230 | #define TWIHS_SWMR_SADR3_Pos 16 |
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231 | #define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ |
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232 | #define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) |
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233 | #define TWIHS_SWMR_DATAM_Pos 24 |
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234 | #define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ |
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235 | #define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) |
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236 | /* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ |
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237 | #define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ |
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238 | #define TWIHS_WPMR_WPKEY_Pos 8 |
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239 | #define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ |
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240 | #define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) |
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241 | #define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ |
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242 | /* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ |
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243 | #define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ |
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244 | #define TWIHS_WPSR_WPVSRC_Pos 8 |
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245 | #define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ |
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246 | |
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247 | /*@}*/ |
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248 | |
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249 | |
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250 | #endif /* _SAMS70_TWIHS_COMPONENT_ */ |
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