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component_matrix.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 50.3 KB

Line
1	/* ---------------------------------------------------------------------------- */
2	/* Atmel Microcontroller Software Support */
3	/* SAM Software Package License */
4	/* ---------------------------------------------------------------------------- */
5	/* Copyright (c) 2015, Atmel Corporation */
6	/* */
7	/* All rights reserved. */
8	/* */
9	/* Redistribution and use in source and binary forms, with or without */
10	/* modification, are permitted provided that the following condition is met: */
11	/* */
12	/* - Redistributions of source code must retain the above copyright notice, */
13	/* this list of conditions and the disclaimer below. */
14	/* */
15	/* Atmel's name may not be used to endorse or promote products derived from */
16	/* this software without specific prior written permission. */
17	/* */
18	/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19	/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20	/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21	/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22	/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23	/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24	/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25	/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26	/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27	/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28	/* ---------------------------------------------------------------------------- */
29
30	#ifndef _SAMS70_MATRIX_COMPONENT_
31	#define _SAMS70_MATRIX_COMPONENT_
32
33	/* ============================================================================= */
34	/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
35	/* ============================================================================= */
36	/** \addtogroup SAMS70_MATRIX AHB Bus Matrix */
37	/@{/
38
39	#if !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
40	/** \brief Matrix hardware registers */
41	typedef struct {
42	__IO uint32_t MATRIX_MCFG0; /*< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 /
43	__IO uint32_t MATRIX_MCFG1; /*< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 /
44	__IO uint32_t MATRIX_MCFG2; /*< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 /
45	__IO uint32_t MATRIX_MCFG3; /*< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 /
46	__IO uint32_t MATRIX_MCFG4; /*< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 /
47	__IO uint32_t MATRIX_MCFG5; /*< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 /
48	__IO uint32_t MATRIX_MCFG6; /*< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 /
49	__I uint32_t Reserved1[1];
50	__IO uint32_t MATRIX_MCFG8; /*< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 /
51	__I uint32_t Reserved2[7];
52	__IO uint32_t MATRIX_SCFG[9]; /*< \brief (Matrix Offset: 0x0040) Slave Configuration Register /
53	__I uint32_t Reserved3[7];
54	__IO uint32_t MATRIX_PRAS0; /*< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 /
55	__IO uint32_t MATRIX_PRBS0; /*< \brief (Matrix Offset: 0x0084) Priority Register B for Slave 0 /
56	__IO uint32_t MATRIX_PRAS1; /*< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 /
57	__IO uint32_t MATRIX_PRBS1; /*< \brief (Matrix Offset: 0x008C) Priority Register B for Slave 1 /
58	__IO uint32_t MATRIX_PRAS2; /*< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 /
59	__IO uint32_t MATRIX_PRBS2; /*< \brief (Matrix Offset: 0x0094) Priority Register B for Slave 2 /
60	__IO uint32_t MATRIX_PRAS3; /*< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 /
61	__IO uint32_t MATRIX_PRBS3; /*< \brief (Matrix Offset: 0x009C) Priority Register B for Slave 3 /
62	__IO uint32_t MATRIX_PRAS4; /*< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 /
63	__IO uint32_t MATRIX_PRBS4; /*< \brief (Matrix Offset: 0x00A4) Priority Register B for Slave 4 /
64	__IO uint32_t MATRIX_PRAS5; /*< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 /
65	__IO uint32_t MATRIX_PRBS5; /*< \brief (Matrix Offset: 0x00AC) Priority Register B for Slave 5 /
66	__IO uint32_t MATRIX_PRAS6; /*< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 /
67	__IO uint32_t MATRIX_PRBS6; /*< \brief (Matrix Offset: 0x00B4) Priority Register B for Slave 6 /
68	__IO uint32_t MATRIX_PRAS7; /*< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 /
69	__IO uint32_t MATRIX_PRBS7; /*< \brief (Matrix Offset: 0x00BC) Priority Register B for Slave 7 /
70	__IO uint32_t MATRIX_PRAS8; /*< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 /
71	__IO uint32_t MATRIX_PRBS8; /*< \brief (Matrix Offset: 0x00C4) Priority Register B for Slave 8 /
72	__I uint32_t Reserved4[14];
73	__IO uint32_t MATRIX_MRCR; /*< \brief (Matrix Offset: 0x0100) Master Remap Control Register /
74	__I uint32_t Reserved5[4];
75	__IO uint32_t CCFG_SYSIO; /*< \brief (Matrix Offset: 0x0114) System I/O Configuration Register /
76	__I uint32_t Reserved6[3];
77	__IO uint32_t CCFG_SMCNFCS; /*< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register /
78	__I uint32_t Reserved7[47];
79	__IO uint32_t MATRIX_WPMR; /*< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register /
80	__I uint32_t MATRIX_WPSR; /*< \brief (Matrix Offset: 0x01E8) Write Protection Status Register /
81	} Matrix;
82	#endif /* !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)) */
83	/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
84	#define MATRIX_MCFG0_ULBT_Pos 0
85	#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /*< \brief (MATRIX_MCFG0) Undefined Length Burst Type /
86	#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
87	#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
88	#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
89	#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
90	#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
91	#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
92	#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
93	#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
94	#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
95	/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
96	#define MATRIX_MCFG1_ULBT_Pos 0
97	#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /*< \brief (MATRIX_MCFG1) Undefined Length Burst Type /
98	#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
99	#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
100	#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
101	#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
102	#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
103	#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
104	#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
105	#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
106	#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
107	/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
108	#define MATRIX_MCFG2_ULBT_Pos 0
109	#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /*< \brief (MATRIX_MCFG2) Undefined Length Burst Type /
110	#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
111	#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
112	#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
113	#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
114	#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
115	#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
116	#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
117	#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
118	#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
119	/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
120	#define MATRIX_MCFG3_ULBT_Pos 0
121	#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /*< \brief (MATRIX_MCFG3) Undefined Length Burst Type /
122	#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
123	#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
124	#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
125	#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
126	#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
127	#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
128	#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
129	#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
130	#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
131	/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
132	#define MATRIX_MCFG4_ULBT_Pos 0
133	#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /*< \brief (MATRIX_MCFG4) Undefined Length Burst Type /
134	#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
135	#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
136	#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
137	#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
138	#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
139	#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
140	#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
141	#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
142	#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
143	/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
144	#define MATRIX_MCFG5_ULBT_Pos 0
145	#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /*< \brief (MATRIX_MCFG5) Undefined Length Burst Type /
146	#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
147	#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
148	#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
149	#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
150	#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
151	#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
152	#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
153	#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
154	#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
155	/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
156	#define MATRIX_MCFG6_ULBT_Pos 0
157	#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /*< \brief (MATRIX_MCFG6) Undefined Length Burst Type /
158	#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
159	#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
160	#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
161	#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
162	#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
163	#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
164	#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
165	#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
166	#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
167	/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
168	#define MATRIX_MCFG8_ULBT_Pos 0
169	#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /*< \brief (MATRIX_MCFG8) Undefined Length Burst Type /
170	#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
171	#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /*< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. /
172	#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /*< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. /
173	#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /*< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. /
174	#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /*< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. /
175	#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /*< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. /
176	#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /*< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. /
177	#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /*< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. /
178	#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /*< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. /
179	/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
180	#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
181	#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /*< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters /
182	#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
183	#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
184	#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /*< \brief (MATRIX_SCFG[9]) Default Master Type /
185	#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
186	#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /*< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. /
187	#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /*< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. /
188	#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /*< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. /
189	#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
190	#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /*< \brief (MATRIX_SCFG[9]) Fixed Default Master /
191	#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
192	/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
193	#define MATRIX_PRAS0_M0PR_Pos 0
194	#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /*< \brief (MATRIX_PRAS0) Master 0 Priority /
195	#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
196	#define MATRIX_PRAS0_M1PR_Pos 4
197	#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /*< \brief (MATRIX_PRAS0) Master 1 Priority /
198	#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
199	#define MATRIX_PRAS0_M2PR_Pos 8
200	#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /*< \brief (MATRIX_PRAS0) Master 2 Priority /
201	#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
202	#define MATRIX_PRAS0_M3PR_Pos 12
203	#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /*< \brief (MATRIX_PRAS0) Master 3 Priority /
204	#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
205	#define MATRIX_PRAS0_M4PR_Pos 16
206	#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /*< \brief (MATRIX_PRAS0) Master 4 Priority /
207	#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
208	#define MATRIX_PRAS0_M5PR_Pos 20
209	#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /*< \brief (MATRIX_PRAS0) Master 5 Priority /
210	#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
211	#define MATRIX_PRAS0_M6PR_Pos 24
212	#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /*< \brief (MATRIX_PRAS0) Master 6 Priority /
213	#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos)))
214	/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */
215	#define MATRIX_PRBS0_M8PR_Pos 0
216	#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos) /*< \brief (MATRIX_PRBS0) Master 8 Priority /
217	#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos)))
218	/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
219	#define MATRIX_PRAS1_M0PR_Pos 0
220	#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /*< \brief (MATRIX_PRAS1) Master 0 Priority /
221	#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
222	#define MATRIX_PRAS1_M1PR_Pos 4
223	#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /*< \brief (MATRIX_PRAS1) Master 1 Priority /
224	#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
225	#define MATRIX_PRAS1_M2PR_Pos 8
226	#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /*< \brief (MATRIX_PRAS1) Master 2 Priority /
227	#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
228	#define MATRIX_PRAS1_M3PR_Pos 12
229	#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /*< \brief (MATRIX_PRAS1) Master 3 Priority /
230	#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
231	#define MATRIX_PRAS1_M4PR_Pos 16
232	#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /*< \brief (MATRIX_PRAS1) Master 4 Priority /
233	#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
234	#define MATRIX_PRAS1_M5PR_Pos 20
235	#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /*< \brief (MATRIX_PRAS1) Master 5 Priority /
236	#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
237	#define MATRIX_PRAS1_M6PR_Pos 24
238	#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /*< \brief (MATRIX_PRAS1) Master 6 Priority /
239	#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos)))
240	/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */
241	#define MATRIX_PRBS1_M8PR_Pos 0
242	#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos) /*< \brief (MATRIX_PRBS1) Master 8 Priority /
243	#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos)))
244	/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
245	#define MATRIX_PRAS2_M0PR_Pos 0
246	#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /*< \brief (MATRIX_PRAS2) Master 0 Priority /
247	#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
248	#define MATRIX_PRAS2_M1PR_Pos 4
249	#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /*< \brief (MATRIX_PRAS2) Master 1 Priority /
250	#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
251	#define MATRIX_PRAS2_M2PR_Pos 8
252	#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /*< \brief (MATRIX_PRAS2) Master 2 Priority /
253	#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
254	#define MATRIX_PRAS2_M3PR_Pos 12
255	#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /*< \brief (MATRIX_PRAS2) Master 3 Priority /
256	#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
257	#define MATRIX_PRAS2_M4PR_Pos 16
258	#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /*< \brief (MATRIX_PRAS2) Master 4 Priority /
259	#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
260	#define MATRIX_PRAS2_M5PR_Pos 20
261	#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /*< \brief (MATRIX_PRAS2) Master 5 Priority /
262	#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
263	#define MATRIX_PRAS2_M6PR_Pos 24
264	#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /*< \brief (MATRIX_PRAS2) Master 6 Priority /
265	#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos)))
266	/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */
267	#define MATRIX_PRBS2_M8PR_Pos 0
268	#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos) /*< \brief (MATRIX_PRBS2) Master 8 Priority /
269	#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos)))
270	/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
271	#define MATRIX_PRAS3_M0PR_Pos 0
272	#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /*< \brief (MATRIX_PRAS3) Master 0 Priority /
273	#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
274	#define MATRIX_PRAS3_M1PR_Pos 4
275	#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /*< \brief (MATRIX_PRAS3) Master 1 Priority /
276	#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
277	#define MATRIX_PRAS3_M2PR_Pos 8
278	#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /*< \brief (MATRIX_PRAS3) Master 2 Priority /
279	#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
280	#define MATRIX_PRAS3_M3PR_Pos 12
281	#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /*< \brief (MATRIX_PRAS3) Master 3 Priority /
282	#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
283	#define MATRIX_PRAS3_M4PR_Pos 16
284	#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /*< \brief (MATRIX_PRAS3) Master 4 Priority /
285	#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
286	#define MATRIX_PRAS3_M5PR_Pos 20
287	#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /*< \brief (MATRIX_PRAS3) Master 5 Priority /
288	#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
289	#define MATRIX_PRAS3_M6PR_Pos 24
290	#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /*< \brief (MATRIX_PRAS3) Master 6 Priority /
291	#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos)))
292	/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */
293	#define MATRIX_PRBS3_M8PR_Pos 0
294	#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos) /*< \brief (MATRIX_PRBS3) Master 8 Priority /
295	#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos)))
296	/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
297	#define MATRIX_PRAS4_M0PR_Pos 0
298	#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /*< \brief (MATRIX_PRAS4) Master 0 Priority /
299	#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
300	#define MATRIX_PRAS4_M1PR_Pos 4
301	#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /*< \brief (MATRIX_PRAS4) Master 1 Priority /
302	#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
303	#define MATRIX_PRAS4_M2PR_Pos 8
304	#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /*< \brief (MATRIX_PRAS4) Master 2 Priority /
305	#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
306	#define MATRIX_PRAS4_M3PR_Pos 12
307	#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /*< \brief (MATRIX_PRAS4) Master 3 Priority /
308	#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
309	#define MATRIX_PRAS4_M4PR_Pos 16
310	#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /*< \brief (MATRIX_PRAS4) Master 4 Priority /
311	#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
312	#define MATRIX_PRAS4_M5PR_Pos 20
313	#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /*< \brief (MATRIX_PRAS4) Master 5 Priority /
314	#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
315	#define MATRIX_PRAS4_M6PR_Pos 24
316	#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /*< \brief (MATRIX_PRAS4) Master 6 Priority /
317	#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos)))
318	/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */
319	#define MATRIX_PRBS4_M8PR_Pos 0
320	#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos) /*< \brief (MATRIX_PRBS4) Master 8 Priority /
321	#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos)))
322	/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
323	#define MATRIX_PRAS5_M0PR_Pos 0
324	#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /*< \brief (MATRIX_PRAS5) Master 0 Priority /
325	#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
326	#define MATRIX_PRAS5_M1PR_Pos 4
327	#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /*< \brief (MATRIX_PRAS5) Master 1 Priority /
328	#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
329	#define MATRIX_PRAS5_M2PR_Pos 8
330	#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /*< \brief (MATRIX_PRAS5) Master 2 Priority /
331	#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
332	#define MATRIX_PRAS5_M3PR_Pos 12
333	#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /*< \brief (MATRIX_PRAS5) Master 3 Priority /
334	#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
335	#define MATRIX_PRAS5_M4PR_Pos 16
336	#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /*< \brief (MATRIX_PRAS5) Master 4 Priority /
337	#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
338	#define MATRIX_PRAS5_M5PR_Pos 20
339	#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /*< \brief (MATRIX_PRAS5) Master 5 Priority /
340	#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
341	#define MATRIX_PRAS5_M6PR_Pos 24
342	#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /*< \brief (MATRIX_PRAS5) Master 6 Priority /
343	#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos)))
344	/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */
345	#define MATRIX_PRBS5_M8PR_Pos 0
346	#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos) /*< \brief (MATRIX_PRBS5) Master 8 Priority /
347	#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos)))
348	/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
349	#define MATRIX_PRAS6_M0PR_Pos 0
350	#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /*< \brief (MATRIX_PRAS6) Master 0 Priority /
351	#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
352	#define MATRIX_PRAS6_M1PR_Pos 4
353	#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /*< \brief (MATRIX_PRAS6) Master 1 Priority /
354	#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
355	#define MATRIX_PRAS6_M2PR_Pos 8
356	#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /*< \brief (MATRIX_PRAS6) Master 2 Priority /
357	#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
358	#define MATRIX_PRAS6_M3PR_Pos 12
359	#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /*< \brief (MATRIX_PRAS6) Master 3 Priority /
360	#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
361	#define MATRIX_PRAS6_M4PR_Pos 16
362	#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /*< \brief (MATRIX_PRAS6) Master 4 Priority /
363	#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
364	#define MATRIX_PRAS6_M5PR_Pos 20
365	#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /*< \brief (MATRIX_PRAS6) Master 5 Priority /
366	#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
367	#define MATRIX_PRAS6_M6PR_Pos 24
368	#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos) /*< \brief (MATRIX_PRAS6) Master 6 Priority /
369	#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos)))
370	/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */
371	#define MATRIX_PRBS6_M8PR_Pos 0
372	#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos) /*< \brief (MATRIX_PRBS6) Master 8 Priority /
373	#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos)))
374	/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
375	#define MATRIX_PRAS7_M0PR_Pos 0
376	#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /*< \brief (MATRIX_PRAS7) Master 0 Priority /
377	#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
378	#define MATRIX_PRAS7_M1PR_Pos 4
379	#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /*< \brief (MATRIX_PRAS7) Master 1 Priority /
380	#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
381	#define MATRIX_PRAS7_M2PR_Pos 8
382	#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /*< \brief (MATRIX_PRAS7) Master 2 Priority /
383	#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
384	#define MATRIX_PRAS7_M3PR_Pos 12
385	#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /*< \brief (MATRIX_PRAS7) Master 3 Priority /
386	#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
387	#define MATRIX_PRAS7_M4PR_Pos 16
388	#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /*< \brief (MATRIX_PRAS7) Master 4 Priority /
389	#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
390	#define MATRIX_PRAS7_M5PR_Pos 20
391	#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /*< \brief (MATRIX_PRAS7) Master 5 Priority /
392	#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
393	#define MATRIX_PRAS7_M6PR_Pos 24
394	#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos) /*< \brief (MATRIX_PRAS7) Master 6 Priority /
395	#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos)))
396	/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */
397	#define MATRIX_PRBS7_M8PR_Pos 0
398	#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos) /*< \brief (MATRIX_PRBS7) Master 8 Priority /
399	#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos)))
400	/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
401	#define MATRIX_PRAS8_M0PR_Pos 0
402	#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /*< \brief (MATRIX_PRAS8) Master 0 Priority /
403	#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
404	#define MATRIX_PRAS8_M1PR_Pos 4
405	#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /*< \brief (MATRIX_PRAS8) Master 1 Priority /
406	#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
407	#define MATRIX_PRAS8_M2PR_Pos 8
408	#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /*< \brief (MATRIX_PRAS8) Master 2 Priority /
409	#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
410	#define MATRIX_PRAS8_M3PR_Pos 12
411	#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /*< \brief (MATRIX_PRAS8) Master 3 Priority /
412	#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
413	#define MATRIX_PRAS8_M4PR_Pos 16
414	#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /*< \brief (MATRIX_PRAS8) Master 4 Priority /
415	#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
416	#define MATRIX_PRAS8_M5PR_Pos 20
417	#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /*< \brief (MATRIX_PRAS8) Master 5 Priority /
418	#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
419	#define MATRIX_PRAS8_M6PR_Pos 24
420	#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos) /*< \brief (MATRIX_PRAS8) Master 6 Priority /
421	#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos)))
422	/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */
423	#define MATRIX_PRBS8_M8PR_Pos 0
424	#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos) /*< \brief (MATRIX_PRBS8) Master 8 Priority /
425	#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos)))
426	/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
427	#define MATRIX_MRCR_RCB0 (0x1u << 0) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 /
428	#define MATRIX_MRCR_RCB1 (0x1u << 1) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 /
429	#define MATRIX_MRCR_RCB2 (0x1u << 2) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 /
430	#define MATRIX_MRCR_RCB3 (0x1u << 3) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 /
431	#define MATRIX_MRCR_RCB4 (0x1u << 4) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 /
432	#define MATRIX_MRCR_RCB5 (0x1u << 5) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 /
433	#define MATRIX_MRCR_RCB6 (0x1u << 6) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 /
434	#define MATRIX_MRCR_RCB8 (0x1u << 8) /*< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 /
435	/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */
436	#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /*< \brief (CCFG_SYSIO) PB4 or TDI Assignment /
437	#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /*< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment /
438	#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /*< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment /
439	#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /*< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment /
440	#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /*< \brief (CCFG_SYSIO) PB12 or ERASE Assignment /
441	/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
442	#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /*< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment /
443	#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /*< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment /
444	#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /*< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment /
445	#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /*< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment /
446	#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /*< \brief (CCFG_SMCNFCS) SDRAM Enable /
447	/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
448	#define MATRIX_WPMR_WPEN (0x1u << 0) /*< \brief (MATRIX_WPMR) Write Protection Enable /
449	#define MATRIX_WPMR_WPKEY_Pos 8
450	#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /*< \brief (MATRIX_WPMR) Write Protection Key /
451	#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
452	#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /*< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. /
453	/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
454	#define MATRIX_WPSR_WPVS (0x1u << 0) /*< \brief (MATRIX_WPSR) Write Protection Violation Status /
455	#define MATRIX_WPSR_WPVSRC_Pos 8
456	#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /*< \brief (MATRIX_WPSR) Write Protection Violation Source /
457
458	/@}/
459
460
461	#endif /* _SAMS70_MATRIX_COMPONENT_ */

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source: rtems/bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h @ 2afb22b

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