source: rtems/bsps/arm/atsam/include/libchip/include/same70/same70q20.h @ 71c5552f

5
Last change on this file since 71c5552f was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 34.5 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
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9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70Q20_
31#define _SAME70Q20_
32
33/** \addtogroup SAME70Q20_definitions SAME70Q20 definitions
34  This file defines all structures and symbols for SAME70Q20:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAME70Q20 */
52/* ************************************************************************** */
53/** \addtogroup SAME70Q20_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAME70Q20 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAME70Q20 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAME70Q20 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAME70Q20 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAME70Q20 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAME70Q20 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAME70Q20 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAME70Q20 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAME70Q20 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAME70Q20 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAME70Q20 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAME70Q20 Parallel I/O Controller B (PIOB) */
82  PIOC_IRQn            = 12, /**< 12 SAME70Q20 Parallel I/O Controller C (PIOC) */
83  USART0_IRQn          = 13, /**< 13 SAME70Q20 USART 0 (USART0) */
84  USART1_IRQn          = 14, /**< 14 SAME70Q20 USART 1 (USART1) */
85  USART2_IRQn          = 15, /**< 15 SAME70Q20 USART 2 (USART2) */
86  PIOD_IRQn            = 16, /**< 16 SAME70Q20 Parallel I/O Controller D (PIOD) */
87  PIOE_IRQn            = 17, /**< 17 SAME70Q20 Parallel I/O Controller E (PIOE) */
88  HSMCI_IRQn           = 18, /**< 18 SAME70Q20 Multimedia Card Interface (HSMCI) */
89  TWIHS0_IRQn          = 19, /**< 19 SAME70Q20 Two Wire Interface 0 HS (TWIHS0) */
90  TWIHS1_IRQn          = 20, /**< 20 SAME70Q20 Two Wire Interface 1 HS (TWIHS1) */
91  SPI0_IRQn            = 21, /**< 21 SAME70Q20 Serial Peripheral Interface 0 (SPI0) */
92  SSC_IRQn             = 22, /**< 22 SAME70Q20 Synchronous Serial Controller (SSC) */
93  TC0_IRQn             = 23, /**< 23 SAME70Q20 Timer/Counter 0 (TC0) */
94  TC1_IRQn             = 24, /**< 24 SAME70Q20 Timer/Counter 1 (TC1) */
95  TC2_IRQn             = 25, /**< 25 SAME70Q20 Timer/Counter 2 (TC2) */
96  TC3_IRQn             = 26, /**< 26 SAME70Q20 Timer/Counter 3 (TC3) */
97  TC4_IRQn             = 27, /**< 27 SAME70Q20 Timer/Counter 4 (TC4) */
98  TC5_IRQn             = 28, /**< 28 SAME70Q20 Timer/Counter 5 (TC5) */
99  AFEC0_IRQn           = 29, /**< 29 SAME70Q20 Analog Front End 0 (AFEC0) */
100  DACC_IRQn            = 30, /**< 30 SAME70Q20 Digital To Analog Converter (DACC) */
101  PWM0_IRQn            = 31, /**< 31 SAME70Q20 Pulse Width Modulation 0 (PWM0) */
102  ICM_IRQn             = 32, /**< 32 SAME70Q20 Integrity Check Monitor (ICM) */
103  ACC_IRQn             = 33, /**< 33 SAME70Q20 Analog Comparator (ACC) */
104  USBHS_IRQn           = 34, /**< 34 SAME70Q20 USB Host / Device Controller (USBHS) */
105  MCAN0_IRQn           = 35, /**< 35 SAME70Q20 MCAN Controller 0 (MCAN0) */
106  MCAN1_IRQn           = 37, /**< 37 SAME70Q20 MCAN Controller 1 (MCAN1) */
107  GMAC_IRQn            = 39, /**< 39 SAME70Q20 Ethernet MAC (GMAC) */
108  AFEC1_IRQn           = 40, /**< 40 SAME70Q20 Analog Front End 1 (AFEC1) */
109  TWIHS2_IRQn          = 41, /**< 41 SAME70Q20 Two Wire Interface 2 HS (TWIHS2) */
110  SPI1_IRQn            = 42, /**< 42 SAME70Q20 Serial Peripheral Interface 1 (SPI1) */
111  QSPI_IRQn            = 43, /**< 43 SAME70Q20 Quad I/O Serial Peripheral Interface (QSPI) */
112  UART2_IRQn           = 44, /**< 44 SAME70Q20 UART 2 (UART2) */
113  UART3_IRQn           = 45, /**< 45 SAME70Q20 UART 3 (UART3) */
114  UART4_IRQn           = 46, /**< 46 SAME70Q20 UART 4 (UART4) */
115  TC6_IRQn             = 47, /**< 47 SAME70Q20 Timer/Counter 6 (TC6) */
116  TC7_IRQn             = 48, /**< 48 SAME70Q20 Timer/Counter 7 (TC7) */
117  TC8_IRQn             = 49, /**< 49 SAME70Q20 Timer/Counter 8 (TC8) */
118  TC9_IRQn             = 50, /**< 50 SAME70Q20 Timer/Counter 9 (TC9) */
119  TC10_IRQn            = 51, /**< 51 SAME70Q20 Timer/Counter 10 (TC10) */
120  TC11_IRQn            = 52, /**< 52 SAME70Q20 Timer/Counter 11 (TC11) */
121  AES_IRQn             = 56, /**< 56 SAME70Q20 AES (AES) */
122  TRNG_IRQn            = 57, /**< 57 SAME70Q20 True Random Generator (TRNG) */
123  XDMAC_IRQn           = 58, /**< 58 SAME70Q20 DMA (XDMAC) */
124  ISI_IRQn             = 59, /**< 59 SAME70Q20 Camera Interface (ISI) */
125  PWM1_IRQn            = 60, /**< 60 SAME70Q20 Pulse Width Modulation 1 (PWM1) */
126  SDRAMC_IRQn          = 62, /**< 62 SAME70Q20 SDRAM Controller (SDRAMC) */
127  RSWDT_IRQn           = 63, /**< 63 SAME70Q20 Reinforced Secure Watchdog Timer (RSWDT) */
128
129  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
130} IRQn_Type;
131
132typedef struct _DeviceVectors
133{
134  /* Stack pointer */
135  void* pvStack;
136
137  /* Cortex-M handlers */
138  void* pfnReset_Handler;
139  void* pfnNMI_Handler;
140  void* pfnHardFault_Handler;
141  void* pfnMemManage_Handler;
142  void* pfnBusFault_Handler;
143  void* pfnUsageFault_Handler;
144  void* pfnReserved1_Handler;
145  void* pfnReserved2_Handler;
146  void* pfnReserved3_Handler;
147  void* pfnReserved4_Handler;
148  void* pfnSVC_Handler;
149  void* pfnDebugMon_Handler;
150  void* pfnReserved5_Handler;
151  void* pfnPendSV_Handler;
152  void* pfnSysTick_Handler;
153
154  /* Peripheral handlers */
155  void* pfnSUPC_Handler;   /*  0 Supply Controller */
156  void* pfnRSTC_Handler;   /*  1 Reset Controller */
157  void* pfnRTC_Handler;    /*  2 Real Time Clock */
158  void* pfnRTT_Handler;    /*  3 Real Time Timer */
159  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
160  void* pfnPMC_Handler;    /*  5 Power Management Controller */
161  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
162  void* pfnUART0_Handler;  /*  7 UART 0 */
163  void* pfnUART1_Handler;  /*  8 UART 1 */
164  void* pvReserved9;
165  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
166  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
167  void* pfnPIOC_Handler;   /* 12 Parallel I/O Controller C */
168  void* pfnUSART0_Handler; /* 13 USART 0 */
169  void* pfnUSART1_Handler; /* 14 USART 1 */
170  void* pfnUSART2_Handler; /* 15 USART 2 */
171  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
172  void* pfnPIOE_Handler;   /* 17 Parallel I/O Controller E */
173  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
174  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
175  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
176  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
177  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
178  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
179  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
180  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
181  void* pfnTC3_Handler;    /* 26 Timer/Counter 3 */
182  void* pfnTC4_Handler;    /* 27 Timer/Counter 4 */
183  void* pfnTC5_Handler;    /* 28 Timer/Counter 5 */
184  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
185  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
186  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
187  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
188  void* pfnACC_Handler;    /* 33 Analog Comparator */
189  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
190  void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
191  void* pvReserved36;
192  void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
193  void* pvReserved38;
194  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
195  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
196  void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
197  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
198  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
199  void* pfnUART2_Handler;  /* 44 UART 2 */
200  void* pfnUART3_Handler;  /* 45 UART 3 */
201  void* pfnUART4_Handler;  /* 46 UART 4 */
202  void* pfnTC6_Handler;    /* 47 Timer/Counter 6 */
203  void* pfnTC7_Handler;    /* 48 Timer/Counter 7 */
204  void* pfnTC8_Handler;    /* 49 Timer/Counter 8 */
205  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
206  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
207  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
208  void* pvReserved53;
209  void* pvReserved54;
210  void* pvReserved55;
211  void* pfnAES_Handler;    /* 56 AES */
212  void* pfnTRNG_Handler;   /* 57 True Random Generator */
213  void* pfnXDMAC_Handler;  /* 58 DMA */
214  void* pfnISI_Handler;    /* 59 Camera Interface */
215  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
216  void* pvReserved61;
217  void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
218  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
219} DeviceVectors;
220
221/* Cortex-M7 core handlers */
222void Reset_Handler      ( void );
223void NMI_Handler        ( void );
224void HardFault_Handler  ( void );
225void MemManage_Handler  ( void );
226void BusFault_Handler   ( void );
227void UsageFault_Handler ( void );
228void SVC_Handler        ( void );
229void DebugMon_Handler   ( void );
230void PendSV_Handler     ( void );
231void SysTick_Handler    ( void );
232
233/* Peripherals handlers */
234void ACC_Handler        ( void );
235void AES_Handler        ( void );
236void AFEC0_Handler      ( void );
237void AFEC1_Handler      ( void );
238void DACC_Handler       ( void );
239void EFC_Handler        ( void );
240void GMAC_Handler       ( void );
241void HSMCI_Handler      ( void );
242void ICM_Handler        ( void );
243void ISI_Handler        ( void );
244void MCAN0_Handler      ( void );
245void MCAN1_Handler      ( void );
246void PIOA_Handler       ( void );
247void PIOB_Handler       ( void );
248void PIOC_Handler       ( void );
249void PIOD_Handler       ( void );
250void PIOE_Handler       ( void );
251void PMC_Handler        ( void );
252void PWM0_Handler       ( void );
253void PWM1_Handler       ( void );
254void QSPI_Handler       ( void );
255void RSTC_Handler       ( void );
256void RSWDT_Handler      ( void );
257void RTC_Handler        ( void );
258void RTT_Handler        ( void );
259void SDRAMC_Handler     ( void );
260void SPI0_Handler       ( void );
261void SPI1_Handler       ( void );
262void SSC_Handler        ( void );
263void SUPC_Handler       ( void );
264void TC0_Handler        ( void );
265void TC1_Handler        ( void );
266void TC2_Handler        ( void );
267void TC3_Handler        ( void );
268void TC4_Handler        ( void );
269void TC5_Handler        ( void );
270void TC6_Handler        ( void );
271void TC7_Handler        ( void );
272void TC8_Handler        ( void );
273void TC9_Handler        ( void );
274void TC10_Handler       ( void );
275void TC11_Handler       ( void );
276void TRNG_Handler       ( void );
277void TWIHS0_Handler     ( void );
278void TWIHS1_Handler     ( void );
279void TWIHS2_Handler     ( void );
280void UART0_Handler      ( void );
281void UART1_Handler      ( void );
282void UART2_Handler      ( void );
283void UART3_Handler      ( void );
284void UART4_Handler      ( void );
285void USART0_Handler     ( void );
286void USART1_Handler     ( void );
287void USART2_Handler     ( void );
288void USBHS_Handler      ( void );
289void WDT_Handler        ( void );
290void XDMAC_Handler      ( void );
291
292/**
293 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
294 */
295
296#define __CM7_REV              0x0000 /**< SAME70Q20 core revision number ([15:8] revision number, [7:0] patch number) */
297#define __MPU_PRESENT          1      /**< SAME70Q20 does provide a MPU */
298#define __NVIC_PRIO_BITS       3      /**< SAME70Q20 uses 3 Bits for the Priority Levels */
299#define __FPU_PRESENT          1      /**< SAME70Q20 does provide a FPU                */
300#define __FPU_DP               1      /**< SAME70Q20 Double precision FPU              */
301#define __ICACHE_PRESENT       1      /**< SAME70Q20 does provide an Instruction Cache */
302#define __DCACHE_PRESENT       1      /**< SAME70Q20 does provide a Data Cache         */
303#define __DTCM_PRESENT         1      /**< SAME70Q20 does provide a Data TCM           */
304#define __ITCM_PRESENT         1      /**< SAME70Q20 does provide an Instruction TCM   */
305#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
306
307/*
308 * \brief CMSIS includes
309 */
310
311#include <core_cm7.h>
312#if !defined DONT_USE_CMSIS_INIT
313#include "system_same70.h"
314#endif /* DONT_USE_CMSIS_INIT */
315
316/*@}*/
317
318/* ************************************************************************** */
319/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20 */
320/* ************************************************************************** */
321/** \addtogroup SAME70Q20_api Peripheral Software API */
322/*@{*/
323
324#include "component/component_acc.h"
325#include "component/component_aes.h"
326#include "component/component_afec.h"
327#include "component/component_chipid.h"
328#include "component/component_dacc.h"
329#include "component/component_efc.h"
330#include "component/component_gmac.h"
331#include "component/component_gpbr.h"
332#include "component/component_hsmci.h"
333#include "component/component_icm.h"
334#include "component/component_isi.h"
335#include "component/component_matrix.h"
336#include "component/component_mcan.h"
337#include "component/component_pio.h"
338#include "component/component_pmc.h"
339#include "component/component_pwm.h"
340#include "component/component_qspi.h"
341#include "component/component_rstc.h"
342#include "component/component_rswdt.h"
343#include "component/component_rtc.h"
344#include "component/component_rtt.h"
345#include "component/component_sdramc.h"
346#include "component/component_smc.h"
347#include "component/component_spi.h"
348#include "component/component_ssc.h"
349#include "component/component_supc.h"
350#include "component/component_tc.h"
351#include "component/component_trng.h"
352#include "component/component_twihs.h"
353#include "component/component_uart.h"
354#include "component/component_usart.h"
355#include "component/component_usbhs.h"
356#include "component/component_utmi.h"
357#include "component/component_wdt.h"
358#include "component/component_xdmac.h"
359/*@}*/
360
361#ifndef __rtems__
362/* ************************************************************************** */
363/*   REGISTER ACCESS DEFINITIONS FOR SAME70Q20 */
364/* ************************************************************************** */
365/** \addtogroup SAME70Q20_reg Registers Access Definitions */
366/*@{*/
367
368#include "instance/instance_hsmci.h"
369#include "instance/instance_ssc.h"
370#include "instance/instance_spi0.h"
371#include "instance/instance_tc0.h"
372#include "instance/instance_tc1.h"
373#include "instance/instance_tc2.h"
374#include "instance/instance_twihs0.h"
375#include "instance/instance_twihs1.h"
376#include "instance/instance_pwm0.h"
377#include "instance/instance_usart0.h"
378#include "instance/instance_usart1.h"
379#include "instance/instance_usart2.h"
380#include "instance/instance_mcan0.h"
381#include "instance/instance_mcan1.h"
382#include "instance/instance_usbhs.h"
383#include "instance/instance_afec0.h"
384#include "instance/instance_dacc.h"
385#include "instance/instance_acc.h"
386#include "instance/instance_icm.h"
387#include "instance/instance_isi.h"
388#include "instance/instance_gmac.h"
389#include "instance/instance_tc3.h"
390#include "instance/instance_spi1.h"
391#include "instance/instance_pwm1.h"
392#include "instance/instance_twihs2.h"
393#include "instance/instance_afec1.h"
394#include "instance/instance_aes.h"
395#include "instance/instance_trng.h"
396#include "instance/instance_xdmac.h"
397#include "instance/instance_qspi.h"
398#include "instance/instance_smc.h"
399#include "instance/instance_sdramc.h"
400#include "instance/instance_matrix.h"
401#include "instance/instance_utmi.h"
402#include "instance/instance_pmc.h"
403#include "instance/instance_uart0.h"
404#include "instance/instance_chipid.h"
405#include "instance/instance_uart1.h"
406#include "instance/instance_efc.h"
407#include "instance/instance_pioa.h"
408#include "instance/instance_piob.h"
409#include "instance/instance_pioc.h"
410#include "instance/instance_piod.h"
411#include "instance/instance_pioe.h"
412#include "instance/instance_rstc.h"
413#include "instance/instance_supc.h"
414#include "instance/instance_rtt.h"
415#include "instance/instance_wdt.h"
416#include "instance/instance_rtc.h"
417#include "instance/instance_gpbr.h"
418#include "instance/instance_rswdt.h"
419#include "instance/instance_uart2.h"
420#include "instance/instance_uart3.h"
421#include "instance/instance_uart4.h"
422/*@}*/
423#endif /* __rtems__ */
424
425/* ************************************************************************** */
426/*   PERIPHERAL ID DEFINITIONS FOR SAME70Q20 */
427/* ************************************************************************** */
428/** \addtogroup SAME70Q20_id Peripheral Ids Definitions */
429/*@{*/
430
431#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
432#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
433#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
434#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
435#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
436#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
437#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
438#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
439#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
440#define ID_SMC    ( 9) /**< \brief Static Memory Controller (SMC) */
441#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
442#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
443#define ID_PIOC   (12) /**< \brief Parallel I/O Controller C (PIOC) */
444#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
445#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
446#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
447#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
448#define ID_PIOE   (17) /**< \brief Parallel I/O Controller E (PIOE) */
449#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
450#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
451#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
452#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
453#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
454#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
455#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
456#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
457#define ID_TC3    (26) /**< \brief Timer/Counter 3 (TC3) */
458#define ID_TC4    (27) /**< \brief Timer/Counter 4 (TC4) */
459#define ID_TC5    (28) /**< \brief Timer/Counter 5 (TC5) */
460#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
461#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
462#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
463#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
464#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
465#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
466#define ID_MCAN0  (35) /**< \brief MCAN Controller 0 (MCAN0) */
467#define ID_MCAN1  (37) /**< \brief MCAN Controller 1 (MCAN1) */
468#define ID_GMAC   (39) /**< \brief Ethernet MAC (GMAC) */
469#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
470#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
471#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
472#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
473#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
474#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
475#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
476#define ID_TC6    (47) /**< \brief Timer/Counter 6 (TC6) */
477#define ID_TC7    (48) /**< \brief Timer/Counter 7 (TC7) */
478#define ID_TC8    (49) /**< \brief Timer/Counter 8 (TC8) */
479#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
480#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
481#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
482#define ID_AES    (56) /**< \brief AES (AES) */
483#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
484#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
485#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
486#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
487#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
488#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
489
490#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
491/*@}*/
492
493/* ************************************************************************** */
494/*   BASE ADDRESS DEFINITIONS FOR SAME70Q20 */
495/* ************************************************************************** */
496/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions */
497/*@{*/
498
499#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
500#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
501#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
502#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
503#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
504#define TC1    (0x40010000U) /**< \brief (TC1   ) Base Address */
505#define TC2    (0x40014000U) /**< \brief (TC2   ) Base Address */
506#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
507#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
508#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
509#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
510#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
511#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
512#define MCAN0  (0x40030000U) /**< \brief (MCAN0 ) Base Address */
513#define MCAN1  (0x40034000U) /**< \brief (MCAN1 ) Base Address */
514#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
515#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
516#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
517#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
518#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
519#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
520#define GMAC   (0x40050000U) /**< \brief (GMAC  ) Base Address */
521#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
522#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
523#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
524#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
525#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
526#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
527#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
528#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
529#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
530#define SMC    (0x40080000U) /**< \brief (SMC   ) Base Address */
531#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
532#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
533#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
534#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
535#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
536#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
537#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
538#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
539#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
540#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
541#define PIOC   (0x400E1200U) /**< \brief (PIOC  ) Base Address */
542#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
543#define PIOE   (0x400E1600U) /**< \brief (PIOE  ) Base Address */
544#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
545#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
546#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
547#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
548#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
549#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
550#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
551#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
552#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
553#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
554#else
555#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
556#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
557#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
558#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
559#define TC1    ((Tc     *)0x40010000U) /**< \brief (TC1   ) Base Address */
560#define TC2    ((Tc     *)0x40014000U) /**< \brief (TC2   ) Base Address */
561#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
562#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
563#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
564#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
565#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
566#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
567#define MCAN0  ((Mcan   *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
568#define MCAN1  ((Mcan   *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
569#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
570#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
571#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
572#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
573#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
574#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
575#define GMAC   ((Gmac   *)0x40050000U) /**< \brief (GMAC  ) Base Address */
576#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
577#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
578#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
579#define TWIHS2 ((Twihs  *)0x40060000U) /**< \brief (TWIHS2) Base Address */
580#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
581#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
582#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
583#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
584#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
585#define SMC    ((Smc    *)0x40080000U) /**< \brief (SMC   ) Base Address */
586#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
587#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
588#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
589#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
590#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
591#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
592#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
593#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
594#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
595#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
596#define PIOC   ((Pio    *)0x400E1200U) /**< \brief (PIOC  ) Base Address */
597#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
598#define PIOE   ((Pio    *)0x400E1600U) /**< \brief (PIOE  ) Base Address */
599#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
600#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
601#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
602#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
603#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
604#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
605#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
606#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
607#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
608#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
609#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
610/*@}*/
611
612/* ************************************************************************** */
613/*   PIO DEFINITIONS FOR SAME70Q20 */
614/* ************************************************************************** */
615/** \addtogroup SAME70Q20_pio Peripheral Pio Definitions */
616/*@{*/
617
618#include "pio/pio_same70q20.h"
619/*@}*/
620
621/* ************************************************************************** */
622/*   MEMORY MAPPING DEFINITIONS FOR SAME70Q20 */
623/* ************************************************************************** */
624
625#define IFLASH_SIZE             (0x100000u)
626#define IFLASH_PAGE_SIZE        (512u)
627#define IFLASH_LOCK_REGION_SIZE (8192u)
628#define IFLASH_NB_OF_PAGES      (2048u)
629#define IFLASH_NB_OF_LOCK_BITS  (64u)
630#define IRAM_SIZE               (0x60000u)
631
632#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
633#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
634#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
635#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
636#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
637#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
638#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
639#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
640#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
641#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
642#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
643#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
644
645/* ************************************************************************** */
646/*   MISCELLANEOUS DEFINITIONS FOR SAME70Q20 */
647/* ************************************************************************** */
648
649#define CHIP_JTAGID (0x05B3D03FUL)
650#define CHIP_CIDR   (0xA1020C00UL)
651#define CHIP_EXID   (0x00000002UL)
652
653/* ************************************************************************** */
654/*   ELECTRICAL DEFINITIONS FOR SAME70Q20 */
655/* ************************************************************************** */
656
657/* %ATMEL_ELECTRICAL% */
658
659/* Device characteristics */
660#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
661#define CHIP_FREQ_SLCK_RC               (32000UL)
662#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
663#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
664#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
665#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
666#define CHIP_FREQ_CPU_MAX               (120000000UL)
667#define CHIP_FREQ_XTAL_32K              (32768UL)
668#define CHIP_FREQ_XTAL_12M              (12000000UL)
669
670/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
671#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
672#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
673#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
674#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
675#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
676#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
677
678#ifdef __cplusplus
679}
680#endif
681
682/*@}*/
683
684#endif /* _SAME70Q20_ */
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