source: rtems/bsps/arm/atsam/include/libchip/include/same70/same70j20.h @ 2afb22b

5
Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.
  • Property mode set to 100644
File size: 31.1 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAME70J20_
31#define _SAME70J20_
32
33/** \addtogroup SAME70J20_definitions SAME70J20 definitions
34  This file defines all structures and symbols for SAME70J20:
35    - registers and bitfields
36    - peripheral base address
37    - peripheral ID
38    - PIO definitions
39*/
40/*@{*/
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/*   CMSIS DEFINITIONS FOR SAME70J20 */
52/* ************************************************************************** */
53/** \addtogroup SAME70J20_cmsis CMSIS Definitions */
54/*@{*/
55
56/**< Interrupt Number Definition */
57typedef enum IRQn
58{
59/******  Cortex-M7 Processor Exceptions Numbers ******************************/
60  NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
61  HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
62  MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
63  BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
64  UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
65  SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
66  DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
67  PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
68  SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
69/******  SAME70J20 specific Interrupt Numbers *********************************/
70
71  SUPC_IRQn            =  0, /**<  0 SAME70J20 Supply Controller (SUPC) */
72  RSTC_IRQn            =  1, /**<  1 SAME70J20 Reset Controller (RSTC) */
73  RTC_IRQn             =  2, /**<  2 SAME70J20 Real Time Clock (RTC) */
74  RTT_IRQn             =  3, /**<  3 SAME70J20 Real Time Timer (RTT) */
75  WDT_IRQn             =  4, /**<  4 SAME70J20 Watchdog Timer (WDT) */
76  PMC_IRQn             =  5, /**<  5 SAME70J20 Power Management Controller (PMC) */
77  EFC_IRQn             =  6, /**<  6 SAME70J20 Enhanced Embedded Flash Controller (EFC) */
78  UART0_IRQn           =  7, /**<  7 SAME70J20 UART 0 (UART0) */
79  UART1_IRQn           =  8, /**<  8 SAME70J20 UART 1 (UART1) */
80  PIOA_IRQn            = 10, /**< 10 SAME70J20 Parallel I/O Controller A (PIOA) */
81  PIOB_IRQn            = 11, /**< 11 SAME70J20 Parallel I/O Controller B (PIOB) */
82  USART0_IRQn          = 13, /**< 13 SAME70J20 USART 0 (USART0) */
83  USART1_IRQn          = 14, /**< 14 SAME70J20 USART 1 (USART1) */
84  USART2_IRQn          = 15, /**< 15 SAME70J20 USART 2 (USART2) */
85  PIOD_IRQn            = 16, /**< 16 SAME70J20 Parallel I/O Controller D (PIOD) */
86  HSMCI_IRQn           = 18, /**< 18 SAME70J20 Multimedia Card Interface (HSMCI) */
87  TWIHS0_IRQn          = 19, /**< 19 SAME70J20 Two Wire Interface 0 HS (TWIHS0) */
88  TWIHS1_IRQn          = 20, /**< 20 SAME70J20 Two Wire Interface 1 HS (TWIHS1) */
89  SPI0_IRQn            = 21, /**< 21 SAME70J20 Serial Peripheral Interface 0 (SPI0) */
90  SSC_IRQn             = 22, /**< 22 SAME70J20 Synchronous Serial Controller (SSC) */
91  TC0_IRQn             = 23, /**< 23 SAME70J20 Timer/Counter 0 (TC0) */
92  TC1_IRQn             = 24, /**< 24 SAME70J20 Timer/Counter 1 (TC1) */
93  TC2_IRQn             = 25, /**< 25 SAME70J20 Timer/Counter 2 (TC2) */
94  AFEC0_IRQn           = 29, /**< 29 SAME70J20 Analog Front End 0 (AFEC0) */
95  DACC_IRQn            = 30, /**< 30 SAME70J19 Digital To Analog Converter (DACC) */
96  PWM0_IRQn            = 31, /**< 31 SAME70J20 Pulse Width Modulation 0 (PWM0) */
97  ICM_IRQn             = 32, /**< 32 SAME70J20 Integrity Check Monitor (ICM) */
98  ACC_IRQn             = 33, /**< 33 SAME70J20 Analog Comparator (ACC) */
99  USBHS_IRQn           = 34, /**< 34 SAME70J20 USB Host / Device Controller (USBHS) */
100  MCAN0_IRQn           = 35, /**< 35 SAME70J20 MCAN Controller 0 (MCAN0) */
101  MCAN1_IRQn           = 37, /**< 37 SAME70J20 MCAN Controller 1 (MCAN1) */
102  GMAC_IRQn            = 39, /**< 39 SAME70J20 Ethernet MAC (GMAC) */
103  AFEC1_IRQn           = 40, /**< 40 SAME70J20 Analog Front End 1 (AFEC1) */
104  SPI1_IRQn            = 42, /**< 42 SAME70J20 Serial Peripheral Interface 1 (SPI1) */
105  QSPI_IRQn            = 43, /**< 43 SAME70J20 Quad I/O Serial Peripheral Interface (QSPI) */
106  UART2_IRQn           = 44, /**< 44 SAME70J20 UART 2 (UART2) */
107  UART3_IRQn           = 45, /**< 45 SAME70J20 UART 3 (UART3) */
108  UART4_IRQn           = 46, /**< 46 SAME70J20 UART 4 (UART4) */
109  TC9_IRQn             = 50, /**< 50 SAME70J20 Timer/Counter 9 (TC9) */
110  TC10_IRQn            = 51, /**< 51 SAME70J20 Timer/Counter 10 (TC10) */
111  TC11_IRQn            = 52, /**< 52 SAME70J20 Timer/Counter 11 (TC11) */
112  AES_IRQn             = 56, /**< 56 SAME70J20 AES (AES) */
113  TRNG_IRQn            = 57, /**< 57 SAME70J20 True Random Generator (TRNG) */
114  XDMAC_IRQn           = 58, /**< 58 SAME70J20 DMA (XDMAC) */
115  ISI_IRQn             = 59, /**< 59 SAME70J20 Camera Interface (ISI) */
116  PWM1_IRQn            = 60, /**< 60 SAME70J20 Pulse Width Modulation 1 (PWM1) */
117  RSWDT_IRQn           = 63, /**< 63 SAME70J20 Reinforced Secure Watchdog Timer (RSWDT) */
118
119  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
120} IRQn_Type;
121
122typedef struct _DeviceVectors
123{
124  /* Stack pointer */
125  void* pvStack;
126
127  /* Cortex-M handlers */
128  void* pfnReset_Handler;
129  void* pfnNMI_Handler;
130  void* pfnHardFault_Handler;
131  void* pfnMemManage_Handler;
132  void* pfnBusFault_Handler;
133  void* pfnUsageFault_Handler;
134  void* pfnReserved1_Handler;
135  void* pfnReserved2_Handler;
136  void* pfnReserved3_Handler;
137  void* pfnReserved4_Handler;
138  void* pfnSVC_Handler;
139  void* pfnDebugMon_Handler;
140  void* pfnReserved5_Handler;
141  void* pfnPendSV_Handler;
142  void* pfnSysTick_Handler;
143
144  /* Peripheral handlers */
145  void* pfnSUPC_Handler;   /*  0 Supply Controller */
146  void* pfnRSTC_Handler;   /*  1 Reset Controller */
147  void* pfnRTC_Handler;    /*  2 Real Time Clock */
148  void* pfnRTT_Handler;    /*  3 Real Time Timer */
149  void* pfnWDT_Handler;    /*  4 Watchdog Timer */
150  void* pfnPMC_Handler;    /*  5 Power Management Controller */
151  void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
152  void* pfnUART0_Handler;  /*  7 UART 0 */
153  void* pfnUART1_Handler;  /*  8 UART 1 */
154  void* pvReserved9;
155  void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
156  void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
157  void* pvReserved12;
158  void* pfnUSART0_Handler; /* 13 USART 0 */
159  void* pfnUSART1_Handler; /* 14 USART 1 */
160  void* pfnUSART2_Handler; /* 15 USART 2 */
161  void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
162  void* pvReserved17;
163  void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
164  void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
165  void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
166  void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
167  void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
168  void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
169  void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
170  void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
171  void* pvReserved26;
172  void* pvReserved27;
173  void* pvReserved28;
174  void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
175  void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
176  void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
177  void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
178  void* pfnACC_Handler;    /* 33 Analog Comparator */
179  void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
180  void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
181  void* pvReserved36;
182  void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
183  void* pvReserved38;
184  void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
185  void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
186  void* pvReserved41;
187  void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
188  void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
189  void* pfnUART2_Handler;  /* 44 UART 2 */
190  void* pfnUART3_Handler;  /* 45 UART 3 */
191  void* pfnUART4_Handler;  /* 46 UART 4 */
192  void* pvReserved47;
193  void* pvReserved48;
194  void* pvReserved49;
195  void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
196  void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
197  void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
198  void* pvReserved53;
199  void* pvReserved54;
200  void* pvReserved55;
201  void* pfnAES_Handler;    /* 56 AES */
202  void* pfnTRNG_Handler;   /* 57 True Random Generator */
203  void* pfnXDMAC_Handler;  /* 58 DMA */
204  void* pfnISI_Handler;    /* 59 Camera Interface */
205  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
206  void* pvReserved61;
207  void* pvReserved62;
208  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
209} DeviceVectors;
210
211/* Cortex-M7 core handlers */
212void Reset_Handler      ( void );
213void NMI_Handler        ( void );
214void HardFault_Handler  ( void );
215void MemManage_Handler  ( void );
216void BusFault_Handler   ( void );
217void UsageFault_Handler ( void );
218void SVC_Handler        ( void );
219void DebugMon_Handler   ( void );
220void PendSV_Handler     ( void );
221void SysTick_Handler    ( void );
222
223/* Peripherals handlers */
224void ACC_Handler        ( void );
225void AES_Handler        ( void );
226void AFEC0_Handler      ( void );
227void AFEC1_Handler      ( void );
228void DACC_Handler       ( void );
229void EFC_Handler        ( void );
230void GMAC_Handler       ( void );
231void HSMCI_Handler      ( void );
232void ICM_Handler        ( void );
233void ISI_Handler        ( void );
234void MCAN0_Handler      ( void );
235void MCAN1_Handler      ( void );
236void PIOA_Handler       ( void );
237void PIOB_Handler       ( void );
238void PIOD_Handler       ( void );
239void PMC_Handler        ( void );
240void PWM0_Handler       ( void );
241void PWM1_Handler       ( void );
242void QSPI_Handler       ( void );
243void RSTC_Handler       ( void );
244void RSWDT_Handler      ( void );
245void RTC_Handler        ( void );
246void RTT_Handler        ( void );
247void SPI0_Handler       ( void );
248void SPI1_Handler       ( void );
249void SSC_Handler        ( void );
250void SUPC_Handler       ( void );
251void TC0_Handler        ( void );
252void TC1_Handler        ( void );
253void TC2_Handler        ( void );
254void TC9_Handler        ( void );
255void TC10_Handler       ( void );
256void TC11_Handler       ( void );
257void TRNG_Handler       ( void );
258void TWIHS0_Handler     ( void );
259void TWIHS1_Handler     ( void );
260void UART0_Handler      ( void );
261void UART1_Handler      ( void );
262void UART2_Handler      ( void );
263void UART3_Handler      ( void );
264void UART4_Handler      ( void );
265void USART0_Handler     ( void );
266void USART1_Handler     ( void );
267void USART2_Handler     ( void );
268void USBHS_Handler      ( void );
269void WDT_Handler        ( void );
270void XDMAC_Handler      ( void );
271
272/**
273 * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
274 */
275
276#define __CM7_REV              0x0000 /**< SAME70J20 core revision number ([15:8] revision number, [7:0] patch number) */
277#define __MPU_PRESENT          1      /**< SAME70J20 does provide a MPU */
278#define __NVIC_PRIO_BITS       3      /**< SAME70J20 uses 3 Bits for the Priority Levels */
279#define __FPU_PRESENT          1      /**< SAME70J20 does provide a FPU                */
280#define __FPU_DP               1      /**< SAME70J20 Double precision FPU              */
281#define __ICACHE_PRESENT       1      /**< SAME70J20 does provide an Instruction Cache */
282#define __DCACHE_PRESENT       1      /**< SAME70J20 does provide a Data Cache         */
283#define __DTCM_PRESENT         1      /**< SAME70J20 does provide a Data TCM           */
284#define __ITCM_PRESENT         1      /**< SAME70J20 does provide an Instruction TCM   */
285#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
286
287/*
288 * \brief CMSIS includes
289 */
290
291#include <core_cm7.h>
292#if !defined DONT_USE_CMSIS_INIT
293#include "system_same70.h"
294#endif /* DONT_USE_CMSIS_INIT */
295
296/*@}*/
297
298/* ************************************************************************** */
299/**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20 */
300/* ************************************************************************** */
301/** \addtogroup SAME70J20_api Peripheral Software API */
302/*@{*/
303
304#include "component/component_acc.h"
305#include "component/component_aes.h"
306#include "component/component_afec.h"
307#include "component/component_chipid.h"
308#include "component/component_dacc.h"
309#include "component/component_efc.h"
310#include "component/component_gmac.h"
311#include "component/component_gpbr.h"
312#include "component/component_hsmci.h"
313#include "component/component_icm.h"
314#include "component/component_isi.h"
315#include "component/component_matrix.h"
316#include "component/component_mcan.h"
317#include "component/component_pio.h"
318#include "component/component_pmc.h"
319#include "component/component_pwm.h"
320#include "component/component_qspi.h"
321#include "component/component_rstc.h"
322#include "component/component_rswdt.h"
323#include "component/component_rtc.h"
324#include "component/component_rtt.h"
325#include "component/component_spi.h"
326#include "component/component_ssc.h"
327#include "component/component_supc.h"
328#include "component/component_tc.h"
329#include "component/component_trng.h"
330#include "component/component_twihs.h"
331#include "component/component_uart.h"
332#include "component/component_usart.h"
333#include "component/component_usbhs.h"
334#include "component/component_utmi.h"
335#include "component/component_wdt.h"
336#include "component/component_xdmac.h"
337/*@}*/
338
339#ifndef __rtems__
340/* ************************************************************************** */
341/*   REGISTER ACCESS DEFINITIONS FOR SAME70J20 */
342/* ************************************************************************** */
343/** \addtogroup SAME70J20_reg Registers Access Definitions */
344/*@{*/
345
346#include "instance/instance_hsmci.h"
347#include "instance/instance_ssc.h"
348#include "instance/instance_spi0.h"
349#include "instance/instance_tc0.h"
350#include "instance/instance_twihs0.h"
351#include "instance/instance_twihs1.h"
352#include "instance/instance_pwm0.h"
353#include "instance/instance_usart0.h"
354#include "instance/instance_usart1.h"
355#include "instance/instance_usart2.h"
356#include "instance/instance_mcan0.h"
357#include "instance/instance_mcan1.h"
358#include "instance/instance_usbhs.h"
359#include "instance/instance_afec0.h"
360#include "instance/instance_dacc.h"
361#include "instance/instance_acc.h"
362#include "instance/instance_icm.h"
363#include "instance/instance_isi.h"
364#include "instance/instance_gmac.h"
365#include "instance/instance_tc3.h"
366#include "instance/instance_spi1.h"
367#include "instance/instance_pwm1.h"
368#include "instance/instance_afec1.h"
369#include "instance/instance_aes.h"
370#include "instance/instance_trng.h"
371#include "instance/instance_xdmac.h"
372#include "instance/instance_qspi.h"
373#include "instance/instance_matrix.h"
374#include "instance/instance_utmi.h"
375#include "instance/instance_pmc.h"
376#include "instance/instance_uart0.h"
377#include "instance/instance_chipid.h"
378#include "instance/instance_uart1.h"
379#include "instance/instance_efc.h"
380#include "instance/instance_pioa.h"
381#include "instance/instance_piob.h"
382#include "instance/instance_piod.h"
383#include "instance/instance_rstc.h"
384#include "instance/instance_supc.h"
385#include "instance/instance_rtt.h"
386#include "instance/instance_wdt.h"
387#include "instance/instance_rtc.h"
388#include "instance/instance_gpbr.h"
389#include "instance/instance_rswdt.h"
390#include "instance/instance_uart2.h"
391#include "instance/instance_uart3.h"
392#include "instance/instance_uart4.h"
393/*@}*/
394#endif /* __rtems__ */
395
396/* ************************************************************************** */
397/*   PERIPHERAL ID DEFINITIONS FOR SAME70J20 */
398/* ************************************************************************** */
399/** \addtogroup SAME70J20_id Peripheral Ids Definitions */
400/*@{*/
401
402#define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
403#define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
404#define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
405#define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
406#define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
407#define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
408#define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
409#define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
410#define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
411#define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
412#define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
413#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
414#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
415#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
416#define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
417#define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
418#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
419#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
420#define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
421#define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
422#define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
423#define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
424#define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
425#define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
426#define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
427#define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
428#define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
429#define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
430#define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
431#define ID_MCAN0  (35) /**< \brief MCAN Controller 0 (MCAN0) */
432#define ID_MCAN1  (37) /**< \brief MCAN Controller 1 (MCAN1) */
433#define ID_GMAC   (39) /**< \brief Ethernet MAC (GMAC) */
434#define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
435#define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
436#define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
437#define ID_UART2  (44) /**< \brief UART 2 (UART2) */
438#define ID_UART3  (45) /**< \brief UART 3 (UART3) */
439#define ID_UART4  (46) /**< \brief UART 4 (UART4) */
440#define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
441#define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
442#define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
443#define ID_AES    (56) /**< \brief AES (AES) */
444#define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
445#define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
446#define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
447#define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
448#define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
449
450#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
451/*@}*/
452
453/* ************************************************************************** */
454/*   BASE ADDRESS DEFINITIONS FOR SAME70J20 */
455/* ************************************************************************** */
456/** \addtogroup SAME70J20_base Peripheral Base Address Definitions */
457/*@{*/
458
459#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
460#define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
461#define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
462#define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
463#define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
464#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
465#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
466#define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
467#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
468#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
469#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
470#define MCAN0  (0x40030000U) /**< \brief (MCAN0 ) Base Address */
471#define MCAN1  (0x40034000U) /**< \brief (MCAN1 ) Base Address */
472#define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
473#define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
474#define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
475#define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
476#define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
477#define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
478#define GMAC   (0x40050000U) /**< \brief (GMAC  ) Base Address */
479#define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
480#define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
481#define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
482#define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
483#define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
484#define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
485#define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
486#define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
487#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
488#define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
489#define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
490#define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
491#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
492#define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
493#define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
494#define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
495#define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
496#define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
497#define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
498#define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
499#define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
500#define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
501#define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
502#define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
503#define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
504#define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
505#define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
506#define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
507#else
508#define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
509#define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
510#define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
511#define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
512#define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
513#define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
514#define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
515#define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
516#define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
517#define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
518#define MCAN0  ((Mcan   *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
519#define MCAN1  ((Mcan   *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
520#define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
521#define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
522#define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
523#define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
524#define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
525#define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
526#define GMAC   ((Gmac   *)0x40050000U) /**< \brief (GMAC  ) Base Address */
527#define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
528#define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
529#define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
530#define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
531#define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
532#define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
533#define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
534#define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
535#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
536#define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
537#define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
538#define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
539#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
540#define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
541#define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
542#define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
543#define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
544#define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
545#define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
546#define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
547#define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
548#define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
549#define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
550#define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
551#define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
552#define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
553#define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
554#define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
555#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
556/*@}*/
557
558/* ************************************************************************** */
559/*   PIO DEFINITIONS FOR SAME70J20 */
560/* ************************************************************************** */
561/** \addtogroup SAME70J20_pio Peripheral Pio Definitions */
562/*@{*/
563
564#include "pio/pio_same70j20.h"
565/*@}*/
566
567/* ************************************************************************** */
568/*   MEMORY MAPPING DEFINITIONS FOR SAME70J20 */
569/* ************************************************************************** */
570
571#define IFLASH_SIZE             (0x100000u)
572#define IFLASH_PAGE_SIZE        (512u)
573#define IFLASH_LOCK_REGION_SIZE (8192u)
574#define IFLASH_NB_OF_PAGES      (2048u)
575#define IFLASH_NB_OF_LOCK_BITS  (64u)
576#define IRAM_SIZE               (0x60000u)
577
578#define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
579#define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
580#define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
581#define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
582#define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
583#define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
584#define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
585#define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
586#define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
587#define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
588#define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
589#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
590
591/* ************************************************************************** */
592/*   MISCELLANEOUS DEFINITIONS FOR SAME70J20 */
593/* ************************************************************************** */
594
595#define CHIP_JTAGID (0x05B3D03FUL)
596#define CHIP_CIDR   (0xA1020C00UL)
597#define CHIP_EXID   (0x00000000UL)
598
599/* ************************************************************************** */
600/*   ELECTRICAL DEFINITIONS FOR SAME70J20 */
601/* ************************************************************************** */
602
603/* %ATMEL_ELECTRICAL% */
604
605/* Device characteristics */
606#define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
607#define CHIP_FREQ_SLCK_RC               (32000UL)
608#define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
609#define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
610#define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
611#define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
612#define CHIP_FREQ_CPU_MAX               (120000000UL)
613#define CHIP_FREQ_XTAL_32K              (32768UL)
614#define CHIP_FREQ_XTAL_12M              (12000000UL)
615
616/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
617#define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
618#define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
619#define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
620#define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
621#define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
622#define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
623
624#ifdef __cplusplus
625}
626#endif
627
628/*@}*/
629
630#endif /* _SAME70J20_ */
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