1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | #ifndef _SAME70_QSPI_COMPONENT_ |
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31 | #define _SAME70_QSPI_COMPONENT_ |
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32 | |
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33 | /* ============================================================================= */ |
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34 | /** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ |
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35 | /* ============================================================================= */ |
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36 | /** \addtogroup SAME70_QSPI Quad Serial Peripheral Interface */ |
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37 | /*@{*/ |
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38 | |
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39 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
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40 | /** \brief Qspi hardware registers */ |
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41 | typedef struct { |
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42 | __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ |
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43 | __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ |
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44 | __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ |
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45 | __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ |
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46 | __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ |
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47 | __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ |
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48 | __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ |
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49 | __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ |
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50 | __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ |
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51 | __I uint32_t Reserved1[3]; |
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52 | __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ |
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53 | __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ |
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54 | __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ |
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55 | __I uint32_t Reserved2[1]; |
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56 | __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ |
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57 | __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ |
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58 | __I uint32_t Reserved3[39]; |
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59 | __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ |
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60 | __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ |
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61 | } Qspi; |
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62 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
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63 | /* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ |
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64 | #define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ |
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65 | #define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ |
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66 | #define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ |
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67 | #define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ |
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68 | /* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ |
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69 | #define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ |
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70 | #define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ |
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71 | #define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ |
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72 | #define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ |
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73 | #define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ |
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74 | #define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ |
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75 | #define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ |
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76 | #define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ |
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77 | #define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ |
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78 | #define QSPI_MR_CSMODE_Pos 4 |
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79 | #define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ |
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80 | #define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) |
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81 | #define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ |
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82 | #define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ |
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83 | #define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ |
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84 | #define QSPI_MR_NBBITS_Pos 8 |
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85 | #define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ |
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86 | #define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) |
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87 | #define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ |
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88 | #define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ |
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89 | #define QSPI_MR_DLYBCT_Pos 16 |
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90 | #define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ |
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91 | #define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) |
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92 | #define QSPI_MR_DLYCS_Pos 24 |
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93 | #define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ |
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94 | #define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) |
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95 | /* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ |
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96 | #define QSPI_RDR_RD_Pos 0 |
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97 | #define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ |
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98 | /* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ |
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99 | #define QSPI_TDR_TD_Pos 0 |
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100 | #define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ |
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101 | #define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) |
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102 | /* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ |
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103 | #define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ |
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104 | #define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ |
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105 | #define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ |
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106 | #define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ |
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107 | #define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ |
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108 | #define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ |
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109 | #define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ |
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110 | #define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ |
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111 | /* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ |
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112 | #define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ |
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113 | #define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ |
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114 | #define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ |
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115 | #define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ |
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116 | #define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ |
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117 | #define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ |
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118 | #define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ |
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119 | /* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ |
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120 | #define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ |
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121 | #define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ |
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122 | #define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ |
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123 | #define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ |
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124 | #define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ |
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125 | #define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ |
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126 | #define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ |
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127 | /* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ |
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128 | #define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ |
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129 | #define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ |
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130 | #define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ |
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131 | #define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ |
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132 | #define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ |
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133 | #define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ |
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134 | #define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ |
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135 | /* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ |
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136 | #define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ |
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137 | #define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ |
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138 | #define QSPI_SCR_SCBR_Pos 8 |
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139 | #define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ |
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140 | #define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) |
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141 | #define QSPI_SCR_DLYBS_Pos 16 |
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142 | #define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ |
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143 | #define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) |
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144 | /* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ |
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145 | #define QSPI_IAR_ADDR_Pos 0 |
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146 | #define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ |
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147 | #define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) |
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148 | /* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ |
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149 | #define QSPI_ICR_INST_Pos 0 |
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150 | #define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ |
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151 | #define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) |
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152 | #define QSPI_ICR_OPT_Pos 16 |
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153 | #define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ |
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154 | #define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) |
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155 | /* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ |
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156 | #define QSPI_IFR_WIDTH_Pos 0 |
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157 | #define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ |
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158 | #define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) |
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159 | #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ |
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160 | #define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ |
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161 | #define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ |
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162 | #define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ |
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163 | #define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ |
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164 | #define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ |
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165 | #define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ |
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166 | #define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ |
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167 | #define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ |
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168 | #define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ |
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169 | #define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ |
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170 | #define QSPI_IFR_OPTL_Pos 8 |
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171 | #define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ |
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172 | #define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) |
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173 | #define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ |
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174 | #define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ |
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175 | #define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ |
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176 | #define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ |
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177 | #define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ |
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178 | #define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ |
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179 | #define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ |
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180 | #define QSPI_IFR_TFRTYP_Pos 12 |
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181 | #define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ |
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182 | #define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) |
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183 | #define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ |
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184 | #define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ |
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185 | #define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ |
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186 | #define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ |
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187 | #define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ |
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188 | #define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ |
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189 | #define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ |
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190 | #define QSPI_IFR_NBDUM_Pos 16 |
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191 | #define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ |
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192 | #define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) |
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193 | /* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ |
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194 | #define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ |
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195 | #define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ |
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196 | #define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ |
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197 | #define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ |
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198 | /* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ |
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199 | #define QSPI_SKR_USRK_Pos 0 |
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200 | #define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ |
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201 | #define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) |
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202 | /* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ |
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203 | #define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ |
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204 | #define QSPI_WPMR_WPKEY_Pos 8 |
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205 | #define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ |
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206 | #define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) |
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207 | #define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ |
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208 | /* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ |
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209 | #define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ |
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210 | #define QSPI_WPSR_WPVSRC_Pos 8 |
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211 | #define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ |
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212 | |
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213 | /*@}*/ |
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214 | |
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215 | |
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216 | #endif /* _SAME70_QSPI_COMPONENT_ */ |
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