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component_pmc.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on 12/23/17 at 07:18:56

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

The make preinstall step itself needs time and disk space.

Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.

There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.

The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.

An introduction of a new build system is difficult.

Include paths specified by the -B option are system headers. This may suppress warnings.

The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

cpukit/include

cpukit/score/cpu/@RTEMS_CPU@/include

cpukit/libnetworking

The new BSP include directories are:

bsps/include

bsps/@RTEMS_CPU@/include

bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

Property mode set to 100644

File size: 65.6 KB

Line
1	/* ---------------------------------------------------------------------------- */
2	/* Atmel Microcontroller Software Support */
3	/* SAM Software Package License */
4	/* ---------------------------------------------------------------------------- */
5	/* Copyright (c) 2015, Atmel Corporation */
6	/* */
7	/* All rights reserved. */
8	/* */
9	/* Redistribution and use in source and binary forms, with or without */
10	/* modification, are permitted provided that the following condition is met: */
11	/* */
12	/* - Redistributions of source code must retain the above copyright notice, */
13	/* this list of conditions and the disclaimer below. */
14	/* */
15	/* Atmel's name may not be used to endorse or promote products derived from */
16	/* this software without specific prior written permission. */
17	/* */
18	/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19	/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20	/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21	/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22	/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23	/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24	/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25	/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26	/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27	/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28	/* ---------------------------------------------------------------------------- */
29
30	#ifndef _SAME70_PMC_COMPONENT_
31	#define _SAME70_PMC_COMPONENT_
32
33	/* ============================================================================= */
34	/** SOFTWARE API DEFINITION FOR Power Management Controller */
35	/* ============================================================================= */
36	/** \addtogroup SAME70_PMC Power Management Controller */
37	/@{/
38
39	#if !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__))
40	/** \brief Pmc hardware registers */
41	typedef struct {
42	__O uint32_t PMC_SCER; /*< \brief (Pmc Offset: 0x0000) System Clock Enable Register /
43	__O uint32_t PMC_SCDR; /*< \brief (Pmc Offset: 0x0004) System Clock Disable Register /
44	__I uint32_t PMC_SCSR; /*< \brief (Pmc Offset: 0x0008) System Clock Status Register /
45	__I uint32_t Reserved1[1];
46	__O uint32_t PMC_PCER0; /*< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 /
47	__O uint32_t PMC_PCDR0; /*< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 /
48	__I uint32_t PMC_PCSR0; /*< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 /
49	__IO uint32_t CKGR_UCKR; /*< \brief (Pmc Offset: 0x001C) UTMI Clock Register /
50	__IO uint32_t CKGR_MOR; /*< \brief (Pmc Offset: 0x0020) Main Oscillator Register /
51	__IO uint32_t CKGR_MCFR; /*< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register /
52	__IO uint32_t CKGR_PLLAR; /*< \brief (Pmc Offset: 0x0028) PLLA Register /
53	__I uint32_t Reserved2[1];
54	__IO uint32_t PMC_MCKR; /*< \brief (Pmc Offset: 0x0030) Master Clock Register /
55	__I uint32_t Reserved3[1];
56	__IO uint32_t PMC_USB; /*< \brief (Pmc Offset: 0x0038) USB Clock Register /
57	__I uint32_t Reserved4[1];
58	__IO uint32_t PMC_PCK[7]; /*< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register /
59	__I uint32_t Reserved5[1];
60	__O uint32_t PMC_IER; /*< \brief (Pmc Offset: 0x0060) Interrupt Enable Register /
61	__O uint32_t PMC_IDR; /*< \brief (Pmc Offset: 0x0064) Interrupt Disable Register /
62	__I uint32_t PMC_SR; /*< \brief (Pmc Offset: 0x0068) Status Register /
63	__I uint32_t PMC_IMR; /*< \brief (Pmc Offset: 0x006C) Interrupt Mask Register /
64	__IO uint32_t PMC_FSMR; /*< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register /
65	__IO uint32_t PMC_FSPR; /*< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register /
66	__O uint32_t PMC_FOCR; /*< \brief (Pmc Offset: 0x0078) Fault Output Clear Register /
67	__I uint32_t Reserved6[26];
68	__IO uint32_t PMC_WPMR; /*< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register /
69	__I uint32_t PMC_WPSR; /*< \brief (Pmc Offset: 0x00E8) Write Protection Status Register /
70	__I uint32_t Reserved7[5];
71	__O uint32_t PMC_PCER1; /*< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 /
72	__O uint32_t PMC_PCDR1; /*< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 /
73	__I uint32_t PMC_PCSR1; /*< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 /
74	__IO uint32_t PMC_PCR; /*< \brief (Pmc Offset: 0x010C) Peripheral Control Register /
75	__IO uint32_t PMC_OCR; /*< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register /
76	__O uint32_t PMC_SLPWK_ER0; /*< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 /
77	__O uint32_t PMC_SLPWK_DR0; /*< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 /
78	__I uint32_t PMC_SLPWK_SR0; /*< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 /
79	__I uint32_t PMC_SLPWK_ASR0; /*< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 /
80	__I uint32_t Reserved8[3];
81	__IO uint32_t PMC_PMMR; /*< \brief (Pmc Offset: 0x0130) PLL Maximum Multiplier Value Register /
82	__O uint32_t PMC_SLPWK_ER1; /*< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 /
83	__O uint32_t PMC_SLPWK_DR1; /*< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 /
84	__I uint32_t PMC_SLPWK_SR1; /*< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 /
85	__I uint32_t PMC_SLPWK_ASR1; /*< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 /
86	__I uint32_t PMC_SLPWK_AIPR; /*< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register /
87	} Pmc;
88	#endif /* !(defined(__ASSEMBLY__) \|\| defined(__IAR_SYSTEMS_ASM__)) */
89	/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
90	#define PMC_SCER_USBCLK (0x1u << 5) /*< \brief (PMC_SCER) Enable USB FS Clock /
91	#define PMC_SCER_PCK0 (0x1u << 8) /*< \brief (PMC_SCER) Programmable Clock 0 Output Enable /
92	#define PMC_SCER_PCK1 (0x1u << 9) /*< \brief (PMC_SCER) Programmable Clock 1 Output Enable /
93	#define PMC_SCER_PCK2 (0x1u << 10) /*< \brief (PMC_SCER) Programmable Clock 2 Output Enable /
94	#define PMC_SCER_PCK3 (0x1u << 11) /*< \brief (PMC_SCER) Programmable Clock 3 Output Enable /
95	#define PMC_SCER_PCK4 (0x1u << 12) /*< \brief (PMC_SCER) Programmable Clock 4 Output Enable /
96	#define PMC_SCER_PCK5 (0x1u << 13) /*< \brief (PMC_SCER) Programmable Clock 5 Output Enable /
97	#define PMC_SCER_PCK6 (0x1u << 14) /*< \brief (PMC_SCER) Programmable Clock 6 Output Enable /
98	/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
99	#define PMC_SCDR_USBCLK (0x1u << 5) /*< \brief (PMC_SCDR) Disable USB FS Clock /
100	#define PMC_SCDR_PCK0 (0x1u << 8) /*< \brief (PMC_SCDR) Programmable Clock 0 Output Disable /
101	#define PMC_SCDR_PCK1 (0x1u << 9) /*< \brief (PMC_SCDR) Programmable Clock 1 Output Disable /
102	#define PMC_SCDR_PCK2 (0x1u << 10) /*< \brief (PMC_SCDR) Programmable Clock 2 Output Disable /
103	#define PMC_SCDR_PCK3 (0x1u << 11) /*< \brief (PMC_SCDR) Programmable Clock 3 Output Disable /
104	#define PMC_SCDR_PCK4 (0x1u << 12) /*< \brief (PMC_SCDR) Programmable Clock 4 Output Disable /
105	#define PMC_SCDR_PCK5 (0x1u << 13) /*< \brief (PMC_SCDR) Programmable Clock 5 Output Disable /
106	#define PMC_SCDR_PCK6 (0x1u << 14) /*< \brief (PMC_SCDR) Programmable Clock 6 Output Disable /
107	/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
108	#define PMC_SCSR_USBCLK (0x1u << 5) /*< \brief (PMC_SCSR) USB FS Clock Status /
109	#define PMC_SCSR_PCK0 (0x1u << 8) /*< \brief (PMC_SCSR) Programmable Clock 0 Output Status /
110	#define PMC_SCSR_PCK1 (0x1u << 9) /*< \brief (PMC_SCSR) Programmable Clock 1 Output Status /
111	#define PMC_SCSR_PCK2 (0x1u << 10) /*< \brief (PMC_SCSR) Programmable Clock 2 Output Status /
112	#define PMC_SCSR_PCK3 (0x1u << 11) /*< \brief (PMC_SCSR) Programmable Clock 3 Output Status /
113	#define PMC_SCSR_PCK4 (0x1u << 12) /*< \brief (PMC_SCSR) Programmable Clock 4 Output Status /
114	#define PMC_SCSR_PCK5 (0x1u << 13) /*< \brief (PMC_SCSR) Programmable Clock 5 Output Status /
115	#define PMC_SCSR_PCK6 (0x1u << 14) /*< \brief (PMC_SCSR) Programmable Clock 6 Output Status /
116	/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
117	#define PMC_PCER0_PID7 (0x1u << 7) /*< \brief (PMC_PCER0) Peripheral Clock 7 Enable /
118	#define PMC_PCER0_PID8 (0x1u << 8) /*< \brief (PMC_PCER0) Peripheral Clock 8 Enable /
119	#define PMC_PCER0_PID9 (0x1u << 9) /*< \brief (PMC_PCER0) Peripheral Clock 9 Enable /
120	#define PMC_PCER0_PID10 (0x1u << 10) /*< \brief (PMC_PCER0) Peripheral Clock 10 Enable /
121	#define PMC_PCER0_PID11 (0x1u << 11) /*< \brief (PMC_PCER0) Peripheral Clock 11 Enable /
122	#define PMC_PCER0_PID12 (0x1u << 12) /*< \brief (PMC_PCER0) Peripheral Clock 12 Enable /
123	#define PMC_PCER0_PID13 (0x1u << 13) /*< \brief (PMC_PCER0) Peripheral Clock 13 Enable /
124	#define PMC_PCER0_PID14 (0x1u << 14) /*< \brief (PMC_PCER0) Peripheral Clock 14 Enable /
125	#define PMC_PCER0_PID15 (0x1u << 15) /*< \brief (PMC_PCER0) Peripheral Clock 15 Enable /
126	#define PMC_PCER0_PID16 (0x1u << 16) /*< \brief (PMC_PCER0) Peripheral Clock 16 Enable /
127	#define PMC_PCER0_PID17 (0x1u << 17) /*< \brief (PMC_PCER0) Peripheral Clock 17 Enable /
128	#define PMC_PCER0_PID18 (0x1u << 18) /*< \brief (PMC_PCER0) Peripheral Clock 18 Enable /
129	#define PMC_PCER0_PID19 (0x1u << 19) /*< \brief (PMC_PCER0) Peripheral Clock 19 Enable /
130	#define PMC_PCER0_PID20 (0x1u << 20) /*< \brief (PMC_PCER0) Peripheral Clock 20 Enable /
131	#define PMC_PCER0_PID21 (0x1u << 21) /*< \brief (PMC_PCER0) Peripheral Clock 21 Enable /
132	#define PMC_PCER0_PID22 (0x1u << 22) /*< \brief (PMC_PCER0) Peripheral Clock 22 Enable /
133	#define PMC_PCER0_PID23 (0x1u << 23) /*< \brief (PMC_PCER0) Peripheral Clock 23 Enable /
134	#define PMC_PCER0_PID24 (0x1u << 24) /*< \brief (PMC_PCER0) Peripheral Clock 24 Enable /
135	#define PMC_PCER0_PID25 (0x1u << 25) /*< \brief (PMC_PCER0) Peripheral Clock 25 Enable /
136	#define PMC_PCER0_PID26 (0x1u << 26) /*< \brief (PMC_PCER0) Peripheral Clock 26 Enable /
137	#define PMC_PCER0_PID27 (0x1u << 27) /*< \brief (PMC_PCER0) Peripheral Clock 27 Enable /
138	#define PMC_PCER0_PID28 (0x1u << 28) /*< \brief (PMC_PCER0) Peripheral Clock 28 Enable /
139	#define PMC_PCER0_PID29 (0x1u << 29) /*< \brief (PMC_PCER0) Peripheral Clock 29 Enable /
140	#define PMC_PCER0_PID30 (0x1u << 30) /*< \brief (PMC_PCER0) Peripheral Clock 30 Enable /
141	#define PMC_PCER0_PID31 (0x1u << 31) /*< \brief (PMC_PCER0) Peripheral Clock 31 Enable /
142	/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
143	#define PMC_PCDR0_PID7 (0x1u << 7) /*< \brief (PMC_PCDR0) Peripheral Clock 7 Disable /
144	#define PMC_PCDR0_PID8 (0x1u << 8) /*< \brief (PMC_PCDR0) Peripheral Clock 8 Disable /
145	#define PMC_PCDR0_PID9 (0x1u << 9) /*< \brief (PMC_PCDR0) Peripheral Clock 9 Disable /
146	#define PMC_PCDR0_PID10 (0x1u << 10) /*< \brief (PMC_PCDR0) Peripheral Clock 10 Disable /
147	#define PMC_PCDR0_PID11 (0x1u << 11) /*< \brief (PMC_PCDR0) Peripheral Clock 11 Disable /
148	#define PMC_PCDR0_PID12 (0x1u << 12) /*< \brief (PMC_PCDR0) Peripheral Clock 12 Disable /
149	#define PMC_PCDR0_PID13 (0x1u << 13) /*< \brief (PMC_PCDR0) Peripheral Clock 13 Disable /
150	#define PMC_PCDR0_PID14 (0x1u << 14) /*< \brief (PMC_PCDR0) Peripheral Clock 14 Disable /
151	#define PMC_PCDR0_PID15 (0x1u << 15) /*< \brief (PMC_PCDR0) Peripheral Clock 15 Disable /
152	#define PMC_PCDR0_PID16 (0x1u << 16) /*< \brief (PMC_PCDR0) Peripheral Clock 16 Disable /
153	#define PMC_PCDR0_PID17 (0x1u << 17) /*< \brief (PMC_PCDR0) Peripheral Clock 17 Disable /
154	#define PMC_PCDR0_PID18 (0x1u << 18) /*< \brief (PMC_PCDR0) Peripheral Clock 18 Disable /
155	#define PMC_PCDR0_PID19 (0x1u << 19) /*< \brief (PMC_PCDR0) Peripheral Clock 19 Disable /
156	#define PMC_PCDR0_PID20 (0x1u << 20) /*< \brief (PMC_PCDR0) Peripheral Clock 20 Disable /
157	#define PMC_PCDR0_PID21 (0x1u << 21) /*< \brief (PMC_PCDR0) Peripheral Clock 21 Disable /
158	#define PMC_PCDR0_PID22 (0x1u << 22) /*< \brief (PMC_PCDR0) Peripheral Clock 22 Disable /
159	#define PMC_PCDR0_PID23 (0x1u << 23) /*< \brief (PMC_PCDR0) Peripheral Clock 23 Disable /
160	#define PMC_PCDR0_PID24 (0x1u << 24) /*< \brief (PMC_PCDR0) Peripheral Clock 24 Disable /
161	#define PMC_PCDR0_PID25 (0x1u << 25) /*< \brief (PMC_PCDR0) Peripheral Clock 25 Disable /
162	#define PMC_PCDR0_PID26 (0x1u << 26) /*< \brief (PMC_PCDR0) Peripheral Clock 26 Disable /
163	#define PMC_PCDR0_PID27 (0x1u << 27) /*< \brief (PMC_PCDR0) Peripheral Clock 27 Disable /
164	#define PMC_PCDR0_PID28 (0x1u << 28) /*< \brief (PMC_PCDR0) Peripheral Clock 28 Disable /
165	#define PMC_PCDR0_PID29 (0x1u << 29) /*< \brief (PMC_PCDR0) Peripheral Clock 29 Disable /
166	#define PMC_PCDR0_PID30 (0x1u << 30) /*< \brief (PMC_PCDR0) Peripheral Clock 30 Disable /
167	#define PMC_PCDR0_PID31 (0x1u << 31) /*< \brief (PMC_PCDR0) Peripheral Clock 31 Disable /
168	/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
169	#define PMC_PCSR0_PID7 (0x1u << 7) /*< \brief (PMC_PCSR0) Peripheral Clock 7 Status /
170	#define PMC_PCSR0_PID8 (0x1u << 8) /*< \brief (PMC_PCSR0) Peripheral Clock 8 Status /
171	#define PMC_PCSR0_PID9 (0x1u << 9) /*< \brief (PMC_PCSR0) Peripheral Clock 9 Status /
172	#define PMC_PCSR0_PID10 (0x1u << 10) /*< \brief (PMC_PCSR0) Peripheral Clock 10 Status /
173	#define PMC_PCSR0_PID11 (0x1u << 11) /*< \brief (PMC_PCSR0) Peripheral Clock 11 Status /
174	#define PMC_PCSR0_PID12 (0x1u << 12) /*< \brief (PMC_PCSR0) Peripheral Clock 12 Status /
175	#define PMC_PCSR0_PID13 (0x1u << 13) /*< \brief (PMC_PCSR0) Peripheral Clock 13 Status /
176	#define PMC_PCSR0_PID14 (0x1u << 14) /*< \brief (PMC_PCSR0) Peripheral Clock 14 Status /
177	#define PMC_PCSR0_PID15 (0x1u << 15) /*< \brief (PMC_PCSR0) Peripheral Clock 15 Status /
178	#define PMC_PCSR0_PID16 (0x1u << 16) /*< \brief (PMC_PCSR0) Peripheral Clock 16 Status /
179	#define PMC_PCSR0_PID17 (0x1u << 17) /*< \brief (PMC_PCSR0) Peripheral Clock 17 Status /
180	#define PMC_PCSR0_PID18 (0x1u << 18) /*< \brief (PMC_PCSR0) Peripheral Clock 18 Status /
181	#define PMC_PCSR0_PID19 (0x1u << 19) /*< \brief (PMC_PCSR0) Peripheral Clock 19 Status /
182	#define PMC_PCSR0_PID20 (0x1u << 20) /*< \brief (PMC_PCSR0) Peripheral Clock 20 Status /
183	#define PMC_PCSR0_PID21 (0x1u << 21) /*< \brief (PMC_PCSR0) Peripheral Clock 21 Status /
184	#define PMC_PCSR0_PID22 (0x1u << 22) /*< \brief (PMC_PCSR0) Peripheral Clock 22 Status /
185	#define PMC_PCSR0_PID23 (0x1u << 23) /*< \brief (PMC_PCSR0) Peripheral Clock 23 Status /
186	#define PMC_PCSR0_PID24 (0x1u << 24) /*< \brief (PMC_PCSR0) Peripheral Clock 24 Status /
187	#define PMC_PCSR0_PID25 (0x1u << 25) /*< \brief (PMC_PCSR0) Peripheral Clock 25 Status /
188	#define PMC_PCSR0_PID26 (0x1u << 26) /*< \brief (PMC_PCSR0) Peripheral Clock 26 Status /
189	#define PMC_PCSR0_PID27 (0x1u << 27) /*< \brief (PMC_PCSR0) Peripheral Clock 27 Status /
190	#define PMC_PCSR0_PID28 (0x1u << 28) /*< \brief (PMC_PCSR0) Peripheral Clock 28 Status /
191	#define PMC_PCSR0_PID29 (0x1u << 29) /*< \brief (PMC_PCSR0) Peripheral Clock 29 Status /
192	#define PMC_PCSR0_PID30 (0x1u << 30) /*< \brief (PMC_PCSR0) Peripheral Clock 30 Status /
193	#define PMC_PCSR0_PID31 (0x1u << 31) /*< \brief (PMC_PCSR0) Peripheral Clock 31 Status /
194	/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
195	#define CKGR_UCKR_UPLLEN (0x1u << 16) /*< \brief (CKGR_UCKR) UTMI PLL Enable /
196	#define CKGR_UCKR_UPLLCOUNT_Pos 20
197	#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /*< \brief (CKGR_UCKR) UTMI PLL Start-up Time /
198	#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
199	/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
200	#define CKGR_MOR_MOSCXTEN (0x1u << 0) /*< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Enable /
201	#define CKGR_MOR_MOSCXTBY (0x1u << 1) /*< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Bypass /
202	#define CKGR_MOR_WAITMODE (0x1u << 2) /*< \brief (CKGR_MOR) Wait Mode Command (Write-only) /
203	#define CKGR_MOR_MOSCRCEN (0x1u << 3) /*< \brief (CKGR_MOR) 4/8/12 MHz On-Chip RC Oscillator Enable /
204	#define CKGR_MOR_MOSCRCF_Pos 4
205	#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /*< \brief (CKGR_MOR) 4/8/12 MHz RC Oscillator Frequency Selection /
206	#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
207	#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /*< \brief (CKGR_MOR) The RC oscillator frequency is at 4 MHz (default) /
208	#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /*< \brief (CKGR_MOR) The RC oscillator frequency is at 8 MHz /
209	#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /*< \brief (CKGR_MOR) The RC oscillator frequency is at 12 MHz /
210	#define CKGR_MOR_MOSCXTST_Pos 8
211	#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /*< \brief (CKGR_MOR) 3 to 20 MHz Crystal Oscillator Start-up Time /
212	#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
213	#define CKGR_MOR_KEY_Pos 16
214	#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /*< \brief (CKGR_MOR) Write Access Password /
215	#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
216	#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /*< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. /
217	#define CKGR_MOR_MOSCSEL (0x1u << 24) /*< \brief (CKGR_MOR) Main Clock Oscillator Selection /
218	#define CKGR_MOR_CFDEN (0x1u << 25) /*< \brief (CKGR_MOR) Clock Failure Detector Enable /
219	#define CKGR_MOR_XT32KFME (0x1u << 26) /*< \brief (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable /
220	/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
221	#define CKGR_MCFR_MAINF_Pos 0
222	#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /*< \brief (CKGR_MCFR) Main Clock Frequency /
223	#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
224	#define CKGR_MCFR_MAINFRDY (0x1u << 16) /*< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready /
225	#define CKGR_MCFR_RCMEAS (0x1u << 20) /*< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) /
226	#define CKGR_MCFR_CCSS (0x1u << 24) /*< \brief (CKGR_MCFR) Counter Clock Source Selection /
227	/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
228	#define CKGR_PLLAR_DIVA_Pos 0
229	#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /*< \brief (CKGR_PLLAR) PLLA Front End Divider /
230	#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
231	#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /*< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. /
232	#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /*< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. /
233	#define CKGR_PLLAR_PLLACOUNT_Pos 8
234	#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /*< \brief (CKGR_PLLAR) PLLA Counter /
235	#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
236	#define CKGR_PLLAR_MULA_Pos 16
237	#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /*< \brief (CKGR_PLLAR) PLLA Multiplier /
238	#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
239	#define CKGR_PLLAR_ONE (0x1u << 29) /*< \brief (CKGR_PLLAR) Must Be Set to 1 /
240	/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
241	#define PMC_MCKR_CSS_Pos 0
242	#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /*< \brief (PMC_MCKR) Master Clock Source Selection /
243	#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
244	#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /*< \brief (PMC_MCKR) Slow Clock is selected /
245	#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /*< \brief (PMC_MCKR) Main Clock is selected /
246	#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /*< \brief (PMC_MCKR) PLLA Clock is selected /
247	#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /*< \brief (PMC_MCKR) Divided UPLL Clock is selected /
248	#define PMC_MCKR_PRES_Pos 4
249	#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /*< \brief (PMC_MCKR) Processor Clock Prescaler /
250	#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
251	#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /*< \brief (PMC_MCKR) Selected clock /
252	#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 2 /
253	#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 4 /
254	#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 8 /
255	#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 16 /
256	#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 32 /
257	#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 64 /
258	#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /*< \brief (PMC_MCKR) Selected clock divided by 3 /
259	#define PMC_MCKR_MDIV_Pos 8
260	#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /*< \brief (PMC_MCKR) Master Clock Division /
261	#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
262	#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /*< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. /
263	#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /*< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. /
264	#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /*< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. /
265	#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /*< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. /
266	#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /*< \brief (PMC_MCKR) UPLL Divisor by 2 /
267	/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
268	#define PMC_USB_USBS (0x1u << 0) /*< \brief (PMC_USB) USB Input Clock Selection /
269	#define PMC_USB_USBDIV_Pos 8
270	#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /*< \brief (PMC_USB) Divider for USB Clock /
271	#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
272	/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
273	#define PMC_PCK_CSS_Pos 0
274	#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /*< \brief (PMC_PCK[7]) Master Clock Source Selection /
275	#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
276	#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /*< \brief (PMC_PCK[7]) Slow Clock is selected /
277	#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /*< \brief (PMC_PCK[7]) Main Clock is selected /
278	#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /*< \brief (PMC_PCK[7]) PLLA Clock is selected /
279	#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /*< \brief (PMC_PCK[7]) Divided UPLL Clock is selected /
280	#define PMC_PCK_CSS_MCK (0x4u << 0) /*< \brief (PMC_PCK[7]) Master Clock is selected /
281	#define PMC_PCK_PRES_Pos 4
282	#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /*< \brief (PMC_PCK[7]) Programmable Clock Prescaler /
283	#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
284	/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
285	#define PMC_IER_MOSCXTS (0x1u << 0) /*< \brief (PMC_IER) 3 to 20 MHz Crystal Oscillator Status Interrupt Enable /
286	#define PMC_IER_LOCKA (0x1u << 1) /*< \brief (PMC_IER) PLLA Lock Interrupt Enable /
287	#define PMC_IER_MCKRDY (0x1u << 3) /*< \brief (PMC_IER) Master Clock Ready Interrupt Enable /
288	#define PMC_IER_LOCKU (0x1u << 6) /*< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable /
289	#define PMC_IER_PCKRDY0 (0x1u << 8) /*< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable /
290	#define PMC_IER_PCKRDY1 (0x1u << 9) /*< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable /
291	#define PMC_IER_PCKRDY2 (0x1u << 10) /*< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable /
292	#define PMC_IER_PCKRDY3 (0x1u << 11) /*< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable /
293	#define PMC_IER_PCKRDY4 (0x1u << 12) /*< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable /
294	#define PMC_IER_PCKRDY5 (0x1u << 13) /*< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable /
295	#define PMC_IER_PCKRDY6 (0x1u << 14) /*< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable /
296	#define PMC_IER_MOSCSELS (0x1u << 16) /*< \brief (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable /
297	#define PMC_IER_MOSCRCS (0x1u << 17) /*< \brief (PMC_IER) 4/8/12 MHz RC Oscillator Status Interrupt Enable /
298	#define PMC_IER_CFDEV (0x1u << 18) /*< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable /
299	#define PMC_IER_XT32KERR (0x1u << 21) /*< \brief (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable /
300	/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
301	#define PMC_IDR_MOSCXTS (0x1u << 0) /*< \brief (PMC_IDR) 3 to 20 MHz Crystal Oscillator Status Interrupt Disable /
302	#define PMC_IDR_LOCKA (0x1u << 1) /*< \brief (PMC_IDR) PLLA Lock Interrupt Disable /
303	#define PMC_IDR_MCKRDY (0x1u << 3) /*< \brief (PMC_IDR) Master Clock Ready Interrupt Disable /
304	#define PMC_IDR_LOCKU (0x1u << 6) /*< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable /
305	#define PMC_IDR_PCKRDY0 (0x1u << 8) /*< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable /
306	#define PMC_IDR_PCKRDY1 (0x1u << 9) /*< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable /
307	#define PMC_IDR_PCKRDY2 (0x1u << 10) /*< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable /
308	#define PMC_IDR_PCKRDY3 (0x1u << 11) /*< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable /
309	#define PMC_IDR_PCKRDY4 (0x1u << 12) /*< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable /
310	#define PMC_IDR_PCKRDY5 (0x1u << 13) /*< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable /
311	#define PMC_IDR_PCKRDY6 (0x1u << 14) /*< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable /
312	#define PMC_IDR_MOSCSELS (0x1u << 16) /*< \brief (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable /
313	#define PMC_IDR_MOSCRCS (0x1u << 17) /*< \brief (PMC_IDR) 4/8/12 MHz RC Status Interrupt Disable /
314	#define PMC_IDR_CFDEV (0x1u << 18) /*< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable /
315	#define PMC_IDR_XT32KERR (0x1u << 21) /*< \brief (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable /
316	/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
317	#define PMC_SR_MOSCXTS (0x1u << 0) /*< \brief (PMC_SR) 3 to 20 MHz Crystal Oscillator Status /
318	#define PMC_SR_LOCKA (0x1u << 1) /*< \brief (PMC_SR) PLLA Lock Status /
319	#define PMC_SR_MCKRDY (0x1u << 3) /*< \brief (PMC_SR) Master Clock Status /
320	#define PMC_SR_LOCKU (0x1u << 6) /*< \brief (PMC_SR) UTMI PLL Lock Status /
321	#define PMC_SR_OSCSELS (0x1u << 7) /*< \brief (PMC_SR) Slow Clock Source Oscillator Selection /
322	#define PMC_SR_PCKRDY0 (0x1u << 8) /*< \brief (PMC_SR) Programmable Clock Ready Status /
323	#define PMC_SR_PCKRDY1 (0x1u << 9) /*< \brief (PMC_SR) Programmable Clock Ready Status /
324	#define PMC_SR_PCKRDY2 (0x1u << 10) /*< \brief (PMC_SR) Programmable Clock Ready Status /
325	#define PMC_SR_PCKRDY3 (0x1u << 11) /*< \brief (PMC_SR) Programmable Clock Ready Status /
326	#define PMC_SR_PCKRDY4 (0x1u << 12) /*< \brief (PMC_SR) Programmable Clock Ready Status /
327	#define PMC_SR_PCKRDY5 (0x1u << 13) /*< \brief (PMC_SR) Programmable Clock Ready Status /
328	#define PMC_SR_PCKRDY6 (0x1u << 14) /*< \brief (PMC_SR) Programmable Clock Ready Status /
329	#define PMC_SR_MOSCSELS (0x1u << 16) /*< \brief (PMC_SR) Main Clock Source Oscillator Selection Status /
330	#define PMC_SR_MOSCRCS (0x1u << 17) /*< \brief (PMC_SR) 4/8/12 MHz RC Oscillator Status /
331	#define PMC_SR_CFDEV (0x1u << 18) /*< \brief (PMC_SR) Clock Failure Detector Event /
332	#define PMC_SR_CFDS (0x1u << 19) /*< \brief (PMC_SR) Clock Failure Detector Status /
333	#define PMC_SR_FOS (0x1u << 20) /*< \brief (PMC_SR) Clock Failure Detector Fault Output Status /
334	#define PMC_SR_XT32KERR (0x1u << 21) /*< \brief (PMC_SR) Slow Crystal Oscillator Error /
335	/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
336	#define PMC_IMR_MOSCXTS (0x1u << 0) /*< \brief (PMC_IMR) 3 to 20 MHz Crystal Oscillator Status Interrupt Mask /
337	#define PMC_IMR_LOCKA (0x1u << 1) /*< \brief (PMC_IMR) PLLA Lock Interrupt Mask /
338	#define PMC_IMR_MCKRDY (0x1u << 3) /*< \brief (PMC_IMR) Master Clock Ready Interrupt Mask /
339	#define PMC_IMR_LOCKU (0x1u << 6) /*< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask /
340	#define PMC_IMR_PCKRDY0 (0x1u << 8) /*< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask /
341	#define PMC_IMR_PCKRDY1 (0x1u << 9) /*< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask /
342	#define PMC_IMR_PCKRDY2 (0x1u << 10) /*< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask /
343	#define PMC_IMR_PCKRDY3 (0x1u << 11) /*< \brief (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask /
344	#define PMC_IMR_PCKRDY4 (0x1u << 12) /*< \brief (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask /
345	#define PMC_IMR_PCKRDY5 (0x1u << 13) /*< \brief (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask /
346	#define PMC_IMR_PCKRDY6 (0x1u << 14) /*< \brief (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask /
347	#define PMC_IMR_MOSCSELS (0x1u << 16) /*< \brief (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask /
348	#define PMC_IMR_MOSCRCS (0x1u << 17) /*< \brief (PMC_IMR) 4/8/12 MHz RC Status Interrupt Mask /
349	#define PMC_IMR_CFDEV (0x1u << 18) /*< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask /
350	#define PMC_IMR_XT32KERR (0x1u << 21) /*< \brief (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask /
351	/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
352	#define PMC_FSMR_FSTT0 (0x1u << 0) /*< \brief (PMC_FSMR) Fast Startup Input Enable 0 /
353	#define PMC_FSMR_FSTT1 (0x1u << 1) /*< \brief (PMC_FSMR) Fast Startup Input Enable 1 /
354	#define PMC_FSMR_FSTT2 (0x1u << 2) /*< \brief (PMC_FSMR) Fast Startup Input Enable 2 /
355	#define PMC_FSMR_FSTT3 (0x1u << 3) /*< \brief (PMC_FSMR) Fast Startup Input Enable 3 /
356	#define PMC_FSMR_FSTT4 (0x1u << 4) /*< \brief (PMC_FSMR) Fast Startup Input Enable 4 /
357	#define PMC_FSMR_FSTT5 (0x1u << 5) /*< \brief (PMC_FSMR) Fast Startup Input Enable 5 /
358	#define PMC_FSMR_FSTT6 (0x1u << 6) /*< \brief (PMC_FSMR) Fast Startup Input Enable 6 /
359	#define PMC_FSMR_FSTT7 (0x1u << 7) /*< \brief (PMC_FSMR) Fast Startup Input Enable 7 /
360	#define PMC_FSMR_FSTT8 (0x1u << 8) /*< \brief (PMC_FSMR) Fast Startup Input Enable 8 /
361	#define PMC_FSMR_FSTT9 (0x1u << 9) /*< \brief (PMC_FSMR) Fast Startup Input Enable 9 /
362	#define PMC_FSMR_FSTT10 (0x1u << 10) /*< \brief (PMC_FSMR) Fast Startup Input Enable 10 /
363	#define PMC_FSMR_FSTT11 (0x1u << 11) /*< \brief (PMC_FSMR) Fast Startup Input Enable 11 /
364	#define PMC_FSMR_FSTT12 (0x1u << 12) /*< \brief (PMC_FSMR) Fast Startup Input Enable 12 /
365	#define PMC_FSMR_FSTT13 (0x1u << 13) /*< \brief (PMC_FSMR) Fast Startup Input Enable 13 /
366	#define PMC_FSMR_FSTT14 (0x1u << 14) /*< \brief (PMC_FSMR) Fast Startup Input Enable 14 /
367	#define PMC_FSMR_FSTT15 (0x1u << 15) /*< \brief (PMC_FSMR) Fast Startup Input Enable 15 /
368	#define PMC_FSMR_RTTAL (0x1u << 16) /*< \brief (PMC_FSMR) RTT Alarm Enable /
369	#define PMC_FSMR_RTCAL (0x1u << 17) /*< \brief (PMC_FSMR) RTC Alarm Enable /
370	#define PMC_FSMR_USBAL (0x1u << 18) /*< \brief (PMC_FSMR) USB Alarm Enable /
371	#define PMC_FSMR_LPM (0x1u << 20) /*< \brief (PMC_FSMR) Low-power Mode /
372	#define PMC_FSMR_FLPM_Pos 21
373	#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /*< \brief (PMC_FSMR) Flash Low-power Mode /
374	#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
375	#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /*< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode /
376	#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /*< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode /
377	#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /*< \brief (PMC_FSMR) Idle mode /
378	#define PMC_FSMR_FFLPM (0x1u << 23) /*< \brief (PMC_FSMR) Force Flash Low-power Mode /
379	/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
380	#define PMC_FSPR_FSTP0 (0x1u << 0) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 0 /
381	#define PMC_FSPR_FSTP1 (0x1u << 1) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 1 /
382	#define PMC_FSPR_FSTP2 (0x1u << 2) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 2 /
383	#define PMC_FSPR_FSTP3 (0x1u << 3) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 3 /
384	#define PMC_FSPR_FSTP4 (0x1u << 4) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 4 /
385	#define PMC_FSPR_FSTP5 (0x1u << 5) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 5 /
386	#define PMC_FSPR_FSTP6 (0x1u << 6) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 6 /
387	#define PMC_FSPR_FSTP7 (0x1u << 7) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 7 /
388	#define PMC_FSPR_FSTP8 (0x1u << 8) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 8 /
389	#define PMC_FSPR_FSTP9 (0x1u << 9) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 9 /
390	#define PMC_FSPR_FSTP10 (0x1u << 10) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 10 /
391	#define PMC_FSPR_FSTP11 (0x1u << 11) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 11 /
392	#define PMC_FSPR_FSTP12 (0x1u << 12) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 12 /
393	#define PMC_FSPR_FSTP13 (0x1u << 13) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 13 /
394	#define PMC_FSPR_FSTP14 (0x1u << 14) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 14 /
395	#define PMC_FSPR_FSTP15 (0x1u << 15) /*< \brief (PMC_FSPR) Fast Startup Input Polarity 15 /
396	/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
397	#define PMC_FOCR_FOCLR (0x1u << 0) /*< \brief (PMC_FOCR) Fault Output Clear /
398	/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
399	#define PMC_WPMR_WPEN (0x1u << 0) /*< \brief (PMC_WPMR) Write Protection Enable /
400	#define PMC_WPMR_WPKEY_Pos 8
401	#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /*< \brief (PMC_WPMR) Write Protection Key /
402	#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
403	#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /*< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. /
404	/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
405	#define PMC_WPSR_WPVS (0x1u << 0) /*< \brief (PMC_WPSR) Write Protection Violation Status /
406	#define PMC_WPSR_WPVSRC_Pos 8
407	#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /*< \brief (PMC_WPSR) Write Protection Violation Source /
408	/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
409	#define PMC_PCER1_PID32 (0x1u << 0) /*< \brief (PMC_PCER1) Peripheral Clock 32 Enable /
410	#define PMC_PCER1_PID33 (0x1u << 1) /*< \brief (PMC_PCER1) Peripheral Clock 33 Enable /
411	#define PMC_PCER1_PID34 (0x1u << 2) /*< \brief (PMC_PCER1) Peripheral Clock 34 Enable /
412	#define PMC_PCER1_PID35 (0x1u << 3) /*< \brief (PMC_PCER1) Peripheral Clock 35 Enable /
413	#define PMC_PCER1_PID37 (0x1u << 5) /*< \brief (PMC_PCER1) Peripheral Clock 37 Enable /
414	#define PMC_PCER1_PID39 (0x1u << 7) /*< \brief (PMC_PCER1) Peripheral Clock 39 Enable /
415	#define PMC_PCER1_PID40 (0x1u << 8) /*< \brief (PMC_PCER1) Peripheral Clock 40 Enable /
416	#define PMC_PCER1_PID41 (0x1u << 9) /*< \brief (PMC_PCER1) Peripheral Clock 41 Enable /
417	#define PMC_PCER1_PID42 (0x1u << 10) /*< \brief (PMC_PCER1) Peripheral Clock 42 Enable /
418	#define PMC_PCER1_PID43 (0x1u << 11) /*< \brief (PMC_PCER1) Peripheral Clock 43 Enable /
419	#define PMC_PCER1_PID44 (0x1u << 12) /*< \brief (PMC_PCER1) Peripheral Clock 44 Enable /
420	#define PMC_PCER1_PID45 (0x1u << 13) /*< \brief (PMC_PCER1) Peripheral Clock 45 Enable /
421	#define PMC_PCER1_PID46 (0x1u << 14) /*< \brief (PMC_PCER1) Peripheral Clock 46 Enable /
422	#define PMC_PCER1_PID47 (0x1u << 15) /*< \brief (PMC_PCER1) Peripheral Clock 47 Enable /
423	#define PMC_PCER1_PID48 (0x1u << 16) /*< \brief (PMC_PCER1) Peripheral Clock 48 Enable /
424	#define PMC_PCER1_PID49 (0x1u << 17) /*< \brief (PMC_PCER1) Peripheral Clock 49 Enable /
425	#define PMC_PCER1_PID50 (0x1u << 18) /*< \brief (PMC_PCER1) Peripheral Clock 50 Enable /
426	#define PMC_PCER1_PID51 (0x1u << 19) /*< \brief (PMC_PCER1) Peripheral Clock 51 Enable /
427	#define PMC_PCER1_PID52 (0x1u << 20) /*< \brief (PMC_PCER1) Peripheral Clock 52 Enable /
428	#define PMC_PCER1_PID53 (0x1u << 21) /*< \brief (PMC_PCER1) Peripheral Clock 53 Enable /
429	#define PMC_PCER1_PID56 (0x1u << 24) /*< \brief (PMC_PCER1) Peripheral Clock 56 Enable /
430	#define PMC_PCER1_PID57 (0x1u << 25) /*< \brief (PMC_PCER1) Peripheral Clock 57 Enable /
431	#define PMC_PCER1_PID58 (0x1u << 26) /*< \brief (PMC_PCER1) Peripheral Clock 58 Enable /
432	#define PMC_PCER1_PID59 (0x1u << 27) /*< \brief (PMC_PCER1) Peripheral Clock 59 Enable /
433	#define PMC_PCER1_PID60 (0x1u << 28) /*< \brief (PMC_PCER1) Peripheral Clock 60 Enable /
434	/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
435	#define PMC_PCDR1_PID32 (0x1u << 0) /*< \brief (PMC_PCDR1) Peripheral Clock 32 Disable /
436	#define PMC_PCDR1_PID33 (0x1u << 1) /*< \brief (PMC_PCDR1) Peripheral Clock 33 Disable /
437	#define PMC_PCDR1_PID34 (0x1u << 2) /*< \brief (PMC_PCDR1) Peripheral Clock 34 Disable /
438	#define PMC_PCDR1_PID35 (0x1u << 3) /*< \brief (PMC_PCDR1) Peripheral Clock 35 Disable /
439	#define PMC_PCDR1_PID37 (0x1u << 5) /*< \brief (PMC_PCDR1) Peripheral Clock 37 Disable /
440	#define PMC_PCDR1_PID39 (0x1u << 7) /*< \brief (PMC_PCDR1) Peripheral Clock 39 Disable /
441	#define PMC_PCDR1_PID40 (0x1u << 8) /*< \brief (PMC_PCDR1) Peripheral Clock 40 Disable /
442	#define PMC_PCDR1_PID41 (0x1u << 9) /*< \brief (PMC_PCDR1) Peripheral Clock 41 Disable /
443	#define PMC_PCDR1_PID42 (0x1u << 10) /*< \brief (PMC_PCDR1) Peripheral Clock 42 Disable /
444	#define PMC_PCDR1_PID43 (0x1u << 11) /*< \brief (PMC_PCDR1) Peripheral Clock 43 Disable /
445	#define PMC_PCDR1_PID44 (0x1u << 12) /*< \brief (PMC_PCDR1) Peripheral Clock 44 Disable /
446	#define PMC_PCDR1_PID45 (0x1u << 13) /*< \brief (PMC_PCDR1) Peripheral Clock 45 Disable /
447	#define PMC_PCDR1_PID46 (0x1u << 14) /*< \brief (PMC_PCDR1) Peripheral Clock 46 Disable /
448	#define PMC_PCDR1_PID47 (0x1u << 15) /*< \brief (PMC_PCDR1) Peripheral Clock 47 Disable /
449	#define PMC_PCDR1_PID48 (0x1u << 16) /*< \brief (PMC_PCDR1) Peripheral Clock 48 Disable /
450	#define PMC_PCDR1_PID49 (0x1u << 17) /*< \brief (PMC_PCDR1) Peripheral Clock 49 Disable /
451	#define PMC_PCDR1_PID50 (0x1u << 18) /*< \brief (PMC_PCDR1) Peripheral Clock 50 Disable /
452	#define PMC_PCDR1_PID51 (0x1u << 19) /*< \brief (PMC_PCDR1) Peripheral Clock 51 Disable /
453	#define PMC_PCDR1_PID52 (0x1u << 20) /*< \brief (PMC_PCDR1) Peripheral Clock 52 Disable /
454	#define PMC_PCDR1_PID53 (0x1u << 21) /*< \brief (PMC_PCDR1) Peripheral Clock 53 Disable /
455	#define PMC_PCDR1_PID56 (0x1u << 24) /*< \brief (PMC_PCDR1) Peripheral Clock 56 Disable /
456	#define PMC_PCDR1_PID57 (0x1u << 25) /*< \brief (PMC_PCDR1) Peripheral Clock 57 Disable /
457	#define PMC_PCDR1_PID58 (0x1u << 26) /*< \brief (PMC_PCDR1) Peripheral Clock 58 Disable /
458	#define PMC_PCDR1_PID59 (0x1u << 27) /*< \brief (PMC_PCDR1) Peripheral Clock 59 Disable /
459	#define PMC_PCDR1_PID60 (0x1u << 28) /*< \brief (PMC_PCDR1) Peripheral Clock 60 Disable /
460	/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
461	#define PMC_PCSR1_PID32 (0x1u << 0) /*< \brief (PMC_PCSR1) Peripheral Clock 32 Status /
462	#define PMC_PCSR1_PID33 (0x1u << 1) /*< \brief (PMC_PCSR1) Peripheral Clock 33 Status /
463	#define PMC_PCSR1_PID34 (0x1u << 2) /*< \brief (PMC_PCSR1) Peripheral Clock 34 Status /
464	#define PMC_PCSR1_PID35 (0x1u << 3) /*< \brief (PMC_PCSR1) Peripheral Clock 35 Status /
465	#define PMC_PCSR1_PID37 (0x1u << 5) /*< \brief (PMC_PCSR1) Peripheral Clock 37 Status /
466	#define PMC_PCSR1_PID39 (0x1u << 7) /*< \brief (PMC_PCSR1) Peripheral Clock 39 Status /
467	#define PMC_PCSR1_PID40 (0x1u << 8) /*< \brief (PMC_PCSR1) Peripheral Clock 40 Status /
468	#define PMC_PCSR1_PID41 (0x1u << 9) /*< \brief (PMC_PCSR1) Peripheral Clock 41 Status /
469	#define PMC_PCSR1_PID42 (0x1u << 10) /*< \brief (PMC_PCSR1) Peripheral Clock 42 Status /
470	#define PMC_PCSR1_PID43 (0x1u << 11) /*< \brief (PMC_PCSR1) Peripheral Clock 43 Status /
471	#define PMC_PCSR1_PID44 (0x1u << 12) /*< \brief (PMC_PCSR1) Peripheral Clock 44 Status /
472	#define PMC_PCSR1_PID45 (0x1u << 13) /*< \brief (PMC_PCSR1) Peripheral Clock 45 Status /
473	#define PMC_PCSR1_PID46 (0x1u << 14) /*< \brief (PMC_PCSR1) Peripheral Clock 46 Status /
474	#define PMC_PCSR1_PID47 (0x1u << 15) /*< \brief (PMC_PCSR1) Peripheral Clock 47 Status /
475	#define PMC_PCSR1_PID48 (0x1u << 16) /*< \brief (PMC_PCSR1) Peripheral Clock 48 Status /
476	#define PMC_PCSR1_PID49 (0x1u << 17) /*< \brief (PMC_PCSR1) Peripheral Clock 49 Status /
477	#define PMC_PCSR1_PID50 (0x1u << 18) /*< \brief (PMC_PCSR1) Peripheral Clock 50 Status /
478	#define PMC_PCSR1_PID51 (0x1u << 19) /*< \brief (PMC_PCSR1) Peripheral Clock 51 Status /
479	#define PMC_PCSR1_PID52 (0x1u << 20) /*< \brief (PMC_PCSR1) Peripheral Clock 52 Status /
480	#define PMC_PCSR1_PID53 (0x1u << 21) /*< \brief (PMC_PCSR1) Peripheral Clock 53 Status /
481	#define PMC_PCSR1_PID56 (0x1u << 24) /*< \brief (PMC_PCSR1) Peripheral Clock 56 Status /
482	#define PMC_PCSR1_PID57 (0x1u << 25) /*< \brief (PMC_PCSR1) Peripheral Clock 57 Status /
483	#define PMC_PCSR1_PID58 (0x1u << 26) /*< \brief (PMC_PCSR1) Peripheral Clock 58 Status /
484	#define PMC_PCSR1_PID59 (0x1u << 27) /*< \brief (PMC_PCSR1) Peripheral Clock 59 Status /
485	#define PMC_PCSR1_PID60 (0x1u << 28) /*< \brief (PMC_PCSR1) Peripheral Clock 60 Status /
486	/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
487	#define PMC_PCR_PID_Pos 0
488	#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /*< \brief (PMC_PCR) Peripheral ID /
489	#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
490	#define PMC_PCR_CMD (0x1u << 12) /*< \brief (PMC_PCR) Command /
491	#define PMC_PCR_EN (0x1u << 28) /*< \brief (PMC_PCR) Enable /
492	/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
493	#define PMC_OCR_CAL4_Pos 0
494	#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /*< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz /
495	#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
496	#define PMC_OCR_SEL4 (0x1u << 7) /*< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz /
497	#define PMC_OCR_CAL8_Pos 8
498	#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /*< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz /
499	#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
500	#define PMC_OCR_SEL8 (0x1u << 15) /*< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz /
501	#define PMC_OCR_CAL12_Pos 16
502	#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /*< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz /
503	#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
504	#define PMC_OCR_SEL12 (0x1u << 23) /*< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz /
505	/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
506	#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /*< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable /
507	#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /*< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable /
508	#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /*< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable /
509	#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /*< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable /
510	#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /*< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable /
511	#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /*< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable /
512	#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /*< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable /
513	#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /*< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable /
514	#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /*< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable /
515	#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /*< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable /
516	#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /*< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable /
517	#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /*< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable /
518	#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /*< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable /
519	#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /*< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable /
520	#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /*< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable /
521	#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /*< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable /
522	#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /*< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable /
523	#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /*< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable /
524	#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /*< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable /
525	#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /*< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable /
526	#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /*< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable /
527	#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /*< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable /
528	#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /*< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable /
529	#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /*< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable /
530	#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /*< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable /
531	/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
532	#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /*< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable /
533	#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /*< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable /
534	#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /*< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable /
535	#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /*< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable /
536	#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /*< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable /
537	#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /*< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable /
538	#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /*< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable /
539	#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /*< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable /
540	#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /*< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable /
541	#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /*< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable /
542	#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /*< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable /
543	#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /*< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable /
544	#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /*< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable /
545	#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /*< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable /
546	#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /*< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable /
547	#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /*< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable /
548	#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /*< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable /
549	#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /*< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable /
550	#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /*< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable /
551	#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /*< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable /
552	#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /*< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable /
553	#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /*< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable /
554	#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /*< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable /
555	#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /*< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable /
556	#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /*< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable /
557	/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
558	#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /*< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status /
559	#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /*< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status /
560	#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /*< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status /
561	#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /*< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status /
562	#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /*< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status /
563	#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /*< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status /
564	#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /*< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status /
565	#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /*< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status /
566	#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /*< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status /
567	#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /*< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status /
568	#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /*< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status /
569	#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /*< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status /
570	#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /*< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status /
571	#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /*< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status /
572	#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /*< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status /
573	#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /*< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status /
574	#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /*< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status /
575	#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /*< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status /
576	#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /*< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status /
577	#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /*< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status /
578	#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /*< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status /
579	#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /*< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status /
580	#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /*< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status /
581	#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /*< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status /
582	#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /*< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status /
583	/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
584	#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /*< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status /
585	#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /*< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status /
586	#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /*< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status /
587	#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /*< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status /
588	#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /*< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status /
589	#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /*< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status /
590	#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /*< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status /
591	#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /*< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status /
592	#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /*< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status /
593	#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /*< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status /
594	#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /*< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status /
595	#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /*< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status /
596	#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /*< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status /
597	#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /*< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status /
598	#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /*< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status /
599	#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /*< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status /
600	#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /*< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status /
601	#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /*< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status /
602	#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /*< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status /
603	#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /*< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status /
604	#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /*< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status /
605	#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /*< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status /
606	#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /*< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status /
607	#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /*< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status /
608	#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /*< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status /
609	/* -------- PMC_PMMR : (PMC Offset: 0x0130) PLL Maximum Multiplier Value Register -------- */
610	#define PMC_PMMR_PLLA_MMAX_Pos 0
611	#define PMC_PMMR_PLLA_MMAX_Msk (0x7ffu << PMC_PMMR_PLLA_MMAX_Pos) /*< \brief (PMC_PMMR) PLLA Maximum Allowed Multiplier Value /
612	#define PMC_PMMR_PLLA_MMAX(value) ((PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)))
613	/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
614	#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /*< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable /
615	#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /*< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable /
616	#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /*< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable /
617	#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /*< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable /
618	#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /*< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable /
619	#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /*< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable /
620	#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /*< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable /
621	#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /*< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable /
622	#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /*< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable /
623	#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /*< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable /
624	#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /*< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable /
625	#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /*< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable /
626	#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /*< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable /
627	#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /*< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable /
628	#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /*< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable /
629	#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /*< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable /
630	#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /*< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable /
631	#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /*< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable /
632	#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /*< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable /
633	#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /*< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable /
634	#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /*< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable /
635	#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /*< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable /
636	#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /*< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable /
637	#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /*< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable /
638	#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /*< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable /
639	/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
640	#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /*< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable /
641	#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /*< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable /
642	#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /*< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable /
643	#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /*< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable /
644	#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /*< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable /
645	#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /*< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable /
646	#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /*< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable /
647	#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /*< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable /
648	#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /*< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable /
649	#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /*< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable /
650	#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /*< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable /
651	#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /*< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable /
652	#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /*< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable /
653	#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /*< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable /
654	#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /*< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable /
655	#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /*< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable /
656	#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /*< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable /
657	#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /*< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable /
658	#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /*< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable /
659	#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /*< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable /
660	#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /*< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable /
661	#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /*< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable /
662	#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /*< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable /
663	#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /*< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable /
664	#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /*< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable /
665	/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
666	#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /*< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status /
667	#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /*< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status /
668	#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /*< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status /
669	#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /*< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status /
670	#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /*< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status /
671	#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /*< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status /
672	#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /*< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status /
673	#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /*< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status /
674	#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /*< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status /
675	#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /*< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status /
676	#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /*< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status /
677	#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /*< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status /
678	#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /*< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status /
679	#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /*< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status /
680	#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /*< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status /
681	#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /*< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status /
682	#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /*< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status /
683	#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /*< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status /
684	#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /*< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status /
685	#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /*< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status /
686	#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /*< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status /
687	#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /*< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status /
688	#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /*< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status /
689	#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /*< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status /
690	#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /*< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status /
691	/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
692	#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /*< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status /
693	#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /*< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status /
694	#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /*< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status /
695	#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /*< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status /
696	#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /*< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status /
697	#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /*< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status /
698	#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /*< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status /
699	#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /*< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status /
700	#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /*< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status /
701	#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /*< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status /
702	#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /*< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status /
703	#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /*< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status /
704	#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /*< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status /
705	#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /*< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status /
706	#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /*< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status /
707	#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /*< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status /
708	#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /*< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status /
709	#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /*< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status /
710	#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /*< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status /
711	#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /*< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status /
712	#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /*< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status /
713	#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /*< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status /
714	#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /*< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status /
715	#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /*< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status /
716	#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /*< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status /
717	/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
718	#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /*< \brief (PMC_SLPWK_AIPR) Activity In Progress /
719
720	/@}/
721
722
723	#endif /* _SAME70_PMC_COMPONENT_ */

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source: rtems/bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h @ 2afb22b

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