source: rtems/bsps/arm/atsam/include/libchip/include/gmac.h @ 2afb22b

Last change on this file since 2afb22b was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 14.1 KB
Line 
1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
7/* All rights reserved.                                                         */
8/*                                                                              */
9/* Redistribution and use in source and binary forms, with or without           */
10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
13/* this list of conditions and the disclaimer below.                            */
14/*                                                                              */
15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
17/*                                                                              */
18/* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
28/* ---------------------------------------------------------------------------- */
29
30/** \file */
31
32/** \addtogroup gmac_module
33 * @{
34 * Provides the interface to configure and use the GMAC peripheral.
35 *
36 * \section gmac_usage Usage
37 * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls
38 *   are also available, such as:
39 *   - GMAC_SetSpeed(): Setup GMAC working clock.
40 *   - GMAC_FullDuplexEnable(): Working in full duplex or not.
41 *   - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF).
42 *   - ...
43 * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls
44 *   can modify with:
45 *   - GMAC_ReceiveEnable(): Enable/Disable Rx.
46 *   - GMAC_TransmitEnable(): Enable/Disable Tx.
47 *   - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving.
48 *   - ...
49 * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(),
50 *   GMAC_GetItMask() and GMAC_GetItStatus().
51 * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus()
52 *   GMAC_ClearTxStatus() and GMAC_ClearRxStatus().
53 * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(),
54 *   GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define
55 *   by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor.
56 * - Manage PHY through GMAC is performed by
57 *   - GMAC_ManagementEnable(): Enable/Disable PHY management.
58 *   - GMAC_PHYMaintain(): Execute PHY management commands.
59 *   - GMAC_PHYData(): Return PHY management data.
60 *   - GMAC_IsIdle(): Check if PHY is idle.
61 * - Setup GMAC parameters with following functions:
62 *   - GMAC_SetHash(): Set Hash value.
63 *   - GMAC_SetAddress(): Set MAC address.
64 * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()
65 * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable()
66 *
67 * For more accurate information, please look at the GMAC section of the
68 * Datasheet.
69 *
70 * \sa \ref gmacd_module
71 *
72 * Related files:\n
73 * gmac.c\n
74 * gmac.h.\n
75 *
76 *   \defgroup gmac_defines GMAC Defines
77 *   \defgroup gmac_structs GMAC Data Structs
78 *   \defgroup gmac_functions GMAC Functions
79 */
80/**@}*/
81
82#ifndef _GMAC_H
83#define _GMAC_H
84
85/*----------------------------------------------------------------------------
86 *        Headers
87 *----------------------------------------------------------------------------*/
88#include "chip.h"
89
90#include <stdint.h>
91
92#ifdef __cplusplus
93extern "C" {
94#endif
95
96/*----------------------------------------------------------------------------
97 *        Defines
98 *----------------------------------------------------------------------------*/
99/** \addtogroup gmac_defines
100        @{*/
101
102#define NUM_GMAC_QUEUES 3
103/// Board GMAC base address
104
105#define GMAC_DUPLEX_HALF 0
106#define GMAC_DUPLEX_FULL 1
107
108//
109#define GMAC_SPEED_10M      0
110#define GMAC_SPEED_100M     1
111#define GMAC_SPEED_1000M    2
112
113/*------------------------------------------------------------------------------
114                            Definitions
115------------------------------------------------------------------------------
116*/
117/// The buffer addresses written into the descriptors must be aligned so the
118/// last few bits are zero.  These bits have special meaning for the GMAC
119/// peripheral and cannot be used as part of the address.
120#define GMAC_ADDRESS_MASK   ((unsigned int)0xFFFFFFFC)
121#define GMAC_LENGTH_FRAME   ((unsigned int)0x3FFF)    /// Length of frame mask
122
123// receive buffer descriptor bits
124#define GMAC_RX_OWNERSHIP_BIT   (1u <<  0)
125#define GMAC_RX_WRAP_BIT        (1u <<  1)
126#define GMAC_RX_SOF_BIT         (1u << 14)
127#define GMAC_RX_EOF_BIT         (1u << 15)
128
129// Transmit buffer descriptor bits
130#define GMAC_TX_LAST_BUFFER_BIT (1u << 15)
131#define GMAC_TX_WRAP_BIT        (1u << 30)
132#define GMAC_TX_USED_BIT        (1u << 31)
133#define GMAC_TX_RLE_BIT         (1u << 29) /// Retry Limit Exceeded
134#define GMAC_TX_UND_BIT         (1u << 28) /// Tx Buffer Under-run
135#define GMAC_TX_ERR_BIT         (1u << 27) /// Exhausted in mid-frame
136#define GMAC_TX_ERR_BITS  \
137        (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
138
139// Interrupt bits
140#define GMAC_INT_RX_BITS  \
141        (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)
142#define GMAC_INT_TX_ERR_BITS  \
143        (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP)
144#define GMAC_INT_TX_BITS  \
145        (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)
146// Interrupt Status bits
147#define GMAC_INT_RX_STATUS_BITS  \
148        (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR)
149#define GMAC_INT_TX_STATUS_ERR_BITS  \
150        (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP)
151/*----------------------------------------------------------------------------
152 *        Types
153 *----------------------------------------------------------------------------*/
154/** \addtogroup gmac_structs
155        @{*/
156
157/* This is the list of GMAC queue */
158typedef enum  {
159        GMAC_QUE_0 = 0,
160        GMAC_QUE_1 = 1,
161        GMAC_QUE_2 = 2
162} gmacQueList_t;
163
164/** Receive buffer descriptor struct */
165typedef struct _GmacRxDescriptor {
166        union _GmacRxAddr {
167                uint32_t val;
168                struct _GmacRxAddrBM {
169                        uint32_t bOwnership: 1,  /**< User clear, GMAC set this to one once
170                                         it has successfully written a frame to
171                                         memory */
172                                         bWrap: 1,      /**< Marks last descriptor in receive buffer */
173                                         addrDW: 30;    /**< Address in number of DW */
174                } bm;
175        } addr;                    /**< Address, Wrap & Ownership */
176        union _GmacRxStatus {
177                uint32_t val;
178                struct _GmacRxStatusBM {
179                        uint32_t len: 12,               /** Length of frame including FCS */
180                                         offset: 2,              /** Receive buffer offset,
181                                                bits 13:12 of frame length for jumbo
182                                                frame */
183                                         bSof: 1,               /** Start of frame */
184                                         bEof: 1,               /** End of frame */
185                                         bCFI: 1,               /** Concatenation Format Indicator */
186                                         vlanPriority: 3,       /** VLAN priority (if VLAN detected) */
187                                         bPriorityDetected: 1,  /** Priority tag detected */
188                                         bVlanDetected: 1,      /**< VLAN tag detected */
189                                         bTypeIDMatch: 1,       /**< Type ID match */
190                                         bAddr4Match: 1,        /**< Address register 4 match */
191                                         bAddr3Match: 1,        /**< Address register 3 match */
192                                         bAddr2Match: 1,        /**< Address register 2 match */
193                                         bAddr1Match: 1,        /**< Address register 1 match */
194                                         reserved: 1,
195                                         bExtAddrMatch: 1,      /**< External address match */
196                                         bUniHashMatch: 1,      /**< Unicast hash match */
197                                         bMultiHashMatch: 1,    /**< Multicast hash match */
198                                         bBroadcastDetected: 1;  /**< Global all ones broadcast
199                                                 address detected */
200                } bm;
201        } status;
202} sGmacRxDescriptor;    /* GCC */
203
204/** Transmit buffer descriptor struct */
205typedef struct _GmacTxDescriptor {
206        uint32_t addr;
207        union _GmacTxStatus {
208                uint32_t val;
209                struct _GmacTxStatusBM {
210                        uint32_t len: 11,       /**< Length of buffer */
211                                         reserved: 4,
212                                         bLastBuffer: 1, /**< Last buffer (in the current frame) */
213                                         bNoCRC: 1,     /**< No CRC */
214                                         reserved1: 10,
215                                         bExhausted: 1, /**< Buffer exhausted in mid frame */
216                                         bUnderrun: 1,  /**< Transmit under run */
217                                         bError: 1,     /**< Retry limit exceeded, error detected */
218                                         bWrap: 1,      /**< Marks last descriptor in TD list */
219                                         bUsed: 1;       /**< User clear, GMAC sets this once a frame
220                                         has been successfully transmitted */
221                } bm;
222        } status;
223} sGmacTxDescriptor;     /* GCC */
224
225/**     @}*/
226
227//-----------------------------------------------------------------------------
228//         PHY Exported functions
229//-----------------------------------------------------------------------------
230extern uint8_t GMAC_IsIdle(Gmac *pGmac);
231extern void GMAC_PHYMaintain(Gmac      *pGmac,
232                                                         uint8_t   bPhyAddr,
233                                                         uint8_t   bRegAddr,
234                                                         uint8_t   bRW,
235                                                         uint16_t  wData);
236extern uint16_t GMAC_PHYData(Gmac *pGmac);
237extern void GMAC_ClearStatistics(Gmac *pGmac);
238extern void GMAC_IncreaseStatistics(Gmac *pGmac);
239extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);
240extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck);
241extern void GMAC_EnableMdio(Gmac *pGmac);
242extern void GMAC_DisableMdio(Gmac *pGmac);
243extern void GMAC_EnableMII(Gmac *pGmac);
244extern void GMAC_EnableRMII(Gmac *pGmac);
245extern void GMAC_EnableGMII(Gmac *pGmac);
246extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);
247extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources,
248                                                  gmacQueList_t queueIdx);
249extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
250extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources,
251                                                   gmacQueList_t queueIdx);
252extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
253extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx);
254extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx);
255extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);
256extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);
257extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);
258extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);
259extern void GMAC_ReceiveEnable(Gmac *pGmac, uint8_t bEnaDis);
260extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);
261extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);
262extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr,
263                                                        gmacQueList_t queueIdx);
264extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
265extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr,
266                                                        gmacQueList_t queueIdx);
267extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
268extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);
269extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);
270extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);
271extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT,
272                                                          uint32_t dwMacB);
273extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);
274extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);
275extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg,
276                                                          gmacQueList_t queueIdx);
277extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx);
278extern uint32_t GMAC_GetConfigure(Gmac *pGmac);
279extern void GMAC_TransmissionStart(Gmac *pGmac);
280extern void GMAC_TransmissionHalt(Gmac *pGmac);
281extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);
282
283void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx);
284
285void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx,
286                                                        uint32_t regVal);
287
288void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx);
289
290void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx,
291                                                         uint32_t regVal);
292
293void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx,
294                                                   uint16_t etherType);
295
296void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg,
297                                                  uint16_t c1Reg);
298
299void GMAC_EnableCbsQueA(Gmac *pGmac);
300
301void GMAC_DisableCbsQueA(Gmac *pGmac);
302
303void GMAC_EnableCbsQueB(Gmac *pGmac);
304
305void GMAC_DisableCbsQueB(Gmac *pGmac);
306
307void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA);
308
309void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB);
310
311void GMAC_SetTsuTmrIncReg(Gmac *pGmac, uint32_t nanoSec);
312
313uint16_t GMAC_GetPtpEvtMsgRxdMsbSec(Gmac *pGmac);
314
315uint32_t GMAC_GetPtpEvtMsgRxdLsbSec(Gmac *pGmac);
316
317uint32_t GMAC_GetPtpEvtMsgRxdNanoSec(Gmac *pGmac);
318
319void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31,
320                                                uint32_t nanosec);
321
322void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec);
323
324void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31);
325
326void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47);
327
328uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac);
329
330uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac);
331
332uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac);
333
334uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac);
335
336uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac);
337
338uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac);
339
340uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac);
341
342uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac);
343
344#ifdef __cplusplus
345}
346#endif
347
348#endif // #ifndef GMAC_H
349
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