source: rtems/bsps/arm/atsam/include/libchip/include/gmac.h

Last change on this file was 4c36a525, checked in by Christian Mauderer <christian.mauderer@…>, on 03/19/18 at 07:58:39

bsp/atsam: Fix GMAC Rx Descriptor fields.
  • Property mode set to 100644
File size: 14.2 KB
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1/* ---------------------------------------------------------------------------- */
2/*                  Atmel Microcontroller Software Support                      */
3/*                       SAM Software Package License                           */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation                                        */
6/*                                                                              */
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10/* modification, are permitted provided that the following condition is met:    */
11/*                                                                              */
12/* - Redistributions of source code must retain the above copyright notice,     */
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15/* Atmel's name may not be used to endorse or promote products derived from     */
16/* this software without specific prior written permission.                     */
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28/* ---------------------------------------------------------------------------- */
29
30/** \file */
31
32/** \addtogroup gmac_module
33 * @{
34 * Provides the interface to configure and use the GMAC peripheral.
35 *
36 * \section gmac_usage Usage
37 * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls
38 *   are also available, such as:
39 *   - GMAC_SetSpeed(): Setup GMAC working clock.
40 *   - GMAC_FullDuplexEnable(): Working in full duplex or not.
41 *   - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF).
42 *   - ...
43 * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls
44 *   can modify with:
45 *   - GMAC_ReceiveEnable(): Enable/Disable Rx.
46 *   - GMAC_TransmitEnable(): Enable/Disable Tx.
47 *   - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving.
48 *   - ...
49 * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(),
50 *   GMAC_GetItMask() and GMAC_GetItStatus().
51 * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus()
52 *   GMAC_ClearTxStatus() and GMAC_ClearRxStatus().
53 * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(),
54 *   GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define
55 *   by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor.
56 * - Manage PHY through GMAC is performed by
57 *   - GMAC_ManagementEnable(): Enable/Disable PHY management.
58 *   - GMAC_PHYMaintain(): Execute PHY management commands.
59 *   - GMAC_PHYData(): Return PHY management data.
60 *   - GMAC_IsIdle(): Check if PHY is idle.
61 * - Setup GMAC parameters with following functions:
62 *   - GMAC_SetHash(): Set Hash value.
63 *   - GMAC_SetAddress(): Set MAC address.
64 * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()
65 * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable()
66 *
67 * For more accurate information, please look at the GMAC section of the
68 * Datasheet.
69 *
70 * \sa \ref gmacd_module
71 *
72 * Related files:\n
73 * gmac.c\n
74 * gmac.h.\n
75 *
76 *   \defgroup gmac_defines GMAC Defines
77 *   \defgroup gmac_structs GMAC Data Structs
78 *   \defgroup gmac_functions GMAC Functions
79 */
80/**@}*/
81
82#ifndef _GMAC_H
83#define _GMAC_H
84
85/*----------------------------------------------------------------------------
86 *        Headers
87 *----------------------------------------------------------------------------*/
88#include "chip.h"
89
90#include <stdint.h>
91
92#ifdef __cplusplus
93extern "C" {
94#endif
95
96/*----------------------------------------------------------------------------
97 *        Defines
98 *----------------------------------------------------------------------------*/
99/** \addtogroup gmac_defines
100        @{*/
101
102#define NUM_GMAC_QUEUES 3
103/// Board GMAC base address
104
105#define GMAC_DUPLEX_HALF 0
106#define GMAC_DUPLEX_FULL 1
107
108//
109#define GMAC_SPEED_10M      0
110#define GMAC_SPEED_100M     1
111#define GMAC_SPEED_1000M    2
112
113/*------------------------------------------------------------------------------
114                            Definitions
115------------------------------------------------------------------------------
116*/
117/// The buffer addresses written into the descriptors must be aligned so the
118/// last few bits are zero.  These bits have special meaning for the GMAC
119/// peripheral and cannot be used as part of the address.
120#define GMAC_ADDRESS_MASK   ((unsigned int)0xFFFFFFFC)
121#define GMAC_LENGTH_FRAME   ((unsigned int)0x3FFF)    /// Length of frame mask
122
123// receive buffer descriptor bits
124#define GMAC_RX_OWNERSHIP_BIT   (1u <<  0)
125#define GMAC_RX_WRAP_BIT        (1u <<  1)
126#define GMAC_RX_SOF_BIT         (1u << 14)
127#define GMAC_RX_EOF_BIT         (1u << 15)
128
129// Transmit buffer descriptor bits
130#define GMAC_TX_LAST_BUFFER_BIT (1u << 15)
131#define GMAC_TX_WRAP_BIT        (1u << 30)
132#define GMAC_TX_USED_BIT        (1u << 31)
133#define GMAC_TX_RLE_BIT         (1u << 29) /// Retry Limit Exceeded
134#define GMAC_TX_UND_BIT         (1u << 28) /// Tx Buffer Under-run
135#define GMAC_TX_ERR_BIT         (1u << 27) /// Exhausted in mid-frame
136#define GMAC_TX_ERR_BITS  \
137        (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
138
139// Interrupt bits
140#define GMAC_INT_RX_BITS  \
141        (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)
142#define GMAC_INT_TX_ERR_BITS  \
143        (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP)
144#define GMAC_INT_TX_BITS  \
145        (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)
146// Interrupt Status bits
147#define GMAC_INT_RX_STATUS_BITS  \
148        (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR)
149#define GMAC_INT_TX_STATUS_ERR_BITS  \
150        (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP)
151
152// Rx descriptor status flags
153#define   GMAC_RXDESC_ST_CKSUM_RESULT_NOT_CHECKED        (0)
154#define   GMAC_RXDESC_ST_CKSUM_RESULT_IP_CHECKED         (1)
155#define   GMAC_RXDESC_ST_CKSUM_RESULT_IP_AND_TCP_CHECKED (2)
156#define   GMAC_RXDESC_ST_CKSUM_RESULT_IP_AND_UDP_CHECKED (3)
157
158/*----------------------------------------------------------------------------
159 *        Types
160 *----------------------------------------------------------------------------*/
161/** \addtogroup gmac_structs
162        @{*/
163
164/* This is the list of GMAC queue */
165typedef enum  {
166        GMAC_QUE_0 = 0,
167        GMAC_QUE_1 = 1,
168        GMAC_QUE_2 = 2
169} gmacQueList_t;
170
171/** Receive buffer descriptor struct */
172typedef struct _GmacRxDescriptor {
173        union _GmacRxAddr {
174                uint32_t val;
175                struct _GmacRxAddrBM {
176                        uint32_t bOwnership: 1,  /**< User clear, GMAC set this to one once
177                                         it has successfully written a frame to
178                                         memory */
179                                         bWrap: 1,      /**< Marks last descriptor in receive buffer */
180                                         addrDW: 30;    /**< Address in number of DW */
181                } bm;
182        } addr;                    /**< Address, Wrap & Ownership */
183        union _GmacRxStatus {
184                uint32_t val;
185                struct _GmacRxStatusBM {
186                        uint32_t len: 12,               /** Length of frame including FCS */
187                                         offset: 2,              /** Receive buffer offset,
188                                                bits 13:12 of frame length for jumbo
189                                                frame */
190                                         bSof: 1,               /** Start of frame */
191                                         bEof: 1,               /** End of frame */
192                                         bCFI: 1,               /** Concatenation Format Indicator */
193                                         vlanPriority: 3,       /** VLAN priority (if VLAN detected) */
194                                         bPriorityDetected: 1,  /** Priority tag detected */
195                                         bVlanDetected: 1,      /**< VLAN tag detected */
196                                         typeIDMatchOrCksumResult: 2,
197                                         bTypeIDMatchFoundOrCksumSNAPState: 1,
198                                         specAddrMatchRegister: 2,
199                                         bSpecAddrMatchFound: 1,
200                                         reserved: 1,
201                                         bUniHashMatch: 1,      /**< Unicast hash match */
202                                         bMultiHashMatch: 1,    /**< Multicast hash match */
203                                         bBroadcastDetected: 1;  /**< Global all ones broadcast
204                                                 address detected */
205                } bm;
206        } status;
207} sGmacRxDescriptor;    /* GCC */
208
209/** Transmit buffer descriptor struct */
210typedef struct _GmacTxDescriptor {
211        uint32_t addr;
212        union _GmacTxStatus {
213                uint32_t val;
214                struct _GmacTxStatusBM {
215                        uint32_t len: 11,       /**< Length of buffer */
216                                         reserved: 4,
217                                         bLastBuffer: 1, /**< Last buffer (in the current frame) */
218                                         bNoCRC: 1,     /**< No CRC */
219                                         reserved1: 10,
220                                         bExhausted: 1, /**< Buffer exhausted in mid frame */
221                                         bUnderrun: 1,  /**< Transmit under run */
222                                         bError: 1,     /**< Retry limit exceeded, error detected */
223                                         bWrap: 1,      /**< Marks last descriptor in TD list */
224                                         bUsed: 1;       /**< User clear, GMAC sets this once a frame
225                                         has been successfully transmitted */
226                } bm;
227        } status;
228} sGmacTxDescriptor;     /* GCC */
229
230/**     @}*/
231
232//-----------------------------------------------------------------------------
233//         PHY Exported functions
234//-----------------------------------------------------------------------------
235extern uint8_t GMAC_IsIdle(Gmac *pGmac);
236extern void GMAC_PHYMaintain(Gmac      *pGmac,
237                                                         uint8_t   bPhyAddr,
238                                                         uint8_t   bRegAddr,
239                                                         uint8_t   bRW,
240                                                         uint16_t  wData);
241extern uint16_t GMAC_PHYData(Gmac *pGmac);
242extern void GMAC_ClearStatistics(Gmac *pGmac);
243extern void GMAC_IncreaseStatistics(Gmac *pGmac);
244extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);
245extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck);
246extern void GMAC_EnableMdio(Gmac *pGmac);
247extern void GMAC_DisableMdio(Gmac *pGmac);
248extern void GMAC_EnableMII(Gmac *pGmac);
249extern void GMAC_EnableRMII(Gmac *pGmac);
250extern void GMAC_EnableGMII(Gmac *pGmac);
251extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);
252extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources,
253                                                  gmacQueList_t queueIdx);
254extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
255extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources,
256                                                   gmacQueList_t queueIdx);
257extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
258extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx);
259extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx);
260extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);
261extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);
262extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);
263extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);
264extern void GMAC_ReceiveEnable(Gmac *pGmac, uint8_t bEnaDis);
265extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);
266extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);
267extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr,
268                                                        gmacQueList_t queueIdx);
269extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
270extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr,
271                                                        gmacQueList_t queueIdx);
272extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
273extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);
274extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);
275extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);
276extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT,
277                                                          uint32_t dwMacB);
278extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);
279extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);
280extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg,
281                                                          gmacQueList_t queueIdx);
282extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx);
283extern uint32_t GMAC_GetConfigure(Gmac *pGmac);
284extern void GMAC_TransmissionStart(Gmac *pGmac);
285extern void GMAC_TransmissionHalt(Gmac *pGmac);
286extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);
287
288void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx);
289
290void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx,
291                                                        uint32_t regVal);
292
293void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx);
294
295void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx,
296                                                         uint32_t regVal);
297
298void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx,
299                                                   uint16_t etherType);
300
301void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg,
302                                                  uint16_t c1Reg);
303
304void GMAC_EnableCbsQueA(Gmac *pGmac);
305
306void GMAC_DisableCbsQueA(Gmac *pGmac);
307
308void GMAC_EnableCbsQueB(Gmac *pGmac);
309
310void GMAC_DisableCbsQueB(Gmac *pGmac);
311
312void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA);
313
314void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB);
315
316void GMAC_SetTsuTmrIncReg(Gmac *pGmac, uint32_t nanoSec);
317
318uint16_t GMAC_GetPtpEvtMsgRxdMsbSec(Gmac *pGmac);
319
320uint32_t GMAC_GetPtpEvtMsgRxdLsbSec(Gmac *pGmac);
321
322uint32_t GMAC_GetPtpEvtMsgRxdNanoSec(Gmac *pGmac);
323
324void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31,
325                                                uint32_t nanosec);
326
327void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec);
328
329void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31);
330
331void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47);
332
333uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac);
334
335uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac);
336
337uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac);
338
339uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac);
340
341uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac);
342
343uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac);
344
345uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac);
346
347uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac);
348
349#ifdef __cplusplus
350}
351#endif
352
353#endif // #ifndef GMAC_H
354
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