1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | /*---------------------------------------------------------------------------- |
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31 | * Headers |
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32 | *----------------------------------------------------------------------------*/ |
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33 | #include "chip.h" |
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34 | |
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35 | #include <assert.h> |
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36 | |
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37 | /*---------------------------------------------------------------------------- |
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38 | * Definition |
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39 | *----------------------------------------------------------------------------*/ |
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40 | #define TWITIMEOUTMAX 400 |
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41 | static uint32_t dmaWriteChannel, dmaReadChannel; |
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42 | |
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43 | extern uint32_t twi_send_stop; |
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44 | |
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45 | /*---------------------------------------------------------------------------- |
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46 | * Types |
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47 | *----------------------------------------------------------------------------*/ |
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48 | |
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49 | /** TWI driver callback function.*/ |
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50 | typedef void (*TwiCallback)(Async *); |
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51 | |
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52 | /** \brief TWI asynchronous transfer descriptor.*/ |
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53 | typedef struct _AsyncTwi { |
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54 | |
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55 | /** Asynchronous transfer status. */ |
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56 | volatile uint8_t status; |
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57 | /** Callback function to invoke when transfer completes or fails.*/ |
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58 | TwiCallback callback; |
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59 | /** Pointer to the data buffer.*/ |
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60 | uint8_t *pData; |
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61 | /** Total number of bytes to transfer.*/ |
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62 | uint32_t num; |
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63 | /** Number of already transferred bytes.*/ |
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64 | uint32_t transferred; |
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65 | |
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66 | } AsyncTwi; |
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67 | |
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68 | /** |
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69 | * \brief Initializes a TWI DMA Read channel. |
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70 | */ |
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71 | static void TWID_DmaInitializeRead(TwihsDma *pTwiXdma) |
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72 | { |
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73 | /* Allocate a XDMA channel, Read accesses into TWI_THR */ |
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74 | dmaReadChannel = XDMAD_AllocateChannel(pTwiXdma->pTwiDma, pTwiXdma->Twi_id, |
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75 | XDMAD_TRANSFER_MEMORY); |
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76 | |
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77 | if (dmaReadChannel == XDMAD_ALLOC_FAILED) |
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78 | printf("-E- Can't allocate XDMA channel\n\r"); |
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79 | |
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80 | XDMAD_PrepareChannel(pTwiXdma->pTwiDma, dmaReadChannel); |
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81 | } |
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82 | |
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83 | /** |
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84 | * \brief Initializes a TWI DMA write channel. |
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85 | */ |
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86 | static void TWID_DmaInitializeWrite(TwihsDma *pTwiXdma) |
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87 | { |
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88 | /* Allocate a XDMA channel, Write accesses into TWI_THR */ |
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89 | dmaWriteChannel = XDMAD_AllocateChannel(pTwiXdma->pTwiDma, |
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90 | XDMAD_TRANSFER_MEMORY, |
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91 | pTwiXdma->Twi_id); |
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92 | |
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93 | if (dmaWriteChannel == XDMAD_ALLOC_FAILED) |
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94 | printf("-E- Can't allocate XDMA channel\n\r"); |
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95 | |
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96 | XDMAD_PrepareChannel(pTwiXdma->pTwiDma, dmaWriteChannel); |
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97 | } |
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98 | |
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99 | /** |
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100 | * \brief Configure xDMA write linker list for TWI transfer. |
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101 | */ |
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102 | static uint8_t TWID_XdmaConfigureWrite(TwihsDma *pTwiXdma, uint8_t *buf, |
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103 | uint32_t len) |
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104 | { |
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105 | uint32_t xdmaCndc, Thr, xdmaInt; |
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106 | sXdmadCfg xdmadTxCfg; |
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107 | |
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108 | Thr = (uint32_t) & (TWIHS0->TWIHS_THR); |
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109 | |
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110 | if (pTwiXdma->Twi_id == ID_TWIHS1) |
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111 | Thr = (uint32_t) & (TWIHS1->TWIHS_THR); |
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112 | |
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113 | if (pTwiXdma->Twi_id == ID_TWIHS2) |
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114 | Thr = (uint32_t) & (TWIHS2->TWIHS_THR); |
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115 | |
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116 | xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | |
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117 | XDMA_UBC_NDE_FETCH_DIS | |
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118 | XDMA_UBC_NSEN_UPDATED | len; |
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119 | |
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120 | xdmadTxCfg.mbr_sa = (uint32_t)buf; |
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121 | xdmadTxCfg.mbr_da = Thr; |
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122 | xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | |
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123 | XDMAC_CC_MBSIZE_SINGLE | |
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124 | XDMAC_CC_DSYNC_MEM2PER | |
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125 | XDMAC_CC_CSIZE_CHK_1 | |
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126 | XDMAC_CC_DWIDTH_BYTE | |
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127 | XDMAC_CC_SIF_AHB_IF1 | |
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128 | XDMAC_CC_DIF_AHB_IF1 | |
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129 | XDMAC_CC_SAM_INCREMENTED_AM | |
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130 | XDMAC_CC_DAM_FIXED_AM | |
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131 | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( |
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132 | pTwiXdma->Twi_id, XDMAD_TRANSFER_TX)); |
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133 | |
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134 | xdmadTxCfg.mbr_bc = 0; |
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135 | xdmadTxCfg.mbr_sus = 0; |
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136 | xdmadTxCfg.mbr_dus = 0; |
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137 | xdmaCndc = 0; |
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138 | |
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139 | xdmaInt = (XDMAC_CIE_BIE | |
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140 | XDMAC_CIE_RBIE | |
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141 | XDMAC_CIE_WBIE); |
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142 | |
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143 | if (XDMAD_ConfigureTransfer(pTwiXdma->pTwiDma, dmaWriteChannel, |
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144 | &xdmadTxCfg, xdmaCndc, 0, xdmaInt)) |
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145 | return USARTD_ERROR; |
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146 | |
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147 | return 0; |
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148 | } |
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149 | |
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150 | |
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151 | /** |
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152 | * \brief Configure xDMA read linker list for TWI transfer. |
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153 | */ |
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154 | static uint8_t TWID_XdmaConfigureRead(TwihsDma *pTwiXdma, uint8_t *buf, |
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155 | uint32_t len) |
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156 | { |
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157 | uint32_t xdmaCndc, Rhr, xdmaInt; |
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158 | sXdmadCfg xdmadRxCfg; |
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159 | |
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160 | Rhr = (uint32_t) & (TWIHS0->TWIHS_RHR); |
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161 | |
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162 | if (pTwiXdma->Twi_id == ID_TWIHS1) |
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163 | Rhr = (uint32_t) & (TWIHS1->TWIHS_RHR); |
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164 | |
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165 | if (pTwiXdma->Twi_id == ID_TWIHS2) |
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166 | Rhr = (uint32_t) & (TWIHS2->TWIHS_RHR); |
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167 | |
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168 | xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | |
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169 | XDMA_UBC_NDE_FETCH_DIS | |
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170 | XDMA_UBC_NDEN_UPDATED | |
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171 | len; |
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172 | |
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173 | xdmadRxCfg.mbr_da = (uint32_t)buf; |
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174 | xdmadRxCfg.mbr_sa = Rhr; |
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175 | |
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176 | xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | |
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177 | XDMAC_CC_MBSIZE_SINGLE | |
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178 | XDMAC_CC_DSYNC_PER2MEM | |
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179 | XDMAC_CC_CSIZE_CHK_1 | |
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180 | XDMAC_CC_DWIDTH_BYTE | |
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181 | XDMAC_CC_SIF_AHB_IF1 | |
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182 | XDMAC_CC_DIF_AHB_IF1 | |
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183 | XDMAC_CC_SAM_FIXED_AM | |
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184 | XDMAC_CC_DAM_INCREMENTED_AM | |
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185 | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( |
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186 | pTwiXdma->Twi_id , XDMAD_TRANSFER_RX)); |
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187 | |
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188 | xdmadRxCfg.mbr_bc = 0; |
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189 | xdmadRxCfg.mbr_sus = 0; |
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190 | xdmadRxCfg.mbr_dus = 0; |
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191 | xdmaCndc = 0; |
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192 | xdmaInt = (XDMAC_CIE_BIE | |
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193 | XDMAC_CIE_RBIE | |
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194 | XDMAC_CIE_WBIE); |
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195 | |
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196 | if (XDMAD_ConfigureTransfer(pTwiXdma->pTwiDma, dmaReadChannel, |
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197 | &xdmadRxCfg, xdmaCndc, 0, xdmaInt)) |
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198 | return 1; |
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199 | |
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200 | return 0; |
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201 | } |
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202 | |
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203 | /*---------------------------------------------------------------------------- |
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204 | * Global functions |
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205 | *----------------------------------------------------------------------------*/ |
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206 | |
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207 | /** |
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208 | * \brief Returns 1 if the given transfer has ended; otherwise returns 0. |
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209 | * \param pAsync Pointer to an Async instance. |
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210 | */ |
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211 | uint32_t ASYNC_IsFinished(Async *pAsync) |
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212 | { |
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213 | return (pAsync->status != ASYNC_STATUS_PENDING); |
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214 | } |
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215 | |
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216 | /** |
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217 | * \brief Initializes a TWI driver instance, using the given TWI peripheral. |
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218 | * \note The peripheral must have been initialized properly before calling this |
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219 | * function. |
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220 | * \param pTwid Pointer to the Twid instance to initialize. |
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221 | * \param pTwi Pointer to the TWI peripheral to use. |
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222 | */ |
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223 | void TWID_Initialize(Twid *pTwid, Twihs *pTwi) |
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224 | { |
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225 | TRACE_DEBUG("TWID_Initialize()\n\r"); |
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226 | assert(pTwid != NULL); |
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227 | assert(pTwi != NULL); |
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228 | |
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229 | /* Initialize driver. */ |
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230 | pTwid->pTwi = pTwi; |
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231 | pTwid->pTransfer = 0; |
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232 | } |
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233 | |
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234 | /** |
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235 | * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer |
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236 | * occurring on the bus. This function MUST be called by the interrupt service |
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237 | * routine of the TWI peripheral if asynchronous read/write are needed. |
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238 | * \param pTwid Pointer to a Twid instance. |
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239 | */ |
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240 | void TWID_Handler(Twid *pTwid) |
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241 | { |
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242 | uint8_t status; |
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243 | AsyncTwi *pTransfer; |
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244 | Twihs *pTwi; |
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245 | |
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246 | assert(pTwid != NULL); |
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247 | |
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248 | pTransfer = (AsyncTwi *)pTwid->pTransfer; |
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249 | assert(pTransfer != NULL); |
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250 | pTwi = pTwid->pTwi; |
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251 | assert(pTwi != NULL); |
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252 | |
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253 | /* Retrieve interrupt status */ |
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254 | status = TWI_GetMaskedStatus(pTwi); |
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255 | |
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256 | /* Byte received */ |
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257 | if (TWI_STATUS_RXRDY(status)) { |
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258 | |
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259 | pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi); |
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260 | pTransfer->transferred++; |
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261 | |
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262 | /* check for transfer finish */ |
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263 | if (pTransfer->transferred == pTransfer->num) { |
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264 | |
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265 | TWI_DisableIt(pTwi, TWIHS_IDR_RXRDY); |
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266 | TWI_EnableIt(pTwi, TWIHS_IER_TXCOMP); |
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267 | } |
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268 | /* Last byte? */ |
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269 | else if (pTransfer->transferred == (pTransfer->num - 1)) |
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270 | |
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271 | TWI_Stop(pTwi); |
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272 | } |
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273 | /* Byte sent*/ |
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274 | else if (TWI_STATUS_TXRDY(status)) { |
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275 | |
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276 | /* Transfer finished ? */ |
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277 | if (pTransfer->transferred == pTransfer->num) { |
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278 | |
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279 | TWI_DisableIt(pTwi, TWIHS_IDR_TXRDY); |
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280 | TWI_EnableIt(pTwi, TWIHS_IER_TXCOMP); |
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281 | TWI_SendSTOPCondition(pTwi); |
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282 | } |
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283 | /* Bytes remaining */ |
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284 | else { |
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285 | |
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286 | TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]); |
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287 | pTransfer->transferred++; |
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288 | } |
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289 | } |
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290 | /* Transfer complete*/ |
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291 | else if (TWI_STATUS_TXCOMP(status)) { |
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292 | |
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293 | TWI_DisableIt(pTwi, TWIHS_IDR_TXCOMP); |
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294 | pTransfer->status = 0; |
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295 | |
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296 | if (pTransfer->callback) |
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297 | pTransfer->callback((Async *) pTransfer); |
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298 | |
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299 | pTwid->pTransfer = 0; |
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300 | } |
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301 | } |
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302 | |
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303 | /** |
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304 | * \brief Asynchronously reads data from a slave on the TWI bus. An optional |
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305 | * callback function is triggered when the transfer is complete. |
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306 | * \param pTwid Pointer to a Twid instance. |
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307 | * \param address TWI slave address. |
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308 | * \param iaddress Optional slave internal address. |
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309 | * \param isize Internal address size in bytes. |
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310 | * \param pData Data buffer for storing received bytes. |
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311 | * \param num Number of bytes to read. |
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312 | * \param pAsync Asynchronous transfer descriptor. |
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313 | * \return 0 if the transfer has been started; otherwise returns a TWI error code. |
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314 | */ |
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315 | uint8_t TWID_Read( |
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316 | Twid *pTwid, |
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317 | uint8_t address, |
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318 | uint32_t iaddress, |
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319 | uint8_t isize, |
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320 | uint8_t *pData, |
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321 | uint32_t num, |
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322 | Async *pAsync) |
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323 | { |
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324 | Twihs *pTwi; |
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325 | AsyncTwi *pTransfer; |
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326 | uint32_t startTime; |
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327 | assert(pTwid != NULL); |
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328 | pTwi = pTwid->pTwi; |
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329 | pTransfer = (AsyncTwi *) pTwid->pTransfer; |
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330 | |
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331 | assert((address & 0x80) == 0); |
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332 | assert((iaddress & 0xFF000000) == 0); |
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333 | assert(isize < 4); |
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334 | |
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335 | /* Check that no transfer is already pending*/ |
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336 | if (pTransfer) { |
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337 | |
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338 | TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); |
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339 | return TWID_ERROR_BUSY; |
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340 | } |
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341 | |
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342 | /* In single data byte master read, the START and STOP must both be set */ |
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343 | twi_send_stop = (num == 1) ? 1 : 0; |
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344 | |
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345 | /* Asynchronous transfer*/ |
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346 | if (pAsync) { |
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347 | |
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348 | /* Update the transfer descriptor */ |
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349 | pTwid->pTransfer = pAsync; |
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350 | pTransfer = (AsyncTwi *) pAsync; |
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351 | pTransfer->status = ASYNC_STATUS_PENDING; |
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352 | pTransfer->pData = pData; |
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353 | pTransfer->num = num; |
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354 | pTransfer->transferred = 0; |
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355 | |
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356 | /* Enable read interrupt and start the transfer */ |
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357 | TWI_EnableIt(pTwi, TWIHS_IER_RXRDY); |
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358 | TWI_StartRead(pTwi, address, iaddress, isize); |
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359 | } |
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360 | /* Synchronous transfer*/ |
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361 | else { |
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362 | |
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363 | /* Start read*/ |
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364 | TWI_StartRead(pTwi, address, iaddress, isize); |
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365 | |
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366 | /* Read all bytes, setting STOP before the last byte*/ |
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367 | while (num > 0) { |
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368 | |
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369 | /* Last byte ?*/ |
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370 | if (num == 1) |
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371 | TWI_Stop(pTwi); |
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372 | |
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373 | /* Wait for byte then read and store it*/ |
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374 | startTime = GetTicks(); |
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375 | |
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376 | while (!TWI_ByteReceived(pTwi)) { |
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377 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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378 | TRACE_ERROR("TWID Timeout BR\n\r"); |
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379 | break; |
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380 | } |
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381 | } |
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382 | |
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383 | *pData++ = TWI_ReadByte(pTwi); |
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384 | num--; |
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385 | } |
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386 | |
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387 | /* Wait for transfer to be complete */ |
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388 | startTime = GetTicks(); |
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389 | |
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390 | while (!TWI_TransferComplete(pTwi)) { |
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391 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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392 | TRACE_ERROR("TWID Timeout TC\n\r"); |
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393 | break; |
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394 | } |
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395 | } |
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396 | } |
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397 | |
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398 | return 0; |
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399 | } |
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400 | |
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401 | /** |
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402 | * \brief Asynchronously sends data to a slave on the TWI bus. An optional |
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403 | * callback function is invoked whenever the transfer is complete. |
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404 | * \param pTwid Pointer to a Twid instance. |
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405 | * \param address TWI slave address. |
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406 | * \param iaddress Optional slave internal address. |
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407 | * \param isize Number of internal address bytes. |
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408 | * \param pData Data buffer for storing received bytes. |
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409 | * \param num Data buffer to send. |
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410 | * \param pAsync Asynchronous transfer descriptor. |
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411 | * \return 0 if the transfer has been started; otherwise returns a TWI error code. |
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412 | */ |
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413 | uint8_t TWID_Write( |
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414 | Twid *pTwid, |
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415 | uint8_t address, |
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416 | uint32_t iaddress, |
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417 | uint8_t isize, |
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418 | uint8_t *pData, |
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419 | uint32_t num, |
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420 | Async *pAsync) |
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421 | { |
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422 | Twihs *pTwi = pTwid->pTwi; |
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423 | uint32_t startTime; |
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424 | AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; |
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425 | |
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426 | assert(pTwi != NULL); |
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427 | assert((address & 0x80) == 0); |
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428 | assert((iaddress & 0xFF000000) == 0); |
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429 | assert(isize < 4); |
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430 | |
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431 | /* Check that no transfer is already pending */ |
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432 | if (pTransfer) { |
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433 | TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); |
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434 | return TWID_ERROR_BUSY; |
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435 | } |
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436 | |
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437 | /* Asynchronous transfer */ |
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438 | if (pAsync) { |
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439 | /* Update the transfer descriptor */ |
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440 | pTwid->pTransfer = pAsync; |
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441 | pTransfer = (AsyncTwi *) pAsync; |
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442 | pTransfer->status = ASYNC_STATUS_PENDING; |
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443 | pTransfer->pData = pData; |
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444 | pTransfer->num = num; |
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445 | pTransfer->transferred = 1; |
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446 | |
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447 | /* Enable write interrupt and start the transfer */ |
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448 | TWI_StartWrite(pTwi, address, iaddress, isize, *pData); |
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449 | TWI_EnableIt(pTwi, TWIHS_IER_TXRDY); |
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450 | |
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451 | } else { |
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452 | /* Synchronous transfer*/ |
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453 | // Start write |
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454 | TWI_StartWrite(pTwi, address, iaddress, isize, *pData++); |
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455 | num--; |
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456 | |
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457 | /* Send all bytes */ |
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458 | while (num > 0) { |
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459 | /* Wait before sending the next byte */ |
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460 | startTime = GetTicks(); |
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461 | |
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462 | while (!TWI_ByteSent(pTwi)) { |
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463 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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464 | TRACE_ERROR("TWID Timeout BS\n\r"); |
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465 | break; |
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466 | } |
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467 | } |
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468 | |
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469 | TWI_WriteByte(pTwi, *pData++); |
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470 | num--; |
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471 | } |
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472 | |
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473 | /* Wait for actual end of transfer */ |
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474 | startTime = GetTicks(); |
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475 | /* Send a STOP condition */ |
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476 | TWI_SendSTOPCondition(pTwi); |
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477 | |
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478 | while (!TWI_TransferComplete(pTwi)) { |
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479 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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480 | TRACE_ERROR("TWID Timeout TC2\n\r"); |
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481 | break; |
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482 | } |
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483 | } |
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484 | } |
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485 | |
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486 | return 0; |
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487 | } |
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488 | |
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489 | /** |
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490 | * \brief Initializes a TWI driver instance, using the given TWI peripheral. |
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491 | * \note The peripheral must have been initialized properly before calling this |
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492 | * function. |
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493 | * \param pTwid Pointer to the Twid instance to initialize. |
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494 | * \param pTwi Pointer to the TWI peripheral to use. |
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495 | */ |
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496 | void TWID_DmaInitialize(TwihsDma *pTwidma, Twihs *pTwi, uint8_t bPolling) |
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497 | { |
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498 | TRACE_DEBUG("TWID_Initialize()\n\r"); |
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499 | assert(pTwidma != NULL); |
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500 | |
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501 | if ((unsigned int)pTwi == (unsigned int)TWIHS0) pTwidma->Twi_id = ID_TWIHS0; |
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502 | |
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503 | if ((unsigned int)pTwi == (unsigned int)TWIHS1) pTwidma->Twi_id = ID_TWIHS1; |
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504 | |
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505 | if ((unsigned int)pTwi == (unsigned int)TWIHS2) pTwidma->Twi_id = ID_TWIHS2; |
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506 | |
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507 | /* Initialize driver. */ |
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508 | pTwidma->pTwid->pTwi = pTwi; |
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509 | pTwidma->pTwid->pTransfer = 0; |
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510 | |
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511 | assert(!bPolling); |
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512 | } |
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513 | |
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514 | /** |
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515 | * \brief Asynchronously reads data from a slave on the TWI bus. An optional |
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516 | * callback function is triggered when the transfer is complete. |
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517 | * \param pTwid Pointer to a Twid instance. |
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518 | * \param address TWI slave address. |
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519 | * \param iaddress Optional slave internal address. |
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520 | * \param isize Internal address size in bytes. |
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521 | * \param pData Data buffer for storing received bytes. |
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522 | * \param num Number of bytes to read. |
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523 | * \param pAsync Asynchronous transfer descriptor. |
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524 | * \param TWI_ID TWI ID for TWI0, TWIHS1, TWIHS2. |
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525 | * \return 0 if the transfer has been started; otherwise returns a TWI error code. |
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526 | */ |
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527 | uint8_t TWID_DmaRead( |
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528 | TwihsDma *pTwiXdma, |
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529 | uint8_t address, |
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530 | uint32_t iaddress, |
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531 | uint8_t isize, |
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532 | uint8_t *pData, |
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533 | uint32_t num, |
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534 | Async *pAsync) |
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535 | { |
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536 | Twihs *pTwi; |
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537 | AsyncTwi *pTransfer; |
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538 | uint32_t status, startTime; |
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539 | |
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540 | assert(pTwiXdma->pTwid != NULL); |
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541 | pTwi = pTwiXdma->pTwid->pTwi; |
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542 | pTransfer = (AsyncTwi *) pTwiXdma->pTwid->pTransfer; |
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543 | |
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544 | assert((address & 0x80) == 0); |
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545 | assert((iaddress & 0xFF000000) == 0); |
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546 | assert(isize < 4); |
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547 | |
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548 | /* Check that no transfer is already pending*/ |
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549 | if (pTransfer) { |
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550 | |
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551 | TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); |
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552 | return TWID_ERROR_BUSY; |
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553 | } |
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554 | |
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555 | /* Asynchronous transfer*/ |
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556 | if (pAsync) { |
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557 | /* Update the transfer descriptor */ |
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558 | pTwiXdma->pTwid->pTransfer = pAsync; |
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559 | pTransfer = (AsyncTwi *) pAsync; |
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560 | pTransfer->status = ASYNC_STATUS_PENDING; |
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561 | pTransfer->pData = pData; |
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562 | pTransfer->num = num; |
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563 | pTransfer->transferred = 0; |
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564 | |
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565 | /* Enable read interrupt and start the transfer */ |
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566 | TWI_EnableIt(pTwi, TWIHS_IER_RXRDY); |
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567 | TWI_StartRead(pTwi, address, iaddress, isize); |
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568 | } else { |
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569 | /* Synchronous transfer*/ |
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570 | TWID_DmaInitializeRead(pTwiXdma); |
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571 | TWID_XdmaConfigureRead(pTwiXdma, pData, (num - 2)); |
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572 | |
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573 | /* Start read*/ |
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574 | XDMAD_StartTransfer(pTwiXdma->pTwiDma, dmaReadChannel); |
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575 | TWI_StartRead(pTwi, address, iaddress, isize); |
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576 | |
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577 | startTime = GetTicks(); |
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578 | status = XDMAD_IsTransferDone(pTwiXdma->pTwiDma, dmaReadChannel); |
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579 | |
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580 | while (status != XDMAD_OK) { |
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581 | status = XDMAD_IsTransferDone(pTwiXdma->pTwiDma, dmaReadChannel); |
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582 | |
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583 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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584 | TRACE_ERROR("TWID DMA not done\n\r"); |
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585 | break; |
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586 | } |
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587 | } |
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588 | |
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589 | if (XDMAD_OK == status) |
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590 | SCB_InvalidateDCache_by_Addr((uint32_t *)pData, (num - 2)); |
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591 | |
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592 | status = TWI_GetStatus(pTwi); |
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593 | startTime = GetTicks(); |
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594 | |
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595 | while (!(status & TWIHS_SR_RXRDY)) { |
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596 | status = TWI_GetStatus(pTwi); |
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597 | |
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598 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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599 | TRACE_ERROR("TWID DMA not done\n\r"); |
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600 | break; |
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601 | } |
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602 | } |
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603 | |
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604 | TWI_Stop(pTwi); |
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605 | |
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606 | pData[num - 2] = TWI_ReadByte(pTwi); |
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607 | status = TWI_GetStatus(pTwi); |
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608 | startTime = GetTicks(); |
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609 | |
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610 | while (!(status & TWIHS_SR_RXRDY)) { |
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611 | status = TWI_GetStatus(pTwi); |
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612 | |
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613 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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614 | TRACE_ERROR("TWID Timeout Read\n\r"); |
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615 | break; |
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616 | } |
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617 | } |
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618 | |
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619 | pData[num - 1] = TWI_ReadByte(pTwi); |
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620 | status = TWI_GetStatus(pTwi); |
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621 | startTime = GetTicks(); |
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622 | |
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623 | while (!(status & TWIHS_SR_TXCOMP)) { |
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624 | status = TWI_GetStatus(pTwi); |
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625 | |
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626 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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627 | TRACE_ERROR("TWID Timeout Read\n\r"); |
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628 | break; |
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629 | } |
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630 | } |
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631 | |
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632 | XDMAD_StopTransfer(pTwiXdma->pTwiDma, dmaReadChannel); |
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633 | XDMAD_FreeChannel(pTwiXdma->pTwiDma, dmaWriteChannel); |
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634 | } |
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635 | |
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636 | return 0; |
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637 | } |
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638 | |
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639 | /** |
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640 | * \brief Asynchronously sends data to a slave on the TWI bus. An optional |
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641 | * callback function is invoked whenever the transfer is complete. |
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642 | * \param pTwid Pointer to a Twid instance. |
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643 | * \param address TWI slave address. |
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644 | * \param iaddress Optional slave internal address. |
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645 | * \param isize Number of internal address bytes. |
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646 | * \param pData Data buffer for storing received bytes. |
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647 | * \param num Data buffer to send. |
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648 | * \param pAsync Asynchronous transfer descriptor. |
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649 | * \param TWI_ID TWIHS ID for TWIHS0, TWIHS1, TWIHS2. |
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650 | * \return 0 if the transfer has been started; otherwise returns a TWI error code. |
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651 | */ |
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652 | uint8_t TWID_DmaWrite( |
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653 | TwihsDma *pTwiXdma, |
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654 | uint8_t address, |
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655 | uint32_t iaddress, |
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656 | uint8_t isize, |
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657 | uint8_t *pData, |
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658 | uint32_t num, |
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659 | Async *pAsync) |
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660 | { |
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661 | Twihs *pTwi = pTwiXdma->pTwid->pTwi; |
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662 | AsyncTwi *pTransfer = (AsyncTwi *) pTwiXdma->pTwid->pTransfer; |
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663 | uint32_t status, startTime; |
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664 | //uint8_t singleTransfer = 0; |
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665 | assert(pTwi != NULL); |
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666 | assert((address & 0x80) == 0); |
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667 | assert((iaddress & 0xFF000000) == 0); |
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668 | assert(isize < 4); |
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669 | |
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670 | // if (num == 1) singleTransfer = 1; |
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671 | /* Check that no transfer is already pending */ |
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672 | if (pTransfer) { |
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673 | |
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674 | TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); |
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675 | return TWID_ERROR_BUSY; |
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676 | } |
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677 | |
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678 | /* Asynchronous transfer */ |
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679 | if (pAsync) { |
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680 | |
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681 | /* Update the transfer descriptor */ |
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682 | pTwiXdma->pTwid->pTransfer = pAsync; |
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683 | pTransfer = (AsyncTwi *) pAsync; |
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684 | pTransfer->status = ASYNC_STATUS_PENDING; |
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685 | pTransfer->pData = pData; |
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686 | pTransfer->num = num; |
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687 | pTransfer->transferred = 1; |
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688 | |
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689 | /* Enable write interrupt and start the transfer */ |
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690 | TWI_StartWrite(pTwi, address, iaddress, isize, *pData); |
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691 | TWI_EnableIt(pTwi, TWIHS_IER_TXRDY); |
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692 | } else { |
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693 | /* Synchronous transfer*/ |
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694 | TWID_DmaInitializeWrite(pTwiXdma); |
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695 | TWID_XdmaConfigureWrite(pTwiXdma, pData, (num - 1)); |
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696 | /* Set slave address and number of internal address bytes. */ |
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697 | pTwi->TWIHS_MMR = 0; |
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698 | pTwi->TWIHS_MMR = (isize << 8) | (address << 16); |
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699 | |
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700 | /* Set internal address bytes. */ |
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701 | pTwi->TWIHS_IADR = 0; |
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702 | pTwi->TWIHS_IADR = iaddress; |
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703 | |
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704 | // cache maintenance before starting DMA Xfr |
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705 | SCB_CleanDCache_by_Addr((uint32_t *)pData, (num - 1)); |
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706 | startTime = GetTicks(); |
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707 | |
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708 | XDMAD_StartTransfer(pTwiXdma->pTwiDma, dmaWriteChannel); |
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709 | |
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710 | while ((XDMAD_IsTransferDone(pTwiXdma->pTwiDma, dmaWriteChannel))) { |
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711 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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712 | TRACE_ERROR("TWID DMA not done, Channel State is %d\n\r", |
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713 | pTwiXdma->pTwiDma->XdmaChannels[dmaWriteChannel].state); |
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714 | break; |
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715 | } |
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716 | } |
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717 | |
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718 | status = TWI_GetStatus(pTwi); |
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719 | startTime = GetTicks(); |
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720 | |
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721 | while (!(status & TWIHS_SR_TXRDY)) { |
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722 | status = TWI_GetStatus(pTwi); |
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723 | |
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724 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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725 | TRACE_ERROR("TWID Timeout TXRDY\n\r"); |
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726 | break; |
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727 | } |
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728 | } |
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729 | |
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730 | /* Send a STOP condition */ |
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731 | TWI_Stop(pTwi); |
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732 | |
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733 | TWI_WriteByte(pTwi, pData[num - 1]); |
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734 | status = TWI_GetStatus(pTwi); |
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735 | startTime = GetTicks(); |
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736 | |
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737 | while (!(status & TWIHS_SR_TXCOMP)) { |
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738 | status = TWI_GetStatus(pTwi); |
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739 | |
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740 | if ((GetDelayInTicks(startTime, GetTicks())) > TWITIMEOUTMAX) { |
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741 | TRACE_ERROR("TWID Timeout Write\n\r"); |
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742 | break; |
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743 | } |
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744 | } |
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745 | |
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746 | XDMAD_StopTransfer(pTwiXdma->pTwiDma, dmaWriteChannel); |
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747 | XDMAD_FreeChannel(pTwiXdma->pTwiDma, dmaWriteChannel); |
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748 | |
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749 | } |
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750 | |
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751 | return 0; |
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752 | } |
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