source: rtems/bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c @ 54aabb7

5
Last change on this file since 54aabb7 was 54aabb7, checked in by Sebastian Huber <sebastian.huber@…>, on 04/22/18 at 13:11:43

bsp/atsam: Move libraries to bsps

This patch is a part of the BSP source reorganization.

Update #3285.
  • Property mode set to 100644
File size: 8.5 KB
Line 
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28/* ---------------------------------------------------------------------------- */
29
30/** \addtogroup sdram_module
31 * The SDRAMC driver provides the Interface to configure the SDRAM Controller
32 * (SDRAMC).
33 *  \section Usage
34 * <ul>
35 *  <li> Configure SDRAM using SDRAMC_Configure().</li>
36
37 * </ul>
38 * For more accurate information, please look at the SDRAMC section of the
39 * Datasheet.
40 * Related files :\n
41 * \ref sdramc.c\n
42 * \ref sdramc.h.\n
43*/
44
45/**
46*  \file
47*
48*  \section Purpose
49*
50*  Interface for configuring and using SDRAM Controller (SDRAMC).
51*
52*/
53
54/**
55 * \file
56 *
57 * Implementation of memories configuration on board.
58 *
59 */
60/*----------------------------------------------------------------------------
61 *        Headers
62 *----------------------------------------------------------------------------*/
63#include "chip.h"
64#include "sdramc.h"
65
66/*----------------------------------------------------------------------------
67 *        Local functions
68 *----------------------------------------------------------------------------*/
69/**
70 * \brief Calculate the sdram controller config register value.
71 * \param pMemory  Pointer to the sdram structure.
72 * \return Configure register value.
73 */
74static uint32_t SDRAMC_compute_CR_value(SSdramc_Memory *pMemory)
75{
76        uint32_t dw = 0;
77
78        dw |= pMemory->cfg.dwColumnBits;
79        dw |= pMemory->cfg.dwRowBits;
80        dw |= pMemory->cfg.dwBanks;  //NB, number of banks
81        dw |= pMemory->cfg.dwCAS;  //CAS, CAS latency
82        dw |= pMemory->cfg.dwDataBusWidth;  //DBW, data bus width
83        dw |= SDRAMC_CR_TWR(pMemory->cfg.dwWriteRecoveryDelay);
84        //TWR, Write Recovery Delay
85        dw |= SDRAMC_CR_TRC_TRFC(pMemory->cfg.dwRowCycleDelay_RowRefreshCycle);
86        //TRC_TRFC,Row Cycle Delay and Row Refresh Cycle
87        dw |= SDRAMC_CR_TRP(pMemory->cfg.dwRowPrechargeDelay);
88        //TRP, Row Precharge Delay
89        dw |= SDRAMC_CR_TRCD(pMemory->cfg.dwRowColumnDelay);
90        //TRCD, Row to Column Delay
91        dw |= SDRAMC_CR_TRAS(pMemory->cfg.dwActivePrechargeDelay);
92        //TRAS, Active to Precharge Delay
93        dw |= SDRAMC_CR_TXSR(pMemory->cfg.dwExitSelfRefreshActiveDelay);
94        //TXSR, Exit Self Refresh to Active Delay
95        return dw;
96}
97
98/*----------------------------------------------------------------------------
99 *        Exported functions
100 *----------------------------------------------------------------------------*/
101/**
102 * \brief Configure and initialize the SDRAM controller.
103 * \param pMemory  Pointer to the sdram structure.
104 * \param dwClockFrequency  SDRAM clock frequency.
105 */
106extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
107                                                          uint32_t dwClockFrequency)
108{
109        volatile uint32_t dw;
110
111        /* SDRAM hardware init */
112        /* Enable peripheral clock */
113        PMC_EnablePeripheral(ID_SMC);
114
115        /* SDRAM device configure */
116        /* Step 1. */
117        /* Program the features of SDRAM device into the Configuration Register.*/
118        SDRAMC->SDRAMC_CR = SDRAMC_compute_CR_value(pMemory);
119
120        /* Step 2. */
121        /* For low-power SDRAM, temperature-compensated self refresh (TCSR),
122           drive strength (DS) and partial array self refresh (PASR) must be set
123           in the Low-power Register.*/
124        SDRAMC->SDRAMC_LPR = 0;
125
126        /* Step 3. */
127        /* Program the memory device type into the Memory Device Register */
128        SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
129
130        /* Step 4 */
131        /* A minimum pause of 200 ŠÌs is provided to precede any signal toggle.
132           (6 core cycles per iteration) */
133        for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);
134
135        /* Step 5. */
136        /* A NOP command is issued to the SDR-SDRAM. Program NOP command into
137         Mode Register, the application must set Mode to 1 in the Mode Register.
138        Perform a write access to any SDR-SDRAM address to acknowledge this command.
139        Now the clock which drives SDR-SDRAM device is enabled.*/
140        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;
141        *(uint16_t *)(EBI_SDRAMC_ADDR) = 0;
142
143        /* Step 6. */
144        /* An all banks precharge command is issued to the SDR-SDRAM. Program all
145           banks precharge command into Mode Register, the application must set Mode to
146           2 in the Mode Register . Perform a write access to any SDRSDRAM address to
147           acknowledge this command. */
148        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
149        *(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0;
150
151        /* add some delays after precharge */
152        for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);
153
154        /* Step 7. */
155        /* Eight auto-refresh (CBR) cycles are provided. Program the auto refresh
156           command (CBR) into Mode Register, the application must set Mode to 4 in
157           the Mode Register. Once in the idle state, eight AUTO REFRESH cycles must
158           be performed. */
159        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
160        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x1;
161
162        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
163        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x2;
164
165        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
166        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x3;
167
168        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
169        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x4;
170
171        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
172        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x5;
173
174        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
175        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x6;
176
177        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
178        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x7;
179
180        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
181        *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x8;
182
183        /* Step 8. */
184        /* A Mode Register set (MRS) cycle is issued to program the parameters of
185           the SDRAM devices, in particular CAS latency and burst length. */
186        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
187        *(uint16_t *)(EBI_SDRAMC_ADDR + 0x22) = 0xcafe;
188
189        /* Step 9. */
190        /* For low-power SDR-SDRAM initialization, an Extended Mode Register set
191           (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS).
192           The write address must be chosen so that BA[1] is set to 1 and BA[0] is set
193           to 0 */
194        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
195        *((uint16_t *)(EBI_SDRAMC_ADDR + (1 << pMemory->cfg.dwBK1))) = 0;
196
197        /* Step 10. */
198        /* The application must go into Normal Mode, setting Mode to 0 in the Mode
199           Register and perform a write access at any location in the SDRAM to
200           acknowledge this command. */
201        SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
202        *(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0;
203
204        /* Step 11. */
205        /* Write the refresh rate into the count field in the SDRAMC Refresh
206           Timer register. Set Refresh timer 15.625 us*/
207        dw = dwClockFrequency / 1000u;
208        dw *= 15625u;
209        dw /= 1000000u;
210        SDRAMC->SDRAMC_TR = SDRAMC_TR_COUNT(dw);
211}
212
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