1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | /** \addtogroup qspi_module Working with QSPI |
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31 | * \ingroup peripherals_module |
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32 | * The QSPI driver provides the interface to configure and use the QSPI |
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33 | * peripheral. |
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34 | * |
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35 | * The Serial Peripheral Interface (QSPI) circuit is a synchronous serial |
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36 | * data link that provides communication with external devices in Master |
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37 | * or Slave Mode. |
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38 | * |
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39 | * To use the QSPI, the user has to follow these few steps: |
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40 | * -# Enable the QSPI pins required by the application (see pio.h). |
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41 | * -# Configure the QSPI using the \ref QSPI_Configure(). This enables the |
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42 | * peripheral clock. The mode register is loaded with the given value. |
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43 | * -# Configure all the necessary chip selects with \ref QSPI_ConfigureNPCS(). |
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44 | * -# Enable the QSPI by calling \ref QSPI_Enable(). |
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45 | * -# Send/receive data using \ref QSPI_Write() and \ref QSPI_Read(). Note that |
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46 | * \ref QSPI_Read() |
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47 | * must be called after \ref QSPI_Write() to retrieve the last value read. |
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48 | * -# Send/receive data using the PDC with the \ref QSPI_WriteBuffer() and |
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49 | * \ref QSPI_ReadBuffer() functions. |
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50 | * -# Disable the QSPI by calling \ref QSPI_Disable(). |
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51 | * |
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52 | * For more accurate information, please look at the QSPI section of the |
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53 | * Datasheet. |
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54 | * |
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55 | * Related files :\n |
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56 | * \ref qspi.c\n |
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57 | * \ref qspi.h.\n |
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58 | */ |
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59 | /*@{*/ |
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60 | /*@}*/ |
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61 | |
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62 | /** |
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63 | * \file |
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64 | * |
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65 | * Implementation of Serial Peripheral Interface (QSPI) controller. |
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66 | * |
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67 | */ |
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68 | |
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69 | /*---------------------------------------------------------------------------- |
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70 | * Headers |
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71 | *----------------------------------------------------------------------------*/ |
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72 | |
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73 | #include "chip.h" |
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74 | #include "stdlib.h" |
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75 | #include "string.h" |
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76 | |
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77 | #include <stdint.h> |
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78 | #include <bsp/iocopy.h> |
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79 | |
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80 | |
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81 | #define SCRAMBLE_KEY 0x0BADDEAD |
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82 | /*---------------------------------------------------------------------------- |
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83 | * Internal functions |
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84 | *----------------------------------------------------------------------------*/ |
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85 | |
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86 | |
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87 | |
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88 | /** |
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89 | * \brief Configure QSPI/SPI mode |
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90 | * |
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91 | * \param pQspi Pointer to a Qspi instance. |
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92 | */ |
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93 | __STATIC_INLINE void QSPI_ConfigureMode(Qspi *pQspi, uint8_t dMode) |
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94 | { |
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95 | assert(pQspi); |
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96 | pQspi->QSPI_MR = dMode; |
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97 | } |
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98 | |
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99 | /** |
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100 | * \brief Configure mode register of QSPI |
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101 | * |
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102 | * \param pQspi Pointer to a Qspi instance. |
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103 | */ |
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104 | __STATIC_INLINE void QSPI_Configure(Qspi *pQspi, uint32_t dwConfiguration) |
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105 | { |
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106 | assert(pQspi); |
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107 | pQspi->QSPI_MR |= dwConfiguration; |
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108 | } |
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109 | |
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110 | |
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111 | /** |
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112 | * \brief Configures a instruction address for QSPI in QSPI mode |
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113 | * |
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114 | * \param pQspi Pointer to a Qspi instance. |
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115 | * \param dwAddr Instruction Address |
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116 | */ |
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117 | __STATIC_INLINE void QSPI_SetInstAddr(Qspi *pQspi, uint32_t dwAddr) |
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118 | { |
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119 | assert(pQspi); |
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120 | pQspi->QSPI_IAR = dwAddr; |
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121 | } |
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122 | |
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123 | |
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124 | /** |
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125 | * \brief Configures instruction register with a given command for QSPI |
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126 | * |
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127 | * \param pQspi Pointer to a Qspi instance. |
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128 | * \param dwInst Instruction Code |
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129 | * \param dwOpt Instruction Code option |
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130 | */ |
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131 | __STATIC_INLINE void QSPI_SetInst(Qspi *pQspi, uint8_t dwInst, uint8_t dwOpt) |
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132 | { |
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133 | assert(pQspi); |
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134 | pQspi->QSPI_ICR = (dwInst | QSPI_ICR_OPT(dwOpt)); |
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135 | } |
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136 | |
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137 | /** |
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138 | * \brief Configures instruction frame register of QSPI |
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139 | * |
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140 | * \param pQspi Pointer to a Qspi instance. |
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141 | * \param pInstFrame Instruction Frame configuration |
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142 | */ |
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143 | __STATIC_INLINE void QSPI_SetInstFrame(Qspi *pQspi, |
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144 | QspiInstFrame_t *pInstFrame) |
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145 | { |
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146 | assert(pQspi); |
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147 | pQspi->QSPI_IFR = pInstFrame->InstFrame.val; |
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148 | } |
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149 | |
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150 | /** |
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151 | * \brief Reads the Instruction frame of QSPI |
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152 | * |
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153 | * \param pQspi Pointer to an Qspi instance. |
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154 | */ |
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155 | __STATIC_INLINE uint32_t QSPI_GetInstFrame(Qspi *pQspi) |
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156 | { |
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157 | assert(pQspi); |
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158 | return pQspi->QSPI_IFR; |
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159 | } |
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160 | |
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161 | /** |
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162 | * \brief Read QSPI RDR register for SPI mode |
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163 | * |
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164 | * \param pQspi Pointer to an Qspi instance. |
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165 | */ |
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166 | __STATIC_INLINE uint16_t QSPI_ReadSPI(Qspi *pQspi) |
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167 | { |
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168 | assert(pQspi); |
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169 | |
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170 | while (!QSPI_GetStatus(pQspi, IsReceived)); |
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171 | |
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172 | return pQspi->QSPI_RDR; |
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173 | } |
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174 | |
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175 | |
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176 | /** |
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177 | * \brief Write to QSPI Tx register in SPI mode |
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178 | * |
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179 | * \param pQspi Pointer to an Qspi instance. |
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180 | * \param wData Data to transmit |
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181 | */ |
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182 | __STATIC_INLINE void QSPI_WriteSPI(Qspi *pQspi, uint16_t wData) |
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183 | { |
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184 | assert(pQspi); |
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185 | |
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186 | /* Send data */ |
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187 | while (!QSPI_GetStatus(pQspi, IsTxEmpty)); |
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188 | |
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189 | pQspi->QSPI_TDR = wData; |
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190 | |
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191 | while (!QSPI_GetStatus(pQspi, IsTxSent)); |
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192 | } |
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193 | |
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194 | /** |
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195 | * \brief Configures QSPI scrambling with a given Key |
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196 | * |
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197 | * \param pQspi Pointer to an Qspi instance. |
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198 | * \param wKey Key for scramble/unscramble |
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199 | * \param EnableFlag Enable/disable scramble |
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200 | * \param Random Add random value with given key |
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201 | */ |
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202 | __STATIC_INLINE void QSPI_ScrambleData(Qspi *pQspi, uint32_t wKey, |
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203 | uint8_t EnableFlag, uint8_t Random) |
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204 | { |
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205 | assert(pQspi); |
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206 | assert(EnableFlag < 2); |
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207 | assert(Random < 2); |
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208 | |
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209 | if (EnableFlag) |
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210 | pQspi->QSPI_SKR = wKey; |
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211 | |
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212 | pQspi->QSPI_SMR = (EnableFlag | (Random << 1)); |
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213 | } |
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214 | |
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215 | /*---------------------------------------------------------------------------- |
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216 | * Exported functions |
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217 | *----------------------------------------------------------------------------*/ |
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218 | |
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219 | /** |
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220 | * \brief Enables a QSPI peripheral. |
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221 | * |
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222 | * \param pQspi Pointer to a Qspi instance. |
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223 | */ |
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224 | void QSPI_Enable(Qspi *pQspi) |
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225 | { |
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226 | assert(pQspi); |
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227 | pQspi->QSPI_CR = QSPI_CR_QSPIEN; |
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228 | |
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229 | while (!(pQspi->QSPI_SR & QSPI_SR_QSPIENS)); |
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230 | } |
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231 | |
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232 | /** |
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233 | * \brief Disables a QSPI peripheral. |
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234 | * |
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235 | * \param pQspi Pointer to a Qspi instance. |
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236 | */ |
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237 | void QSPI_Disable(Qspi *pQspi) |
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238 | { |
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239 | assert(pQspi); |
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240 | pQspi->QSPI_CR = QSPI_CR_QSPIDIS; |
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241 | |
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242 | while (pQspi->QSPI_SR & QSPI_SR_QSPIENS); |
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243 | } |
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244 | |
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245 | /** |
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246 | * \brief Resets a QSPI peripheral. |
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247 | * |
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248 | * \param pQspi Pointer to a Qspi instance. |
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249 | */ |
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250 | void QSPI_SwReset(Qspi *pQspi) |
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251 | { |
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252 | assert(pQspi); |
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253 | pQspi->QSPI_CR = QSPI_CR_SWRST; |
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254 | } |
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255 | |
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256 | /** |
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257 | * \brief Enables one or more interrupt sources of a QSPI peripheral. |
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258 | * |
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259 | * \param pQspi Pointer to a Qspi instance. |
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260 | * \param sources Bitwise OR of selected interrupt sources. |
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261 | */ |
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262 | QspidStatus_t QSPI_EnableIt(Qspi *pQspi, uint32_t dwSources) |
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263 | { |
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264 | assert(pQspi); |
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265 | pQspi->QSPI_IER = dwSources; |
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266 | return QSPI_SUCCESS; |
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267 | } |
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268 | |
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269 | /** |
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270 | * \brief Disables one or more interrupt sources of a QSPI peripheral. |
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271 | * |
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272 | * \param pQspi Pointer to a Qspi instance. |
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273 | * \param sources Bitwise OR of selected interrupt sources. |
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274 | */ |
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275 | QspidStatus_t QSPI_DisableIt(Qspi *pQspi, uint32_t dwSources) |
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276 | { |
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277 | assert(pQspi); |
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278 | pQspi->QSPI_IDR = dwSources; |
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279 | return QSPI_SUCCESS; |
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280 | } |
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281 | |
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282 | /** |
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283 | * \brief Return the interrupt mask register. |
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284 | * |
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285 | * \return Qspi interrupt mask register. |
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286 | */ |
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287 | uint32_t QSPI_GetItMask(Qspi *pQspi) |
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288 | { |
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289 | assert(pQspi); |
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290 | return (pQspi->QSPI_IMR); |
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291 | } |
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292 | |
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293 | /** |
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294 | * \brief Returns enabled interrupt status |
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295 | * |
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296 | * \return Qspi interrupt mask register. |
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297 | */ |
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298 | uint32_t QSPI_GetEnabledItStatus(Qspi *pQspi) |
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299 | { |
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300 | assert(pQspi); |
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301 | return (pQspi->QSPI_IMR & QSPI_GetStatus(pQspi, (QspiStatus_t)0xFFFFFFFF)); |
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302 | } |
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303 | |
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304 | /** |
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305 | * \brief Get the current status register of the given QSPI peripheral. |
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306 | * \note This resets the internal value of the status register, so further |
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307 | * read may yield different values. |
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308 | * \param pQspi Pointer to a Qspi instance. |
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309 | * \param rStatus Compare status with given status bit |
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310 | * \return QSPI status register. |
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311 | */ |
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312 | uint32_t QSPI_GetStatus(Qspi *pQspi, const QspiStatus_t rStatus) |
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313 | { |
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314 | assert(pQspi); |
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315 | return (pQspi->QSPI_SR & rStatus); |
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316 | } |
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317 | |
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318 | /** |
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319 | * \brief Configures peripheral clock of a QSPI/SPI peripheral. |
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320 | * |
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321 | * \param pQspi Pointer to an Qspi instance. |
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322 | * \param dwConfiguration Desired clock configuration. |
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323 | */ |
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324 | void QSPI_ConfigureClock(Qspi *pQspi, QspiClockMode_t ClockMode, |
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325 | uint32_t dwClockCfg) |
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326 | { |
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327 | assert(pQspi); |
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328 | pQspi->QSPI_SCR = ClockMode; |
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329 | pQspi->QSPI_SCR |= dwClockCfg; |
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330 | } |
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331 | |
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332 | /** |
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333 | * \brief Configures QSPI/SPI |
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334 | * |
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335 | * \param pQspi Pointer to an Qspi instance. |
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336 | * \param Mode Mode for QSPI or SPI |
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337 | * \param dwConfiguration Config of SPI or QSPI mode |
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338 | */ |
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339 | QspidStatus_t QSPI_ConfigureInterface(Qspid_t *pQspid, QspiMode_t Mode, |
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340 | uint32_t dwConfiguration) |
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341 | { |
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342 | pQspid->pQspiHw = QSPI; |
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343 | pQspid->qspiId = ID_QSPI; |
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344 | |
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345 | QSPI_Disable(pQspid->pQspiHw); |
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346 | QSPI_SwReset(pQspid->pQspiHw); |
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347 | |
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348 | QSPI_ConfigureMode(pQspid->pQspiHw, Mode); |
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349 | QSPI_Configure(pQspid->pQspiHw, dwConfiguration); |
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350 | |
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351 | return QSPI_SUCCESS; |
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352 | } |
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353 | |
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354 | |
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355 | /** |
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356 | * \brief Ends ongoing transfer by releasing CS of QSPI peripheral. |
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357 | * |
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358 | * \param pQspi Pointer to an Qspi instance. |
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359 | */ |
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360 | QspidStatus_t QSPI_EndTransfer(Qspi *pQspi) |
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361 | { |
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362 | assert(pQspi); |
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363 | |
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364 | while (!QSPI_GetStatus(pQspi, IsTxEmpty)); |
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365 | |
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366 | pQspi->QSPI_CR = QSPI_CR_LASTXFER; |
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367 | |
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368 | return QSPI_SUCCESS; |
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369 | } |
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370 | |
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371 | |
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372 | /*---------------------------------------------------------------------------- |
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373 | * SPI functions |
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374 | *----------------------------------------------------------------------------*/ |
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375 | /** |
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376 | * \brief Reads the data received by a SPI peripheral. This |
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377 | * method must be called after a successful SPI_Write call. |
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378 | * |
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379 | * \param pQspid Pointer to a Qspi instance. |
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380 | * \param pData Buffer to put read value |
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381 | * \return Qspi status |
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382 | */ |
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383 | QspidStatus_t QSPI_SingleReadSPI(Qspid_t *pQspid, uint16_t *const pData) |
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384 | { |
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385 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
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386 | Qspi *pQspi = pQspid->pQspiHw; |
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387 | uint32_t NumOfAttempt = 0; |
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388 | uint16_t Dummy = 0xFF; |
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389 | |
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390 | for (;;) { |
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391 | if (QSPI_GetStatus(pQspi, IsReceived)) { |
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392 | *pData = QSPI_ReadSPI(pQspi); |
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393 | QSPI_WriteSPI(pQspi, Dummy); |
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394 | *pData = QSPI_ReadSPI(pQspi); |
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395 | NumOfAttempt = 0; |
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396 | Status = QSPI_SUCCESS; |
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397 | } else { |
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398 | if (NumOfAttempt > 0xFFFF) { |
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399 | Status = QSPI_READ_ERROR; |
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400 | TRACE_ERROR(" SPI Read Error \n\r"); |
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401 | break; |
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402 | } else { |
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403 | Status = QSPI_READ_ERROR; |
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404 | NumOfAttempt++; |
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405 | } |
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406 | } |
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407 | } |
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408 | |
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409 | return Status; |
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410 | } |
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411 | |
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412 | /** |
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413 | * \brief Reads multiple data received by a SPI peripheral. This |
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414 | * method must be called after a successful SPI_Write call. |
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415 | * |
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416 | * \param pQspid Pointer to a Qspi instance. |
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417 | * \param pData Pointer to read buffer |
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418 | * \param NumOfBytes Num of bytes to read |
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419 | * |
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420 | * \return Qspi status |
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421 | */ |
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422 | QspidStatus_t QSPI_MultiReadSPI(Qspid_t *pQspid, uint16_t *const pData, |
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423 | uint32_t NumOfBytes) |
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424 | { |
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425 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
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426 | Qspi *pQspi = pQspid->pQspiHw; |
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427 | uint32_t NumOfBytesRead = 0; |
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428 | uint32_t NumOfAttempt = 0; |
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429 | uint8_t *pwData = (uint8_t *)pData; |
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430 | uint16_t Dummy = 0xFF; |
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431 | |
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432 | /* Dummy read and write to discard first bytes recvd and start |
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433 | receiving new data*/ |
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434 | Dummy = QSPI_ReadSPI(pQspi); |
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435 | QSPI_WriteSPI(pQspi, Dummy); |
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436 | |
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437 | for (; NumOfBytesRead < NumOfBytes;) { |
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438 | if (QSPI_GetStatus(pQspi, IsTxSent)) { |
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439 | *pwData = QSPI_ReadSPI(pQspi); |
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440 | |
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441 | if (pQspi->QSPI_MR & QSPI_MR_NBBITS_Msk) |
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442 | pwData += sizeof(uint16_t); |
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443 | else |
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444 | pwData += sizeof(uint8_t); |
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445 | |
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446 | NumOfBytesRead++; |
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447 | NumOfAttempt = 0; |
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448 | Status = QSPI_SUCCESS; |
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449 | QSPI_WriteSPI(pQspi, Dummy); |
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450 | } else { |
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451 | if (NumOfAttempt > 0xFFFF) { |
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452 | Status = QSPI_READ_ERROR; |
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453 | TRACE_ERROR(" SPI MultiRead Error \n\r"); |
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454 | break; |
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455 | } else { |
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456 | Status = QSPI_READ_ERROR; |
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457 | NumOfAttempt++; |
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458 | } |
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459 | } |
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460 | } |
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461 | |
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462 | return Status; |
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463 | } |
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464 | |
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465 | /** |
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466 | * \brief Sends a single data through a SPI peripheral. |
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467 | * |
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468 | * \param pQspid Pointer to a Qspi instance. |
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469 | * \param pData Pointer to Tx data |
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470 | * |
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471 | * \return Qspi status |
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472 | */ |
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473 | QspidStatus_t QSPI_SingleWriteSPI(Qspid_t *pQspid, uint16_t const *pData) |
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474 | { |
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475 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
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476 | Qspi *pQspi = pQspid->pQspiHw; |
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477 | uint32_t NumOfAttempt = 0; |
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478 | |
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479 | for (;;) { |
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480 | if (QSPI_GetStatus(pQspi, IsTxSent)) { |
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481 | QSPI_WriteSPI(pQspi, *pData); |
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482 | NumOfAttempt = 0; |
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483 | Status = QSPI_SUCCESS; |
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484 | break; |
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485 | } else { |
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486 | Status = QSPI_BUSY_SENDING; |
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487 | NumOfAttempt++; |
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488 | |
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489 | if (NumOfAttempt > 0xFFFF) { |
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490 | Status = QSPI_WRITE_ERROR; |
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491 | TRACE_ERROR(" SPI Write Error \n\r"); |
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492 | break; |
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493 | } |
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494 | } |
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495 | } |
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496 | |
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497 | return Status; |
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498 | |
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499 | } |
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500 | |
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501 | /** |
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502 | * \brief Sends multiple data through a SPI peripheral. |
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503 | * |
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504 | * \param pQspid Pointer to a Qspi instance. |
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505 | * \param pData Pointer to a Tx buffer |
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506 | * \param NumOfBytes Num of data to send. |
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507 | */ |
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508 | QspidStatus_t QSPI_MultiWriteSPI(Qspid_t *pQspid, uint16_t const *pData, |
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509 | uint32_t NumOfBytes) |
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510 | { |
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511 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
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512 | Qspi *pQspi = pQspid->pQspiHw; |
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513 | uint32_t NumOfBytesWrite = 0; |
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514 | uint32_t NumOfAttempt = 0; |
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515 | uint8_t *pwData = (uint8_t *)pData; |
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516 | uint8_t Addr_Inc = 0; |
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517 | |
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518 | if (pQspi->QSPI_MR & QSPI_MR_NBBITS_Msk) |
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519 | Addr_Inc = sizeof(uint16_t); |
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520 | else |
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521 | Addr_Inc = sizeof(uint8_t); |
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522 | |
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523 | for (; NumOfBytesWrite < NumOfBytes;) { |
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524 | if (QSPI_GetStatus(pQspi, IsTxEmpty)) { |
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525 | QSPI_WriteSPI(pQspi, (uint16_t)*pwData); |
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526 | pwData += Addr_Inc; |
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527 | NumOfBytesWrite++; |
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528 | NumOfAttempt = 0; |
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529 | Status = QSPI_SUCCESS; |
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530 | } else { |
---|
531 | Status = QSPI_BUSY_SENDING; |
---|
532 | NumOfAttempt++; |
---|
533 | |
---|
534 | if (NumOfAttempt > 0xFFFF) { |
---|
535 | Status = QSPI_WRITE_ERROR; |
---|
536 | TRACE_ERROR(" SPI Multi Write Error \n\r"); |
---|
537 | break; |
---|
538 | } |
---|
539 | } |
---|
540 | } |
---|
541 | |
---|
542 | return Status; |
---|
543 | |
---|
544 | } |
---|
545 | |
---|
546 | /*---------------------------------------------------------------------------- |
---|
547 | * QSPI functions |
---|
548 | *----------------------------------------------------------------------------*/ |
---|
549 | |
---|
550 | /** |
---|
551 | * \brief Send an instruction over QSPI (oly a flash command no data) |
---|
552 | * |
---|
553 | * \param pQspi Pointer to an Qspi instance. |
---|
554 | * \param KeepCfg To keep Instruction fram value or restes to zero |
---|
555 | * |
---|
556 | * \return Returns 1 if At least one instruction end has been detected since |
---|
557 | * the last read of QSPI_SR.; otherwise |
---|
558 | * returns 0. |
---|
559 | */ |
---|
560 | QspidStatus_t QSPI_SendCommand(Qspid_t *pQspid, uint8_t const KeepCfg) |
---|
561 | { |
---|
562 | QspiInstFrame_t *const pFrame = pQspid->pQspiFrame; |
---|
563 | QspiMemCmd_t pCommand = pQspid->qspiCommand; |
---|
564 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
---|
565 | uint32_t timeout = 15000; |
---|
566 | |
---|
567 | if (pFrame->InstFrame.bm.bAddrEn) |
---|
568 | QSPI_SetInstAddr(pQspid->pQspiHw, pFrame->Addr); |
---|
569 | |
---|
570 | QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), |
---|
571 | ((pCommand.Option >> QSPI_ICR_OPT_Pos) & 0xFF)); |
---|
572 | QSPI_SetInstFrame(pQspid->pQspiHw, pFrame); |
---|
573 | |
---|
574 | memory_sync(); |
---|
575 | |
---|
576 | /* |
---|
577 | * FIXME: Timeout has been introduced due to a problem that was detected |
---|
578 | * when QSPI_SR_INSTRE was not detected and the function is stuck in an |
---|
579 | * endless loop. This is still an open issue. |
---|
580 | * peripheral clock: 50Mhz -> 20 ns period time. |
---|
581 | * timeout: set to 15000 loop cycles => 300000 ns. |
---|
582 | * with loop instructions, the delay increases to 1ms altogether. |
---|
583 | */ |
---|
584 | while (!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE) && timeout > 0) { |
---|
585 | --timeout; |
---|
586 | } |
---|
587 | |
---|
588 | if (timeout == 0) { |
---|
589 | Status = QSPI_WRITE_ERROR; |
---|
590 | } |
---|
591 | |
---|
592 | // poll CR reg to know status if instruction has end |
---|
593 | if (!KeepCfg) |
---|
594 | pFrame->InstFrame.val = 0; |
---|
595 | |
---|
596 | return Status; |
---|
597 | } |
---|
598 | |
---|
599 | |
---|
600 | |
---|
601 | /** |
---|
602 | * \brief Send instruction over QSPI with data |
---|
603 | * |
---|
604 | * \param pQspi Pointer to an Qspi instance. |
---|
605 | * \param KeepCfg To keep Instruction fram value or restes to zero |
---|
606 | * |
---|
607 | * \return Returns 1 if At least one instruction end has been detected |
---|
608 | * since the last read of QSPI_SR.; otherwise returns 0. |
---|
609 | */ |
---|
610 | QspidStatus_t QSPI_SendCommandWithData(Qspid_t *pQspid, uint8_t const KeepCfg) |
---|
611 | { |
---|
612 | QspiInstFrame_t *const pFrame = pQspid->pQspiFrame; |
---|
613 | QspiMemCmd_t pCommand = pQspid->qspiCommand; |
---|
614 | QspiBuffer_t pBuffer = pQspid->qspiBuffer; |
---|
615 | uint32_t *pQspiBuffer = (uint32_t *)QSPIMEM_ADDR; |
---|
616 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
---|
617 | |
---|
618 | //assert(pBuffer.pDataRx); |
---|
619 | assert(pBuffer.pDataTx); |
---|
620 | |
---|
621 | QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), |
---|
622 | (pCommand.Option & 0xFF)); |
---|
623 | QSPI_SetInstFrame(pQspid->pQspiHw, pFrame); |
---|
624 | |
---|
625 | QSPI_GetInstFrame(pQspid->pQspiHw); |
---|
626 | |
---|
627 | // to synchronize system bus accesses |
---|
628 | if (!KeepCfg) |
---|
629 | pFrame->InstFrame.val = 0; |
---|
630 | |
---|
631 | memcpy(pQspiBuffer , pBuffer.pDataTx , pBuffer.TxDataSize); |
---|
632 | memory_sync(); |
---|
633 | QSPI_EndTransfer(pQspid->pQspiHw); |
---|
634 | |
---|
635 | // End transmission after all data has been sent |
---|
636 | while (!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); |
---|
637 | |
---|
638 | // poll CR reg to know status if instruction has end |
---|
639 | |
---|
640 | return Status; |
---|
641 | } |
---|
642 | |
---|
643 | /** |
---|
644 | * \brief Send instruction over QSPI to read data |
---|
645 | * |
---|
646 | * \param pQspi Pointer to an Qspi instance. |
---|
647 | * \param KeepCfg To keep Instruction from value or resets to zero |
---|
648 | * |
---|
649 | * \return Returns 1 if At least one instruction end has been detected |
---|
650 | * since the last read of QSPI_SR.; otherwise returns 0. |
---|
651 | */ |
---|
652 | QspidStatus_t QSPI_ReadCommand(Qspid_t *pQspid, uint8_t const KeepCfg) |
---|
653 | { |
---|
654 | QspiInstFrame_t *const pFrame = pQspid->pQspiFrame; |
---|
655 | QspiMemCmd_t pCommand = pQspid->qspiCommand; |
---|
656 | QspiBuffer_t pBuffer = pQspid->qspiBuffer; |
---|
657 | uint32_t *pQspiBuffer = (uint32_t *)QSPIMEM_ADDR; |
---|
658 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
---|
659 | |
---|
660 | assert(pBuffer.pDataRx); |
---|
661 | |
---|
662 | QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), |
---|
663 | (pCommand.Option & 0xFF)); |
---|
664 | QSPI_SetInstFrame(pQspid->pQspiHw, pFrame); |
---|
665 | |
---|
666 | QSPI_GetInstFrame(pQspid->pQspiHw); |
---|
667 | |
---|
668 | // to synchronize system bus accesses |
---|
669 | if (!KeepCfg) |
---|
670 | pFrame->InstFrame.val = 0; |
---|
671 | |
---|
672 | memcpy(pBuffer.pDataRx , pQspiBuffer, pBuffer.RxDataSize); |
---|
673 | memory_sync(); |
---|
674 | QSPI_EndTransfer(pQspid->pQspiHw); |
---|
675 | |
---|
676 | // End transmission after all data has been sent |
---|
677 | while (!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); |
---|
678 | |
---|
679 | // poll CR reg to know status if instruction has end |
---|
680 | |
---|
681 | return Status; |
---|
682 | } |
---|
683 | |
---|
684 | /** |
---|
685 | * \brief Sends an instruction over QSPI and configures other related address |
---|
686 | * like Addr , Frame and synchronise bus access before data read or write |
---|
687 | * |
---|
688 | * \param pQspi Pointer to an Qspi instance. |
---|
689 | * \param KeepCfg To keep Instruction from value or resets to zero |
---|
690 | * \param ScrambleFlag Enable or disable scramble on QSPI |
---|
691 | * |
---|
692 | * \return Returns 1 if At least one instruction end has been detected since |
---|
693 | * the last read of QSPI_SR.; otherwise returns 0. |
---|
694 | */ |
---|
695 | QspidStatus_t QSPI_EnableMemAccess(Qspid_t *pQspid, uint8_t const KeepCfg, |
---|
696 | uint8_t ScrambleFlag) |
---|
697 | { |
---|
698 | QspiInstFrame_t *const pFrame = pQspid->pQspiFrame; |
---|
699 | QspiMemCmd_t pCommand = pQspid->qspiCommand; |
---|
700 | |
---|
701 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
---|
702 | |
---|
703 | QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), |
---|
704 | (pCommand.Option & 0xFF)); |
---|
705 | |
---|
706 | if (ScrambleFlag) |
---|
707 | QSPI_ScrambleData(pQspid->pQspiHw, SCRAMBLE_KEY, ScrambleFlag, 1); |
---|
708 | |
---|
709 | QSPI_SetInstFrame(pQspid->pQspiHw, pFrame); |
---|
710 | |
---|
711 | QSPI_GetInstFrame(pQspid->pQspiHw); |
---|
712 | |
---|
713 | // to synchronize system bus accesses |
---|
714 | if (!KeepCfg) |
---|
715 | pFrame->InstFrame.val = 0; |
---|
716 | |
---|
717 | Status = QSPI_SUCCESS; |
---|
718 | return Status; |
---|
719 | } |
---|
720 | |
---|
721 | /** |
---|
722 | * \brief Writes or reads the QSPI memory (0x80000000) to transmit or |
---|
723 | * receive data from Flash memory |
---|
724 | * \param pQspi Pointer to an Qspi instance. |
---|
725 | * \param ReadWrite Flag to indicate read/write QSPI memory access |
---|
726 | * |
---|
727 | * \return Returns 1 if At least one instruction end has been detected since |
---|
728 | * the last read of QSPI_SR.; otherwise returns 0. |
---|
729 | */ |
---|
730 | QspidStatus_t QSPI_ReadWriteMem(Qspid_t *pQspid, Access_t const ReadWrite) |
---|
731 | { |
---|
732 | QspidStatus_t Status = QSPI_UNKNOWN_ERROR; |
---|
733 | QspiInstFrame_t *const pFrame = pQspid->pQspiFrame; |
---|
734 | void *pQspiMem = (void *)(QSPIMEM_ADDR | pFrame->Addr); |
---|
735 | QspiBuffer_t pBuffer = pQspid->qspiBuffer; |
---|
736 | |
---|
737 | assert(((ReadWrite > CmdAccess) |
---|
738 | && (ReadWrite <= WriteAccess)) ? true : false); |
---|
739 | |
---|
740 | if (ReadWrite == WriteAccess) { |
---|
741 | atsam_copy_to_io(pQspiMem, pBuffer.pDataTx , |
---|
742 | pBuffer.TxDataSize); |
---|
743 | } else { |
---|
744 | atsam_copy_from_io(pBuffer.pDataRx, pQspiMem, |
---|
745 | pBuffer.RxDataSize); |
---|
746 | } |
---|
747 | memory_sync(); |
---|
748 | QSPI_EndTransfer(pQspid->pQspiHw); |
---|
749 | |
---|
750 | // End transmission after all data has been sent |
---|
751 | while (!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); |
---|
752 | |
---|
753 | // poll CR reg to know status if instruction has end |
---|
754 | |
---|
755 | Status = QSPI_SUCCESS; |
---|
756 | return Status; |
---|
757 | } |
---|