1 | /* ---------------------------------------------------------------------------- */ |
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2 | /* Atmel Microcontroller Software Support */ |
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3 | /* SAM Software Package License */ |
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4 | /* ---------------------------------------------------------------------------- */ |
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5 | /* Copyright (c) 2015, Atmel Corporation */ |
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6 | /* */ |
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7 | /* All rights reserved. */ |
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8 | /* */ |
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9 | /* Redistribution and use in source and binary forms, with or without */ |
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10 | /* modification, are permitted provided that the following condition is met: */ |
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11 | /* */ |
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12 | /* - Redistributions of source code must retain the above copyright notice, */ |
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13 | /* this list of conditions and the disclaimer below. */ |
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14 | /* */ |
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15 | /* Atmel's name may not be used to endorse or promote products derived from */ |
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16 | /* this software without specific prior written permission. */ |
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17 | /* */ |
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18 | /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ |
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19 | /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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20 | /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ |
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21 | /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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22 | /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ |
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23 | /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ |
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24 | /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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25 | /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ |
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26 | /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ |
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27 | /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ |
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28 | /* ---------------------------------------------------------------------------- */ |
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29 | |
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30 | /** |
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31 | * \file |
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32 | * |
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33 | * Interface for the S25fl1 Serial Flash driver. |
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34 | * |
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35 | */ |
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36 | |
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37 | #ifndef S25FL1_H |
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38 | #define S25FL1_H |
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39 | #define USE_QSPI_DMA |
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40 | /*---------------------------------------------------------------------------- |
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41 | * Macros |
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42 | *----------------------------------------------------------------------------*/ |
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43 | |
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44 | #define Size(pAt25) ((pAt25)->pDesc->size) |
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45 | #define PageSize(pAt25) ((pAt25)->pDesc->pageSize) |
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46 | #define BlockSize(pAt25) ((pAt25)->pDesc->blockSize) |
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47 | #define Name(pAt25) ((pAt25)->pDesc->name) |
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48 | #define ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF) |
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49 | #define PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25)) |
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50 | #define BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25)) |
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51 | #define PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25)) |
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52 | #define BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd) |
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53 | |
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54 | /*---------------------------------------------------------------------------- |
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55 | * Local definitions |
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56 | *----------------------------------------------------------------------------*/ |
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57 | |
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58 | /** Device is protected, operation cannot be carried out. */ |
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59 | #define ERROR_PROTECTED 1 |
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60 | /** Device is busy executing a command. */ |
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61 | #define ERROR_BUSY 2 |
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62 | /** There was a problem while trying to program page data. */ |
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63 | #define ERROR_PROGRAM 3 |
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64 | /** There was an SPI communication error. */ |
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65 | #define ERROR_SPI 4 |
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66 | |
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67 | /** Device ready/busy status bit. */ |
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68 | #define STATUS_RDYBSY (1 << 0) |
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69 | /** Device is ready. */ |
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70 | #define STATUS_RDYBSY_READY (0 << 0) |
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71 | /** Device is busy with internal operations. */ |
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72 | #define STATUS_RDYBSY_BUSY (1 << 0) |
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73 | /** Write enable latch status bit. */ |
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74 | #define STATUS_WEL (1 << 1) |
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75 | /** Device is not write enabled. */ |
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76 | #define STATUS_WEL_DISABLED (0 << 1) |
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77 | /** Device is write enabled. */ |
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78 | #define STATUS_WEL_ENABLED (1 << 1) |
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79 | /** Software protection status bit-field. */ |
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80 | #define STATUS_SWP (3 << 2) |
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81 | /** All sectors are software protected. */ |
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82 | #define STATUS_SWP_PROTALL (3 << 2) |
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83 | /** Some sectors are software protected. */ |
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84 | #define STATUS_SWP_PROTSOME (1 << 2) |
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85 | /** No sector is software protected. */ |
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86 | #define STATUS_SWP_PROTNONE (0 << 2) |
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87 | /** Write protect pin status bit. */ |
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88 | #define STATUS_WPP (1 << 4) |
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89 | /** Write protect signal is not asserted. */ |
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90 | #define STATUS_WPP_NOTASSERTED (0 << 4) |
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91 | /** Write protect signal is asserted. */ |
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92 | #define STATUS_WPP_ASSERTED (1 << 4) |
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93 | /** Erase/program error bit. */ |
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94 | #define STATUS_EPE (1 << 5) |
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95 | /** Erase or program operation was successful. */ |
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96 | #define STATUS_EPE_SUCCESS (0 << 5) |
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97 | /** Erase or program error detected. */ |
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98 | #define STATUS_EPE_ERROR (1 << 5) |
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99 | /** Sector protection registers locked bit. */ |
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100 | #define STATUS_SPRL (1 << 7) |
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101 | /** Sector protection registers are unlocked. */ |
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102 | #define STATUS_SPRL_UNLOCKED (0 << 7) |
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103 | /** Sector protection registers are locked. */ |
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104 | #define STATUS_SPRL_LOCKED (1 << 7) |
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105 | |
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106 | /** Quad enable bit */ |
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107 | #define STATUS_QUAD_ENABLE (1 << 1) |
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108 | /** Quad enable bit */ |
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109 | #define STATUS_WRAP_ENABLE (0 << 4) |
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110 | |
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111 | /** Latency control bits */ |
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112 | #define STATUS_LATENCY_CTRL (0xF << 0) |
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113 | |
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114 | #define STATUS_WRAP_BYTE (1 << 5) |
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115 | |
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116 | #define BLOCK_PROTECT_Msk (7 << 2) |
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117 | |
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118 | #define TOP_BTM_PROTECT_Msk (1 << 5) |
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119 | |
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120 | #define SEC_PROTECT_Msk (1 << 6) |
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121 | |
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122 | #define CHIP_PROTECT_Msk (0x1F << 2) |
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123 | |
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124 | /** Read array command code. */ |
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125 | #define READ_ARRAY 0x0B |
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126 | /** Read array (low frequency) command code. */ |
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127 | #define READ_ARRAY_LF 0x03 |
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128 | /** Fast Read array command code. */ |
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129 | #define READ_ARRAY_DUAL 0x3B |
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130 | /** Fast Read array command code. */ |
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131 | #define READ_ARRAY_QUAD 0x6B |
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132 | /** Fast Read array command code. */ |
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133 | #define READ_ARRAY_DUAL_IO 0xBB |
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134 | /** Fast Read array command code. */ |
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135 | #define READ_ARRAY_QUAD_IO 0xEB |
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136 | /** Block erase command code (4K block). */ |
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137 | #define BLOCK_ERASE_4K 0x20 |
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138 | /** Block erase command code (32K block). */ |
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139 | #define BLOCK_ERASE_32K 0x52 |
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140 | /** Block erase command code (64K block). */ |
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141 | #define BLOCK_ERASE_64K 0xD8 |
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142 | /** Chip erase command code 1. */ |
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143 | #define CHIP_ERASE_1 0x60 |
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144 | /** Chip erase command code 2. */ |
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145 | #define CHIP_ERASE_2 0xC7 |
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146 | /** Byte/page program command code. */ |
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147 | #define BYTE_PAGE_PROGRAM 0x02 |
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148 | /** Sequential program mode command code 1. */ |
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149 | #define SEQUENTIAL_PROGRAM_1 0xAD |
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150 | /** Sequential program mode command code 2. */ |
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151 | #define SEQUENTIAL_PROGRAM_2 0xAF |
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152 | /** Write enable command code. */ |
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153 | #define WRITE_ENABLE 0x06 |
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154 | /** Write disable command code. */ |
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155 | #define WRITE_DISABLE 0x04 |
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156 | /** Protect sector command code. */ |
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157 | #define PROTECT_SECTOR 0x36 |
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158 | /** Unprotected sector command code. */ |
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159 | #define UNPROTECT_SECTOR 0x39 |
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160 | /** Read sector protection registers command code. */ |
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161 | #define READ_SECTOR_PROT 0x3C |
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162 | /** Read status register command code. */ |
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163 | #define READ_STATUS_1 0x05 |
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164 | /** Read status register command code. */ |
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165 | #define READ_STATUS_2 0x35 |
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166 | /** Read status register command code. */ |
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167 | #define READ_STATUS_3 0x33 |
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168 | /** Write status register command code. */ |
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169 | #define WRITE_STATUS 0x01 |
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170 | /** Read manufacturer and device ID command code. */ |
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171 | #define READ_JEDEC_ID 0x9F |
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172 | /** Deep power-down command code. */ |
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173 | #define DEEP_PDOWN 0xB9 |
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174 | /** Resume from deep power-down command code. */ |
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175 | #define RES_DEEP_PDOWN 0xAB |
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176 | /** Resume from deep power-down command code. */ |
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177 | #define SOFT_RESET_ENABLE 0x66 |
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178 | /** Resume from deep power-down command code. */ |
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179 | #define SOFT_RESET 0x99 |
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180 | /** Resume from deep power-down command code. */ |
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181 | #define WRAP_ENABLE 0x77 |
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182 | /** Continuous Read Mode Reset command code. */ |
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183 | #define CONT_MODE_RESET 0xFF |
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184 | |
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185 | /** SPI Flash Manufacturer JEDEC ID */ |
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186 | #define ATMEL_SPI_FLASH 0x1F |
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187 | #define ST_SPI_FLASH 0x20 |
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188 | #define WINBOND_SPI_FLASH 0xEF |
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189 | #define MACRONIX_SPI_FLASH 0xC2 |
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190 | #define SST_SPI_FLASH 0xBF |
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191 | |
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192 | /*---------------------------------------------------------------------------- |
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193 | * Exported functions |
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194 | *----------------------------------------------------------------------------*/ |
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195 | |
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196 | uint32_t S25FL1D_ReadJedecId(void); |
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197 | |
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198 | void S25FL1D_InitFlashInterface(uint8_t Mode); |
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199 | |
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200 | void S25FL1D_SoftReset(void); |
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201 | |
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202 | void S25FL1D_ContReadModeReset(void); |
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203 | unsigned char S25FL1D_Unprotect(void); |
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204 | |
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205 | unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size); |
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206 | |
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207 | void S25FL1D_QuadMode(uint8_t Enable); |
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208 | |
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209 | void S25FL1D_EnableWrap(uint8_t ByetAlign); |
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210 | |
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211 | void S25FL1D_SetReadLatencyControl(uint8_t Latency); |
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212 | |
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213 | unsigned char S25FL1D_EraseChip(void); |
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214 | |
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215 | unsigned char S25FL1D_EraseSector(unsigned int address); |
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216 | |
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217 | unsigned char S25FL1D_Erase64KBlock(unsigned int address); |
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218 | |
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219 | unsigned char S25FL1D_Write( |
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220 | uint32_t *pData, |
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221 | uint32_t size, |
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222 | uint32_t address, |
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223 | uint8_t Secure); |
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224 | |
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225 | extern unsigned char S25FL1D_Read( |
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226 | uint32_t *pData, |
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227 | uint32_t size, |
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228 | uint32_t address); |
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229 | |
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230 | extern unsigned char S25FL1D_ReadDual( |
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231 | uint32_t *pData, |
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232 | uint32_t size, |
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233 | uint32_t address); |
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234 | |
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235 | extern unsigned char S25FL1D_ReadQuad( |
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236 | uint32_t *pData, |
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237 | uint32_t size, |
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238 | uint32_t address); |
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239 | |
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240 | extern unsigned char S25FL1D_ReadDualIO( |
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241 | uint32_t *pData, |
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242 | uint32_t size, |
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243 | uint32_t address, |
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244 | uint8_t ContMode, |
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245 | uint8_t Secure); |
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246 | |
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247 | extern unsigned char S25FL1D_ReadQuadIO( |
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248 | uint32_t *pData, |
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249 | uint32_t size, |
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250 | uint32_t address, |
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251 | uint8_t ContMode, |
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252 | uint8_t Secure); |
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253 | |
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254 | #endif // #ifndef S25FL1_H |
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255 | |
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