1 | /* |
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2 | * Copyright (c) 2016 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <bsp/irq.h> |
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17 | #include <bsp/fatal.h> |
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18 | #include <rtems/console.h> |
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19 | #include <rtems/seterr.h> |
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20 | |
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21 | #include <rtems/termiostypes.h> |
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22 | |
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23 | #include <chip.h> |
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24 | |
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25 | #include <unistd.h> |
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26 | |
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27 | #define UART_RX_DMA_BUF_SIZE 32l |
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28 | |
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29 | typedef struct { |
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30 | char buf[UART_RX_DMA_BUF_SIZE]; |
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31 | LinkedListDescriporView3 desc; |
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32 | } atsam_uart_rx_dma; |
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33 | |
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34 | typedef struct { |
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35 | rtems_termios_device_context base; |
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36 | Uart *regs; |
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37 | rtems_vector_number irq; |
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38 | uint32_t id; |
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39 | bool console; |
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40 | bool is_usart; |
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41 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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42 | bool transmitting; |
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43 | bool rx_dma_enabled; |
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44 | uint32_t rx_dma_channel; |
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45 | atsam_uart_rx_dma *rx_dma; |
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46 | char *volatile*rx_dma_da; |
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47 | char *rx_next_read_pos; |
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48 | #endif |
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49 | } atsam_uart_context; |
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50 | |
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51 | static atsam_uart_context atsam_usart_instances[] = { |
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52 | { |
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53 | .regs = (Uart *)USART0, |
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54 | .irq = USART0_IRQn, |
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55 | .id = ID_USART0, |
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56 | .is_usart = true, |
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57 | } |
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58 | #ifdef USART1 |
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59 | , { |
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60 | .regs = (Uart *)USART1, |
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61 | .irq = USART1_IRQn, |
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62 | .id = ID_USART1, |
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63 | .is_usart = true, |
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64 | } |
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65 | #endif |
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66 | #ifdef USART2 |
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67 | , { |
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68 | .regs = (Uart *)USART2, |
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69 | .irq = USART2_IRQn, |
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70 | .id = ID_USART2, |
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71 | .is_usart = true, |
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72 | } |
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73 | #endif |
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74 | }; |
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75 | |
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76 | static atsam_uart_context atsam_uart_instances[] = { |
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77 | { |
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78 | .regs = UART0, |
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79 | .irq = UART0_IRQn, |
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80 | .id = ID_UART0, |
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81 | .is_usart = false, |
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82 | } |
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83 | #ifdef UART1 |
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84 | , { |
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85 | .regs = UART1, |
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86 | .irq = UART1_IRQn, |
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87 | .id = ID_UART1, |
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88 | .is_usart = false, |
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89 | } |
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90 | #endif |
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91 | #ifdef UART2 |
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92 | , { |
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93 | .regs = UART2, |
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94 | .irq = UART2_IRQn, |
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95 | .id = ID_UART2, |
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96 | .is_usart = false, |
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97 | } |
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98 | #endif |
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99 | #ifdef UART3 |
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100 | , { |
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101 | .regs = UART3, |
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102 | .irq = UART3_IRQn, |
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103 | .id = ID_UART3, |
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104 | .is_usart = false, |
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105 | } |
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106 | #endif |
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107 | #ifdef UART4 |
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108 | , { |
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109 | .regs = UART4, |
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110 | .irq = UART4_IRQn, |
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111 | .id = ID_UART4, |
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112 | .is_usart = false, |
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113 | } |
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114 | #endif |
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115 | }; |
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116 | |
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117 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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118 | static void atsam_uart_interrupt(void *arg) |
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119 | { |
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120 | rtems_termios_tty *tty = arg; |
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121 | atsam_uart_context *ctx = rtems_termios_get_device_context(tty); |
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122 | Uart *regs = ctx->regs; |
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123 | uint32_t sr = regs->UART_SR; |
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124 | |
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125 | if (!ctx->rx_dma_enabled) { |
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126 | while ((sr & UART_SR_RXRDY) != 0) { |
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127 | char c = (char) regs->UART_RHR; |
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128 | |
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129 | rtems_termios_enqueue_raw_characters(tty, &c, 1); |
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130 | |
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131 | sr = regs->UART_SR; |
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132 | } |
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133 | } else { |
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134 | while (*ctx->rx_dma_da != ctx->rx_next_read_pos) { |
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135 | char c; |
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136 | |
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137 | c = *ctx->rx_next_read_pos; |
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138 | |
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139 | ++ctx->rx_next_read_pos; |
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140 | if (ctx->rx_next_read_pos >= &ctx->rx_dma->buf[UART_RX_DMA_BUF_SIZE]) { |
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141 | ctx->rx_next_read_pos = &ctx->rx_dma->buf[0]; |
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142 | } |
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143 | |
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144 | rtems_termios_enqueue_raw_characters(tty, &c, 1); |
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145 | } |
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146 | } |
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147 | |
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148 | if (ctx->transmitting && (sr & UART_SR_TXEMPTY) != 0) { |
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149 | rtems_termios_dequeue_characters(tty, 1); |
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150 | } |
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151 | } |
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152 | #endif |
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153 | |
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154 | static bool atsam_uart_set_attributes( |
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155 | rtems_termios_device_context *base, |
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156 | const struct termios *term |
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157 | ) |
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158 | { |
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159 | atsam_uart_context *ctx = (atsam_uart_context *) base; |
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160 | Uart *regs = ctx->regs; |
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161 | rtems_termios_baud_t baud; |
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162 | uint32_t mr; |
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163 | |
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164 | baud = rtems_termios_baud_to_number(term->c_ospeed); |
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165 | regs->UART_BRGR = (BOARD_MCK / baud) / 16; |
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166 | |
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167 | if ((term->c_cflag & CREAD) != 0) { |
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168 | regs->UART_CR = UART_CR_RXEN | UART_CR_TXEN; |
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169 | } else { |
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170 | regs->UART_CR = UART_CR_TXEN; |
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171 | } |
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172 | |
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173 | if (ctx->is_usart) { |
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174 | mr = US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK; |
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175 | } else { |
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176 | mr = UART_MR_FILTER_DISABLED | UART_MR_BRSRCCK_PERIPH_CLK; |
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177 | } |
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178 | |
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179 | if (ctx->is_usart) { |
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180 | switch (term->c_cflag & CSIZE) { |
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181 | case CS5: |
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182 | mr |= US_MR_CHRL_5_BIT; |
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183 | break; |
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184 | case CS6: |
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185 | mr |= US_MR_CHRL_6_BIT; |
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186 | break; |
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187 | case CS7: |
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188 | mr |= US_MR_CHRL_7_BIT; |
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189 | break; |
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190 | default: |
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191 | mr |= US_MR_CHRL_8_BIT; |
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192 | break; |
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193 | } |
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194 | } else { |
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195 | if ((term->c_cflag & CSIZE) != CS8) { |
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196 | return false; |
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197 | } |
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198 | } |
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199 | |
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200 | if ((term->c_cflag & PARENB) != 0) { |
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201 | if ((term->c_cflag & PARODD) != 0) { |
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202 | mr |= UART_MR_PAR_ODD; |
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203 | } else { |
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204 | mr |= UART_MR_PAR_EVEN; |
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205 | } |
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206 | } else { |
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207 | mr |= UART_MR_PAR_NO; |
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208 | } |
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209 | |
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210 | if (ctx->is_usart) { |
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211 | if ((term->c_cflag & CSTOPB) != 0) { |
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212 | mr |= US_MR_NBSTOP_2_BIT; |
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213 | } else { |
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214 | mr |= US_MR_NBSTOP_1_BIT; |
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215 | } |
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216 | } else { |
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217 | if ((term->c_cflag & CSTOPB) != 0) { |
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218 | return false; |
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219 | } |
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220 | } |
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221 | |
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222 | regs->UART_MR = mr; |
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223 | |
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224 | return true; |
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225 | } |
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226 | |
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227 | static void atsam_uart_disable_rx_dma(atsam_uart_context *ctx) |
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228 | { |
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229 | if (ctx->rx_dma) { |
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230 | rtems_cache_coherent_free(ctx->rx_dma); |
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231 | ctx->rx_dma = NULL; |
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232 | } |
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233 | |
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234 | if (ctx->rx_dma_channel != XDMAD_ALLOC_FAILED) { |
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235 | XDMAD_FreeChannel(&XDMAD_Instance, ctx->rx_dma_channel); |
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236 | } |
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237 | |
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238 | ctx->rx_dma_enabled = false; |
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239 | } |
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240 | |
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241 | static rtems_status_code atsam_uart_enable_rx_dma(atsam_uart_context *ctx) |
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242 | { |
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243 | eXdmadRC rc; |
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244 | int channel_id; |
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245 | |
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246 | if (ctx->rx_dma_enabled) { |
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247 | return RTEMS_SUCCESSFUL; |
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248 | } |
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249 | |
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250 | /* |
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251 | * Make sure everything is in a clean default state so that the cleanup works |
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252 | * in an error case. |
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253 | */ |
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254 | ctx->rx_dma = NULL; |
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255 | ctx->rx_dma_channel = XDMAD_ALLOC_FAILED; |
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256 | |
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257 | ctx->rx_dma = rtems_cache_coherent_allocate(sizeof(*ctx->rx_dma), 0, 0); |
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258 | if (ctx->rx_dma == NULL) { |
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259 | atsam_uart_disable_rx_dma(ctx); |
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260 | return RTEMS_NO_MEMORY; |
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261 | } |
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262 | |
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263 | ctx->rx_next_read_pos = &ctx->rx_dma->buf[0]; |
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264 | |
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265 | ctx->rx_dma_channel = XDMAD_AllocateChannel( |
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266 | &XDMAD_Instance, |
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267 | XDMAD_TRANSFER_MEMORY, |
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268 | ctx->id |
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269 | ); |
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270 | |
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271 | if (ctx->rx_dma_channel == XDMAD_ALLOC_FAILED) { |
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272 | atsam_uart_disable_rx_dma(ctx); |
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273 | return RTEMS_IO_ERROR; |
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274 | } |
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275 | |
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276 | rc = XDMAD_PrepareChannel(&XDMAD_Instance, ctx->rx_dma_channel); |
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277 | if (rc != XDMAD_OK) { |
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278 | atsam_uart_disable_rx_dma(ctx); |
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279 | return RTEMS_IO_ERROR; |
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280 | } |
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281 | |
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282 | channel_id = ctx->rx_dma_channel & 0xff; |
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283 | ctx->rx_dma_da = |
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284 | (char *volatile*) &XDMAD_Instance.pXdmacs->XDMAC_CHID[channel_id].XDMAC_CDA; |
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285 | |
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286 | ctx->rx_dma->desc.mbr_nda = (uint32_t)&ctx->rx_dma->desc; |
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287 | ctx->rx_dma->desc.mbr_ubc = |
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288 | 1 | |
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289 | XDMA_UBC_NVIEW_NDV3 | |
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290 | XDMA_UBC_NDE_FETCH_EN | |
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291 | XDMA_UBC_NDEN_UPDATED | |
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292 | XDMA_UBC_NSEN_UPDATED; |
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293 | ctx->rx_dma->desc.mbr_sa = (uint32_t) &ctx->regs->UART_RHR; |
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294 | ctx->rx_dma->desc.mbr_da = (uint32_t) &ctx->rx_dma->buf[0]; |
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295 | ctx->rx_dma->desc.mbr_cfg = |
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296 | XDMAC_CC_TYPE_PER_TRAN | |
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297 | XDMAC_CC_MBSIZE_SINGLE | |
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298 | XDMAC_CC_DSYNC_PER2MEM | |
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299 | XDMAC_CC_SWREQ_HWR_CONNECTED | |
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300 | XDMAC_CC_MEMSET_NORMAL_MODE | |
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301 | XDMAC_CC_CSIZE_CHK_1 | |
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302 | XDMAC_CC_DWIDTH_BYTE | |
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303 | XDMAC_CC_SIF_AHB_IF1 | |
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304 | XDMAC_CC_DIF_AHB_IF1 | |
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305 | XDMAC_CC_SAM_FIXED_AM | |
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306 | XDMAC_CC_DAM_UBS_AM | |
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307 | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ctx->id, XDMAD_TRANSFER_RX)); |
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308 | ctx->rx_dma->desc.mbr_bc = UART_RX_DMA_BUF_SIZE - 1; |
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309 | ctx->rx_dma->desc.mbr_ds = 0; |
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310 | ctx->rx_dma->desc.mbr_sus = 0; |
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311 | ctx->rx_dma->desc.mbr_dus = 0; |
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312 | |
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313 | rc = XDMAD_ConfigureTransfer( |
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314 | &XDMAD_Instance, |
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315 | ctx->rx_dma_channel, |
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316 | NULL, |
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317 | XDMAC_CNDC_NDE_DSCR_FETCH_EN | |
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318 | XDMAC_CNDC_NDVIEW_NDV3 | |
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319 | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED | |
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320 | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED, |
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321 | (uint32_t)&ctx->rx_dma->desc, |
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322 | 0); |
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323 | if (rc != XDMAD_OK) { |
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324 | atsam_uart_disable_rx_dma(ctx); |
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325 | return RTEMS_IO_ERROR; |
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326 | } |
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327 | |
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328 | rc = XDMAD_StartTransfer(&XDMAD_Instance, ctx->rx_dma_channel); |
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329 | if (rc != XDMAD_OK) { |
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330 | atsam_uart_disable_rx_dma(ctx); |
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331 | return RTEMS_IO_ERROR; |
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332 | } |
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333 | |
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334 | ctx->rx_dma_enabled = true; |
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335 | |
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336 | return RTEMS_SUCCESSFUL; |
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337 | } |
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338 | |
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339 | static bool atsam_uart_first_open( |
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340 | rtems_termios_tty *tty, |
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341 | rtems_termios_device_context *base, |
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342 | struct termios *term, |
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343 | rtems_libio_open_close_args_t *args |
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344 | ) |
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345 | { |
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346 | atsam_uart_context *ctx = (atsam_uart_context *) base; |
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347 | Uart *regs = ctx->regs; |
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348 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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349 | rtems_status_code sc; |
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350 | #endif |
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351 | |
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352 | regs->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RSTSTA; |
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353 | regs->UART_IDR = 0xffffffff; |
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354 | |
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355 | PMC_EnablePeripheral(ctx->id); |
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356 | |
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357 | rtems_termios_set_initial_baud(tty, ATSAM_CONSOLE_BAUD); |
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358 | atsam_uart_set_attributes(base, term); |
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359 | |
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360 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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361 | regs->UART_IER = UART_IDR_RXRDY; |
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362 | sc = rtems_interrupt_handler_install( |
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363 | ctx->irq, |
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364 | ctx->is_usart ? "USART" : "UART", |
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365 | RTEMS_INTERRUPT_SHARED, |
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366 | atsam_uart_interrupt, |
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367 | tty |
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368 | ); |
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369 | if (sc != RTEMS_SUCCESSFUL) { |
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370 | return false; |
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371 | } |
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372 | #endif |
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373 | |
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374 | return true; |
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375 | } |
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376 | |
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377 | static void atsam_uart_last_close( |
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378 | rtems_termios_tty *tty, |
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379 | rtems_termios_device_context *base, |
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380 | rtems_libio_open_close_args_t *args |
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381 | ) |
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382 | { |
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383 | atsam_uart_context *ctx = (atsam_uart_context *) base; |
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384 | |
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385 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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386 | rtems_interrupt_handler_remove(ctx->irq, atsam_uart_interrupt, tty); |
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387 | #endif |
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388 | |
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389 | if (ctx->rx_dma_enabled) { |
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390 | atsam_uart_disable_rx_dma(ctx); |
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391 | } |
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392 | |
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393 | if (!ctx->console) { |
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394 | PMC_DisablePeripheral(ctx->id); |
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395 | } |
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396 | } |
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397 | |
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398 | static void atsam_uart_write( |
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399 | rtems_termios_device_context *base, |
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400 | const char *buf, |
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401 | size_t len |
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402 | ) |
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403 | { |
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404 | atsam_uart_context *ctx = (atsam_uart_context *) base; |
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405 | Uart *regs = ctx->regs; |
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406 | |
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407 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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408 | if (len > 0) { |
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409 | ctx->transmitting = true; |
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410 | regs->UART_THR = buf[0]; |
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411 | regs->UART_IER = UART_IDR_TXEMPTY; |
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412 | } else { |
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413 | ctx->transmitting = false; |
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414 | regs->UART_IDR = UART_IDR_TXEMPTY; |
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415 | } |
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416 | #else |
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417 | size_t i; |
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418 | |
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419 | for (i = 0; i < len; ++i) { |
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420 | while ((regs->UART_SR & UART_SR_TXEMPTY) == 0) { |
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421 | /* Wait */ |
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422 | } |
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423 | |
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424 | regs->UART_THR = buf[i]; |
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425 | } |
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426 | #endif |
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427 | } |
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428 | |
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429 | #ifndef ATSAM_CONSOLE_USE_INTERRUPTS |
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430 | static int atsam_uart_read(rtems_termios_device_context *base) |
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431 | { |
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432 | atsam_uart_context *ctx = (atsam_uart_context *) base; |
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433 | Uart *regs = ctx->regs; |
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434 | |
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435 | if ((regs->UART_SR & UART_SR_RXRDY) != 0) { |
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436 | return (char) regs->UART_RHR; |
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437 | } else { |
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438 | return -1; |
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439 | } |
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440 | } |
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441 | #endif |
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442 | |
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443 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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444 | static int atsam_uart_ioctl( |
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445 | rtems_termios_device_context *base, |
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446 | ioctl_command_t request, |
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447 | void *buffer |
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448 | ) |
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449 | { |
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450 | atsam_uart_context *ctx = (atsam_uart_context *) base; |
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451 | rtems_status_code sc; |
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452 | |
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453 | switch (request) { |
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454 | case ATSAM_UART_ENABLE_RX_DMA: |
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455 | sc = atsam_uart_enable_rx_dma(ctx); |
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456 | if (sc != RTEMS_SUCCESSFUL) { |
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457 | rtems_set_errno_and_return_minus_one(EIO); |
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458 | } else { |
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459 | ctx->rx_dma_enabled = true; |
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460 | } |
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461 | break; |
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462 | default: |
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463 | rtems_set_errno_and_return_minus_one(EINVAL); |
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464 | } |
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465 | |
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466 | return 0; |
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467 | } |
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468 | #endif |
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469 | |
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470 | static const rtems_termios_device_handler atsam_uart_handler = { |
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471 | .first_open = atsam_uart_first_open, |
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472 | .last_close = atsam_uart_last_close, |
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473 | .write = atsam_uart_write, |
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474 | .set_attributes = atsam_uart_set_attributes, |
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475 | #ifdef ATSAM_CONSOLE_USE_INTERRUPTS |
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476 | .mode = TERMIOS_IRQ_DRIVEN, |
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477 | .ioctl = atsam_uart_ioctl, |
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478 | #else |
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479 | .poll_read = atsam_uart_read, |
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480 | .mode = TERMIOS_POLLED |
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481 | #endif |
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482 | }; |
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483 | |
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484 | rtems_status_code console_initialize( |
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485 | rtems_device_major_number major, |
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486 | rtems_device_minor_number minor, |
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487 | void *arg |
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488 | ) |
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489 | { |
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490 | size_t i; |
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491 | |
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492 | rtems_termios_initialize(); |
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493 | |
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494 | for (i = 0; i < RTEMS_ARRAY_SIZE(atsam_usart_instances); ++i) { |
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495 | char usart[] = "/dev/ttyUSARTX"; |
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496 | |
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497 | usart[sizeof(usart) - 2] = (char) ('0' + i); |
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498 | rtems_termios_device_install( |
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499 | &usart[0], |
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500 | &atsam_uart_handler, |
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501 | NULL, |
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502 | &atsam_usart_instances[i].base |
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503 | ); |
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504 | |
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505 | #if ATSAM_CONSOLE_DEVICE_TYPE == 0 |
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506 | if (i == ATSAM_CONSOLE_DEVICE_INDEX) { |
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507 | atsam_usart_instances[i].console = true; |
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508 | link(&usart[0], CONSOLE_DEVICE_NAME); |
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509 | } |
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510 | #endif |
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511 | } |
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512 | |
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513 | for (i = 0; i < RTEMS_ARRAY_SIZE(atsam_uart_instances); ++i) { |
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514 | char uart[] = "/dev/ttyUARTX"; |
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515 | |
---|
516 | uart[sizeof(uart) - 2] = (char) ('0' + i); |
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517 | rtems_termios_device_install( |
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518 | &uart[0], |
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519 | &atsam_uart_handler, |
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520 | NULL, |
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521 | &atsam_uart_instances[i].base |
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522 | ); |
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523 | |
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524 | #if ATSAM_CONSOLE_DEVICE_TYPE == 1 |
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525 | if (i == ATSAM_CONSOLE_DEVICE_INDEX) { |
---|
526 | atsam_uart_instances[i].console = true; |
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527 | link(&uart[0], CONSOLE_DEVICE_NAME); |
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528 | } |
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529 | #endif |
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530 | } |
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531 | |
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532 | return RTEMS_SUCCESSFUL; |
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533 | } |
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