1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMSBSPsARMCycV |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <bsp/bootcard.h> |
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16 | #include <bsp/fdt.h> |
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17 | #include <bsp/irq-generic.h> |
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18 | #include <bsp/linker-symbols.h> |
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19 | |
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20 | #include <bsp/alt_clock_manager.h> |
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21 | |
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22 | #include <libfdt.h> |
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23 | |
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24 | #ifdef BSP_FDT_IS_SUPPORTED |
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25 | uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) |
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26 | { |
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27 | return intr[1] + 32; |
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28 | } |
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29 | |
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30 | static void set_clock( |
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31 | const void *fdt, |
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32 | int parent, |
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33 | ALT_CLK_t clk, |
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34 | const char *name |
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35 | ) |
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36 | { |
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37 | int node; |
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38 | int len; |
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39 | const uint32_t *val; |
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40 | |
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41 | node = fdt_subnode_offset(fdt, parent, name); |
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42 | val = fdt_getprop(fdt, node, "clock-frequency", &len); |
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43 | |
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44 | if (val != NULL && len >= 4) { |
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45 | alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0])); |
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46 | } |
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47 | } |
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48 | |
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49 | static void set_clock_by_output_name( |
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50 | const void *fdt, |
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51 | ALT_CLK_t clk, |
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52 | const char *clock_output_name |
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53 | ) |
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54 | { |
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55 | int node; |
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56 | int len; |
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57 | const uint32_t *val; |
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58 | |
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59 | node = fdt_node_offset_by_prop_value( |
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60 | fdt, |
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61 | -1, |
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62 | "clock-output-names", |
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63 | clock_output_name, |
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64 | strlen(clock_output_name) + 1 |
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65 | ); |
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66 | val = fdt_getprop(fdt, node, "clock-frequency", &len); |
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67 | |
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68 | if (val != NULL && len >= 4) { |
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69 | alt_clk_ext_clk_freq_set(clk, fdt32_to_cpu(val[0])); |
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70 | } |
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71 | } |
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72 | |
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73 | static void update_clocks(void) |
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74 | { |
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75 | const void *fdt; |
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76 | int parent; |
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77 | |
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78 | fdt = bsp_fdt_get(); |
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79 | |
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80 | /* Try to set by node name */ |
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81 | parent = fdt_node_offset_by_compatible(fdt, -1, "altr,clk-mgr"); |
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82 | parent = fdt_subnode_offset(fdt, parent, "clocks"); |
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83 | set_clock(fdt, parent, ALT_CLK_OSC1, "osc1"); |
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84 | set_clock(fdt, parent, ALT_CLK_IN_PIN_OSC2, "osc2"); |
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85 | set_clock(fdt, parent, ALT_CLK_F2H_PERIPH_REF, "f2s_periph_ref_clk"); |
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86 | set_clock(fdt, parent, ALT_CLK_F2H_SDRAM_REF, "f2s_sdram_ref_clk"); |
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87 | |
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88 | /* Try to set by "clock-output-names" property value */ |
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89 | set_clock_by_output_name(fdt, ALT_CLK_OSC1, "hps_0_eosc1-clk"); |
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90 | set_clock_by_output_name(fdt, ALT_CLK_IN_PIN_OSC2, "hps_0_eosc2-clk"); |
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91 | set_clock_by_output_name(fdt, ALT_CLK_F2H_PERIPH_REF, "hps_0_f2s_periph_ref_clk-clk"); |
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92 | set_clock_by_output_name(fdt, ALT_CLK_F2H_SDRAM_REF, "hps_0_f2s_sdram_ref_clk-clk"); |
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93 | } |
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94 | #endif |
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95 | |
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96 | #ifdef ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK |
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97 | uint32_t altera_cyclone_v_a9mpcore_periphclk; |
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98 | #endif |
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99 | |
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100 | void bsp_start(void) |
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101 | { |
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102 | #ifdef BSP_FDT_IS_SUPPORTED |
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103 | update_clocks(); |
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104 | #endif |
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105 | #ifdef ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK |
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106 | alt_clk_freq_get(ALT_CLK_MPU_PERIPH, &altera_cyclone_v_a9mpcore_periphclk); |
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107 | #endif |
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108 | bsp_interrupt_initialize(); |
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109 | rtems_cache_coherent_add_area( |
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110 | bsp_section_nocacheheap_begin, |
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111 | (uintptr_t) bsp_section_nocacheheap_size |
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112 | ); |
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113 | } |
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